drm/sprd/sprd_dpu.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2020 Unisoc Inc.
0004  */
0005
0006 #ifndef __SPRD_DPU_H__
0007 #define __SPRD_DPU_H__
0008
0009 #include <linux/bug.h>
0010 #include <linux/delay.h>
0011 #include <linux/device.h>
0012 #include <linux/kernel.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/string.h>
0015 #include <video/videomode.h>
0016
0017 #include <drm/drm_crtc.h>
0018 #include <drm/drm_fourcc.h>
0019 #include <drm/drm_print.h>
0020 #include <drm/drm_vblank.h>
0021 #include <uapi/drm/drm_mode.h>
0022
0023 /* DPU Layer registers offset */
0024 #define DPU_LAY_REG_OFFSET  0x30
0025
0026 enum {
0027     SPRD_DPU_IF_DPI,
0028     SPRD_DPU_IF_EDPI,
0029     SPRD_DPU_IF_LIMIT
0030 };
0031
0032 /**
0033  * Sprd DPU context structure
0034  *
0035  * @base: DPU controller base address
0036  * @irq: IRQ number to install the handler for
0037  * @if_type: The type of DPI interface, default is DPI mode.
0038  * @vm: videomode structure to use for DPU and DPI initialization
0039  * @stopped: indicates whether DPU are stopped
0040  * @wait_queue: wait queue, used to wait for DPU shadow register update done and
0041  * DPU stop register done interrupt signal.
0042  * @evt_update: wait queue condition for DPU shadow register
0043  * @evt_stop: wait queue condition for DPU stop register
0044  */
0045 struct dpu_context {
0046     void __iomem *base;
0047     int irq;
0048     u8 if_type;
0049     struct videomode vm;
0050     bool stopped;
0051     wait_queue_head_t wait_queue;
0052     bool evt_update;
0053     bool evt_stop;
0054 };
0055
0056 /**
0057  * Sprd DPU device structure
0058  *
0059  * @crtc: crtc object
0060  * @drm: A point to drm device
0061  * @ctx: DPU's implementation specific context object
0062  */
0063 struct sprd_dpu {
0064     struct drm_crtc base;
0065     struct drm_device *drm;
0066     struct dpu_context ctx;
0067 };
0068
0069 static inline struct sprd_dpu *to_sprd_crtc(struct drm_crtc *crtc)
0070 {
0071     return container_of(crtc, struct sprd_dpu, base);
0072 }
0073
0074 static inline void
0075 dpu_reg_set(struct dpu_context *ctx, u32 offset, u32 set_bits)
0076 {
0077     u32 bits = readl_relaxed(ctx->base + offset);
0078
0079     writel(bits | set_bits, ctx->base + offset);
0080 }
0081
0082 static inline void
0083 dpu_reg_clr(struct dpu_context *ctx, u32 offset, u32 clr_bits)
0084 {
0085     u32 bits = readl_relaxed(ctx->base + offset);
0086
0087     writel(bits & ~clr_bits, ctx->base + offset);
0088 }
0089
0090 static inline u32
0091 layer_reg_rd(struct dpu_context *ctx, u32 offset, int index)
0092 {
0093     u32 layer_offset = offset + index * DPU_LAY_REG_OFFSET;
0094
0095     return readl(ctx->base + layer_offset);
0096 }
0097
0098 static inline void
0099 layer_reg_wr(struct dpu_context *ctx, u32 offset, u32 cfg_bits, int index)
0100 {
0101     u32 layer_offset =  offset + index * DPU_LAY_REG_OFFSET;
0102
0103     writel(cfg_bits, ctx->base + layer_offset);
0104 }
0105
0106 void sprd_dpu_run(struct sprd_dpu *dpu);
0107 void sprd_dpu_stop(struct sprd_dpu *dpu);
0108
0109 #endif