drm/shmobile/shmob_drm_regs.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * shmob_drm_regs.h  --  SH Mobile DRM registers
0004  *
0005  * Copyright (C) 2012 Renesas Electronics Corporation
0006  *
0007  * Laurent Pinchart (laurent.pinchart@ideasonboard.com)
0008  */
0009
0010 #ifndef __SHMOB_DRM_REGS_H__
0011 #define __SHMOB_DRM_REGS_H__
0012
0013 #include <linux/io.h>
0014 #include <linux/jiffies.h>
0015
0016 #include "shmob_drm_drv.h"
0017
0018 /* Register definitions */
0019 #define LDDCKPAT1R      0x400
0020 #define LDDCKPAT2R      0x404
0021 #define LDDCKR          0x410
0022 #define LDDCKR_ICKSEL_BUS   (0 << 16)
0023 #define LDDCKR_ICKSEL_MIPI  (1 << 16)
0024 #define LDDCKR_ICKSEL_HDMI  (2 << 16)
0025 #define LDDCKR_ICKSEL_EXT   (3 << 16)
0026 #define LDDCKR_ICKSEL_MASK  (7 << 16)
0027 #define LDDCKR_MOSEL        (1 << 6)
0028 #define LDDCKSTPR       0x414
0029 #define LDDCKSTPR_DCKSTS    (1 << 16)
0030 #define LDDCKSTPR_DCKSTP    (1 << 0)
0031 #define LDMT1R          0x418
0032 #define LDMT1R_VPOL     (1 << 28)
0033 #define LDMT1R_HPOL     (1 << 27)
0034 #define LDMT1R_DWPOL        (1 << 26)
0035 #define LDMT1R_DIPOL        (1 << 25)
0036 #define LDMT1R_DAPOL        (1 << 24)
0037 #define LDMT1R_HSCNT        (1 << 17)
0038 #define LDMT1R_DWCNT        (1 << 16)
0039 #define LDMT1R_IFM      (1 << 12)
0040 #define LDMT1R_MIFTYP_RGB8  (0x0 << 0)
0041 #define LDMT1R_MIFTYP_RGB9  (0x4 << 0)
0042 #define LDMT1R_MIFTYP_RGB12A    (0x5 << 0)
0043 #define LDMT1R_MIFTYP_RGB12B    (0x6 << 0)
0044 #define LDMT1R_MIFTYP_RGB16 (0x7 << 0)
0045 #define LDMT1R_MIFTYP_RGB18 (0xa << 0)
0046 #define LDMT1R_MIFTYP_RGB24 (0xb << 0)
0047 #define LDMT1R_MIFTYP_YCBCR (0xf << 0)
0048 #define LDMT1R_MIFTYP_SYS8A (0x0 << 0)
0049 #define LDMT1R_MIFTYP_SYS8B (0x1 << 0)
0050 #define LDMT1R_MIFTYP_SYS8C (0x2 << 0)
0051 #define LDMT1R_MIFTYP_SYS8D (0x3 << 0)
0052 #define LDMT1R_MIFTYP_SYS9  (0x4 << 0)
0053 #define LDMT1R_MIFTYP_SYS12 (0x5 << 0)
0054 #define LDMT1R_MIFTYP_SYS16A    (0x7 << 0)
0055 #define LDMT1R_MIFTYP_SYS16B    (0x8 << 0)
0056 #define LDMT1R_MIFTYP_SYS16C    (0x9 << 0)
0057 #define LDMT1R_MIFTYP_SYS18 (0xa << 0)
0058 #define LDMT1R_MIFTYP_SYS24 (0xb << 0)
0059 #define LDMT1R_MIFTYP_MASK  (0xf << 0)
0060 #define LDMT2R          0x41c
0061 #define LDMT2R_CSUP_MASK    (7 << 26)
0062 #define LDMT2R_CSUP_SHIFT   26
0063 #define LDMT2R_RSV      (1 << 25)
0064 #define LDMT2R_VSEL     (1 << 24)
0065 #define LDMT2R_WCSC_MASK    (0xff << 16)
0066 #define LDMT2R_WCSC_SHIFT   16
0067 #define LDMT2R_WCEC_MASK    (0xff << 8)
0068 #define LDMT2R_WCEC_SHIFT   8
0069 #define LDMT2R_WCLW_MASK    (0xff << 0)
0070 #define LDMT2R_WCLW_SHIFT   0
0071 #define LDMT3R          0x420
0072 #define LDMT3R_RDLC_MASK    (0x3f << 24)
0073 #define LDMT3R_RDLC_SHIFT   24
0074 #define LDMT3R_RCSC_MASK    (0xff << 16)
0075 #define LDMT3R_RCSC_SHIFT   16
0076 #define LDMT3R_RCEC_MASK    (0xff << 8)
0077 #define LDMT3R_RCEC_SHIFT   8
0078 #define LDMT3R_RCLW_MASK    (0xff << 0)
0079 #define LDMT3R_RCLW_SHIFT   0
0080 #define LDDFR           0x424
0081 #define LDDFR_CF1       (1 << 18)
0082 #define LDDFR_CF0       (1 << 17)
0083 #define LDDFR_CC        (1 << 16)
0084 #define LDDFR_YF_420        (0 << 8)
0085 #define LDDFR_YF_422        (1 << 8)
0086 #define LDDFR_YF_444        (2 << 8)
0087 #define LDDFR_YF_MASK       (3 << 8)
0088 #define LDDFR_PKF_ARGB32    (0x00 << 0)
0089 #define LDDFR_PKF_RGB16     (0x03 << 0)
0090 #define LDDFR_PKF_RGB24     (0x0b << 0)
0091 #define LDDFR_PKF_MASK      (0x1f << 0)
0092 #define LDSM1R          0x428
0093 #define LDSM1R_OS       (1 << 0)
0094 #define LDSM2R          0x42c
0095 #define LDSM2R_OSTRG        (1 << 0)
0096 #define LDSA1R          0x430
0097 #define LDSA2R          0x434
0098 #define LDMLSR          0x438
0099 #define LDWBFR          0x43c
0100 #define LDWBCNTR        0x440
0101 #define LDWBAR          0x444
0102 #define LDHCNR          0x448
0103 #define LDHSYNR         0x44c
0104 #define LDVLNR          0x450
0105 #define LDVSYNR         0x454
0106 #define LDHPDR          0x458
0107 #define LDVPDR          0x45c
0108 #define LDPMR           0x460
0109 #define LDPMR_LPS       (3 << 0)
0110 #define LDINTR          0x468
0111 #define LDINTR_FE       (1 << 10)
0112 #define LDINTR_VSE      (1 << 9)
0113 #define LDINTR_VEE      (1 << 8)
0114 #define LDINTR_FS       (1 << 2)
0115 #define LDINTR_VSS      (1 << 1)
0116 #define LDINTR_VES      (1 << 0)
0117 #define LDINTR_STATUS_MASK  (0xff << 0)
0118 #define LDSR            0x46c
0119 #define LDSR_MSS        (1 << 10)
0120 #define LDSR_MRS        (1 << 8)
0121 #define LDSR_AS         (1 << 1)
0122 #define LDCNT1R         0x470
0123 #define LDCNT1R_DE      (1 << 0)
0124 #define LDCNT2R         0x474
0125 #define LDCNT2R_BR      (1 << 8)
0126 #define LDCNT2R_MD      (1 << 3)
0127 #define LDCNT2R_SE      (1 << 2)
0128 #define LDCNT2R_ME      (1 << 1)
0129 #define LDCNT2R_DO      (1 << 0)
0130 #define LDRCNTR         0x478
0131 #define LDRCNTR_SRS     (1 << 17)
0132 #define LDRCNTR_SRC     (1 << 16)
0133 #define LDRCNTR_MRS     (1 << 1)
0134 #define LDRCNTR_MRC     (1 << 0)
0135 #define LDDDSR          0x47c
0136 #define LDDDSR_LS       (1 << 2)
0137 #define LDDDSR_WS       (1 << 1)
0138 #define LDDDSR_BS       (1 << 0)
0139 #define LDHAJR          0x4a0
0140
0141 #define LDDWD0R         0x800
0142 #define LDDWDxR_WDACT       (1 << 28)
0143 #define LDDWDxR_RSW     (1 << 24)
0144 #define LDDRDR          0x840
0145 #define LDDRDR_RSR      (1 << 24)
0146 #define LDDRDR_DRD_MASK     (0x3ffff << 0)
0147 #define LDDWAR          0x900
0148 #define LDDWAR_WA       (1 << 0)
0149 #define LDDRAR          0x904
0150 #define LDDRAR_RA       (1 << 0)
0151
0152 #define LDBCR           0xb00
0153 #define LDBCR_UPC(n)        (1 << ((n) + 16))
0154 #define LDBCR_UPF(n)        (1 << ((n) + 8))
0155 #define LDBCR_UPD(n)        (1 << ((n) + 0))
0156 #define LDBnBSIFR(n)        (0xb20 + (n) * 0x20 + 0x00)
0157 #define LDBBSIFR_EN     (1 << 31)
0158 #define LDBBSIFR_VS     (1 << 29)
0159 #define LDBBSIFR_BRSEL      (1 << 28)
0160 #define LDBBSIFR_MX     (1 << 27)
0161 #define LDBBSIFR_MY     (1 << 26)
0162 #define LDBBSIFR_CV3        (3 << 24)
0163 #define LDBBSIFR_CV2        (2 << 24)
0164 #define LDBBSIFR_CV1        (1 << 24)
0165 #define LDBBSIFR_CV0        (0 << 24)
0166 #define LDBBSIFR_CV_MASK    (3 << 24)
0167 #define LDBBSIFR_LAY_MASK   (0xff << 16)
0168 #define LDBBSIFR_LAY_SHIFT  16
0169 #define LDBBSIFR_ROP3_MASK  (0xff << 16)
0170 #define LDBBSIFR_ROP3_SHIFT 16
0171 #define LDBBSIFR_AL_PL8     (3 << 14)
0172 #define LDBBSIFR_AL_PL1     (2 << 14)
0173 #define LDBBSIFR_AL_PK      (1 << 14)
0174 #define LDBBSIFR_AL_1       (0 << 14)
0175 #define LDBBSIFR_AL_MASK    (3 << 14)
0176 #define LDBBSIFR_SWPL       (1 << 10)
0177 #define LDBBSIFR_SWPW       (1 << 9)
0178 #define LDBBSIFR_SWPB       (1 << 8)
0179 #define LDBBSIFR_RY     (1 << 7)
0180 #define LDBBSIFR_CHRR_420   (2 << 0)
0181 #define LDBBSIFR_CHRR_422   (1 << 0)
0182 #define LDBBSIFR_CHRR_444   (0 << 0)
0183 #define LDBBSIFR_RPKF_ARGB32    (0x00 << 0)
0184 #define LDBBSIFR_RPKF_RGB16 (0x03 << 0)
0185 #define LDBBSIFR_RPKF_RGB24 (0x0b << 0)
0186 #define LDBBSIFR_RPKF_MASK  (0x1f << 0)
0187 #define LDBnBSSZR(n)        (0xb20 + (n) * 0x20 + 0x04)
0188 #define LDBBSSZR_BVSS_MASK  (0xfff << 16)
0189 #define LDBBSSZR_BVSS_SHIFT 16
0190 #define LDBBSSZR_BHSS_MASK  (0xfff << 0)
0191 #define LDBBSSZR_BHSS_SHIFT 0
0192 #define LDBnBLOCR(n)        (0xb20 + (n) * 0x20 + 0x08)
0193 #define LDBBLOCR_CVLC_MASK  (0xfff << 16)
0194 #define LDBBLOCR_CVLC_SHIFT 16
0195 #define LDBBLOCR_CHLC_MASK  (0xfff << 0)
0196 #define LDBBLOCR_CHLC_SHIFT 0
0197 #define LDBnBSMWR(n)        (0xb20 + (n) * 0x20 + 0x0c)
0198 #define LDBBSMWR_BSMWA_MASK (0xffff << 16)
0199 #define LDBBSMWR_BSMWA_SHIFT    16
0200 #define LDBBSMWR_BSMW_MASK  (0xffff << 0)
0201 #define LDBBSMWR_BSMW_SHIFT 0
0202 #define LDBnBSAYR(n)        (0xb20 + (n) * 0x20 + 0x10)
0203 #define LDBBSAYR_FG1A_MASK  (0xff << 24)
0204 #define LDBBSAYR_FG1A_SHIFT 24
0205 #define LDBBSAYR_FG1R_MASK  (0xff << 16)
0206 #define LDBBSAYR_FG1R_SHIFT 16
0207 #define LDBBSAYR_FG1G_MASK  (0xff << 8)
0208 #define LDBBSAYR_FG1G_SHIFT 8
0209 #define LDBBSAYR_FG1B_MASK  (0xff << 0)
0210 #define LDBBSAYR_FG1B_SHIFT 0
0211 #define LDBnBSACR(n)        (0xb20 + (n) * 0x20 + 0x14)
0212 #define LDBBSACR_FG2A_MASK  (0xff << 24)
0213 #define LDBBSACR_FG2A_SHIFT 24
0214 #define LDBBSACR_FG2R_MASK  (0xff << 16)
0215 #define LDBBSACR_FG2R_SHIFT 16
0216 #define LDBBSACR_FG2G_MASK  (0xff << 8)
0217 #define LDBBSACR_FG2G_SHIFT 8
0218 #define LDBBSACR_FG2B_MASK  (0xff << 0)
0219 #define LDBBSACR_FG2B_SHIFT 0
0220 #define LDBnBSAAR(n)        (0xb20 + (n) * 0x20 + 0x18)
0221 #define LDBBSAAR_AP_MASK    (0xff << 24)
0222 #define LDBBSAAR_AP_SHIFT   24
0223 #define LDBBSAAR_R_MASK     (0xff << 16)
0224 #define LDBBSAAR_R_SHIFT    16
0225 #define LDBBSAAR_GY_MASK    (0xff << 8)
0226 #define LDBBSAAR_GY_SHIFT   8
0227 #define LDBBSAAR_B_MASK     (0xff << 0)
0228 #define LDBBSAAR_B_SHIFT    0
0229 #define LDBnBPPCR(n)        (0xb20 + (n) * 0x20 + 0x1c)
0230 #define LDBBPPCR_AP_MASK    (0xff << 24)
0231 #define LDBBPPCR_AP_SHIFT   24
0232 #define LDBBPPCR_R_MASK     (0xff << 16)
0233 #define LDBBPPCR_R_SHIFT    16
0234 #define LDBBPPCR_GY_MASK    (0xff << 8)
0235 #define LDBBPPCR_GY_SHIFT   8
0236 #define LDBBPPCR_B_MASK     (0xff << 0)
0237 #define LDBBPPCR_B_SHIFT    0
0238 #define LDBnBBGCL(n)        (0xb10 + (n) * 0x04)
0239 #define LDBBBGCL_BGA_MASK   (0xff << 24)
0240 #define LDBBBGCL_BGA_SHIFT  24
0241 #define LDBBBGCL_BGR_MASK   (0xff << 16)
0242 #define LDBBBGCL_BGR_SHIFT  16
0243 #define LDBBBGCL_BGG_MASK   (0xff << 8)
0244 #define LDBBBGCL_BGG_SHIFT  8
0245 #define LDBBBGCL_BGB_MASK   (0xff << 0)
0246 #define LDBBBGCL_BGB_SHIFT  0
0247
0248 #define LCDC_SIDE_B_OFFSET  0x1000
0249 #define LCDC_MIRROR_OFFSET  0x2000
0250
0251 static inline bool lcdc_is_banked(u32 reg)
0252 {
0253     switch (reg) {
0254     case LDMT1R:
0255     case LDMT2R:
0256     case LDMT3R:
0257     case LDDFR:
0258     case LDSM1R:
0259     case LDSA1R:
0260     case LDSA2R:
0261     case LDMLSR:
0262     case LDWBFR:
0263     case LDWBCNTR:
0264     case LDWBAR:
0265     case LDHCNR:
0266     case LDHSYNR:
0267     case LDVLNR:
0268     case LDVSYNR:
0269     case LDHPDR:
0270     case LDVPDR:
0271     case LDHAJR:
0272         return true;
0273     default:
0274         return reg >= LDBnBBGCL(0) && reg <= LDBnBPPCR(3);
0275     }
0276 }
0277
0278 static inline void lcdc_write_mirror(struct shmob_drm_device *sdev, u32 reg,
0279                      u32 data)
0280 {
0281     iowrite32(data, sdev->mmio + reg + LCDC_MIRROR_OFFSET);
0282 }
0283
0284 static inline void lcdc_write(struct shmob_drm_device *sdev, u32 reg, u32 data)
0285 {
0286     iowrite32(data, sdev->mmio + reg);
0287     if (lcdc_is_banked(reg))
0288         iowrite32(data, sdev->mmio + reg + LCDC_SIDE_B_OFFSET);
0289 }
0290
0291 static inline u32 lcdc_read(struct shmob_drm_device *sdev, u32 reg)
0292 {
0293     return ioread32(sdev->mmio + reg);
0294 }
0295
0296 static inline int lcdc_wait_bit(struct shmob_drm_device *sdev, u32 reg,
0297                 u32 mask, u32 until)
0298 {
0299     unsigned long timeout = jiffies + msecs_to_jiffies(5);
0300
0301     while ((lcdc_read(sdev, reg) & mask) != until) {
0302         if (time_after(jiffies, timeout))
0303             return -ETIMEDOUT;
0304         cpu_relax();
0305     }
0306
0307     return 0;
0308 }
0309
0310 #endif /* __SHMOB_DRM_REGS_H__ */