drm/savage/savage_drv.h

0001 /* savage_drv.h -- Private header for the savage driver */
0002 /*
0003  * Copyright 2004  Felix Kuehling
0004  * All Rights Reserved.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sub license,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice (including the
0014  * next paragraph) shall be included in all copies or substantial portions
0015  * of the Software.
0016  *
0017  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0018  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0019  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0020  * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
0021  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
0022  * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
0023  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0024  */
0025
0026 #ifndef __SAVAGE_DRV_H__
0027 #define __SAVAGE_DRV_H__
0028
0029 #include <linux/io.h>
0030
0031 #include <drm/drm_ioctl.h>
0032 #include <drm/drm_legacy.h>
0033 #include <drm/savage_drm.h>
0034
0035 #define DRIVER_AUTHOR   "Felix Kuehling"
0036
0037 #define DRIVER_NAME "savage"
0038 #define DRIVER_DESC "Savage3D/MX/IX, Savage4, SuperSavage, Twister, ProSavage[DDR]"
0039 #define DRIVER_DATE "20050313"
0040
0041 #define DRIVER_MAJOR        2
0042 #define DRIVER_MINOR        4
0043 #define DRIVER_PATCHLEVEL   1
0044 /* Interface history:
0045  *
0046  * 1.x   The DRM driver from the VIA/S3 code drop, basically a dummy
0047  * 2.0   The first real DRM
0048  * 2.1   Scissors registers managed by the DRM, 3D operations clipped by
0049  *       cliprects of the cmdbuf ioctl
0050  * 2.2   Implemented SAVAGE_CMD_DMA_IDX and SAVAGE_CMD_VB_IDX
0051  * 2.3   Event counters used by BCI_EVENT_EMIT/WAIT ioctls are now 32 bits
0052  *       wide and thus very long lived (unlikely to ever wrap). The size
0053  *       in the struct was 32 bits before, but only 16 bits were used
0054  * 2.4   Implemented command DMA. Now drm_savage_init_t.cmd_dma_offset is
0055  *       actually used
0056  */
0057
0058 typedef struct drm_savage_age {
0059     uint16_t event;
0060     unsigned int wrap;
0061 } drm_savage_age_t;
0062
0063 typedef struct drm_savage_buf_priv {
0064     struct drm_savage_buf_priv *next;
0065     struct drm_savage_buf_priv *prev;
0066     drm_savage_age_t age;
0067     struct drm_buf *buf;
0068 } drm_savage_buf_priv_t;
0069
0070 typedef struct drm_savage_dma_page {
0071     drm_savage_age_t age;
0072     unsigned int used, flushed;
0073 } drm_savage_dma_page_t;
0074 #define SAVAGE_DMA_PAGE_SIZE 1024   /* in dwords */
0075 /* Fake DMA buffer size in bytes. 4 pages. Allows a maximum command
0076  * size of 16kbytes or 4k entries. Minimum requirement would be
0077  * 10kbytes for 255 40-byte vertices in one drawing command. */
0078 #define SAVAGE_FAKE_DMA_SIZE (SAVAGE_DMA_PAGE_SIZE*4*4)
0079
0080 /* interesting bits of hardware state that are saved in dev_priv */
0081 typedef union {
0082     struct drm_savage_common_state {
0083         uint32_t vbaddr;
0084     } common;
0085     struct {
0086         unsigned char pad[sizeof(struct drm_savage_common_state)];
0087         uint32_t texctrl, texaddr;
0088         uint32_t scstart, new_scstart;
0089         uint32_t scend, new_scend;
0090     } s3d;
0091     struct {
0092         unsigned char pad[sizeof(struct drm_savage_common_state)];
0093         uint32_t texdescr, texaddr0, texaddr1;
0094         uint32_t drawctrl0, new_drawctrl0;
0095         uint32_t drawctrl1, new_drawctrl1;
0096     } s4;
0097 } drm_savage_state_t;
0098
0099 /* these chip tags should match the ones in the 2D driver in savage_regs.h. */
0100 enum savage_family {
0101     S3_UNKNOWN = 0,
0102     S3_SAVAGE3D,
0103     S3_SAVAGE_MX,
0104     S3_SAVAGE4,
0105     S3_PROSAVAGE,
0106     S3_TWISTER,
0107     S3_PROSAVAGEDDR,
0108     S3_SUPERSAVAGE,
0109     S3_SAVAGE2000,
0110     S3_LAST
0111 };
0112
0113 extern const struct drm_ioctl_desc savage_ioctls[];
0114 extern int savage_max_ioctl;
0115
0116 #define S3_SAVAGE3D_SERIES(chip)  ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
0117
0118 #define S3_SAVAGE4_SERIES(chip)  ((chip==S3_SAVAGE4)            \
0119                                   || (chip==S3_PROSAVAGE)       \
0120                                   || (chip==S3_TWISTER)         \
0121                                   || (chip==S3_PROSAVAGEDDR))
0122
0123 #define S3_SAVAGE_MOBILE_SERIES(chip)   ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))
0124
0125 #define S3_SAVAGE_SERIES(chip)    ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
0126
0127 #define S3_MOBILE_TWISTER_SERIES(chip)   ((chip==S3_TWISTER)    \
0128                                           ||(chip==S3_PROSAVAGEDDR))
0129
0130 /* flags */
0131 #define SAVAGE_IS_AGP 1
0132
0133 typedef struct drm_savage_private {
0134     drm_savage_sarea_t *sarea_priv;
0135
0136     drm_savage_buf_priv_t head, tail;
0137
0138     /* who am I? */
0139     enum savage_family chipset;
0140
0141     unsigned int cob_size;
0142     unsigned int bci_threshold_lo, bci_threshold_hi;
0143     unsigned int dma_type;
0144
0145     /* frame buffer layout */
0146     unsigned int fb_bpp;
0147     unsigned int front_offset, front_pitch;
0148     unsigned int back_offset, back_pitch;
0149     unsigned int depth_bpp;
0150     unsigned int depth_offset, depth_pitch;
0151
0152     /* bitmap descriptors for swap and clear */
0153     unsigned int front_bd, back_bd, depth_bd;
0154
0155     /* local textures */
0156     unsigned int texture_offset;
0157     unsigned int texture_size;
0158
0159     /* memory regions in physical memory */
0160     drm_local_map_t *sarea;
0161     drm_local_map_t *mmio;
0162     drm_local_map_t *fb;
0163     drm_local_map_t *aperture;
0164     drm_local_map_t *status;
0165     drm_local_map_t *agp_textures;
0166     drm_local_map_t *cmd_dma;
0167     drm_local_map_t fake_dma;
0168
0169     int mtrr_handles[3];
0170
0171     /* BCI and status-related stuff */
0172     volatile uint32_t *status_ptr, *bci_ptr;
0173     uint32_t status_used_mask;
0174     uint16_t event_counter;
0175     unsigned int event_wrap;
0176
0177     /* Savage4 command DMA */
0178     drm_savage_dma_page_t *dma_pages;
0179     unsigned int nr_dma_pages, first_dma_page, current_dma_page;
0180     drm_savage_age_t last_dma_age;
0181
0182     /* saved hw state for global/local check on S3D */
0183     uint32_t hw_draw_ctrl, hw_zbuf_ctrl;
0184     /* and for scissors (global, so don't emit if not changed) */
0185     uint32_t hw_scissors_start, hw_scissors_end;
0186
0187     drm_savage_state_t state;
0188
0189     /* after emitting a wait cmd Savage3D needs 63 nops before next DMA */
0190     unsigned int waiting;
0191
0192     /* config/hardware-dependent function pointers */
0193     int (*wait_fifo) (struct drm_savage_private * dev_priv, unsigned int n);
0194     int (*wait_evnt) (struct drm_savage_private * dev_priv, uint16_t e);
0195     /* Err, there is a macro wait_event in include/linux/wait.h.
0196      * Avoid unwanted macro expansion. */
0197     void (*emit_clip_rect) (struct drm_savage_private * dev_priv,
0198                 const struct drm_clip_rect * pbox);
0199     void (*dma_flush) (struct drm_savage_private * dev_priv);
0200 } drm_savage_private_t;
0201
0202 /* ioctls */
0203 extern int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv);
0204 extern int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
0205
0206 /* BCI functions */
0207 extern uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv,
0208                       unsigned int flags);
0209 extern void savage_freelist_put(struct drm_device * dev, struct drm_buf * buf);
0210 extern void savage_dma_reset(drm_savage_private_t * dev_priv);
0211 extern void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page);
0212 extern uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv,
0213                   unsigned int n);
0214 extern int savage_driver_load(struct drm_device *dev, unsigned long chipset);
0215 extern int savage_driver_firstopen(struct drm_device *dev);
0216 extern void savage_driver_lastclose(struct drm_device *dev);
0217 extern void savage_driver_unload(struct drm_device *dev);
0218 extern void savage_reclaim_buffers(struct drm_device *dev,
0219                    struct drm_file *file_priv);
0220
0221 /* state functions */
0222 extern void savage_emit_clip_rect_s3d(drm_savage_private_t * dev_priv,
0223                       const struct drm_clip_rect * pbox);
0224 extern void savage_emit_clip_rect_s4(drm_savage_private_t * dev_priv,
0225                      const struct drm_clip_rect * pbox);
0226
0227 #define SAVAGE_FB_SIZE_S3   0x01000000  /*  16MB */
0228 #define SAVAGE_FB_SIZE_S4   0x02000000  /*  32MB */
0229 #define SAVAGE_MMIO_SIZE        0x00080000  /* 512kB */
0230 #define SAVAGE_APERTURE_OFFSET  0x02000000  /*  32MB */
0231 #define SAVAGE_APERTURE_SIZE    0x05000000  /* 5 tiled surfaces, 16MB each */
0232
0233 #define SAVAGE_BCI_OFFSET       0x00010000  /* offset of the BCI region
0234                          * inside the MMIO region */
0235 #define SAVAGE_BCI_FIFO_SIZE    32  /* number of entries in on-chip
0236                      * BCI FIFO */
0237
0238 /*
0239  * MMIO registers
0240  */
0241 #define SAVAGE_STATUS_WORD0     0x48C00
0242 #define SAVAGE_STATUS_WORD1     0x48C04
0243 #define SAVAGE_ALT_STATUS_WORD0     0x48C60
0244
0245 #define SAVAGE_FIFO_USED_MASK_S3D   0x0001ffff
0246 #define SAVAGE_FIFO_USED_MASK_S4    0x001fffff
0247
0248 /* Copied from savage_bci.h in the 2D driver with some renaming. */
0249
0250 /* Bitmap descriptors */
0251 #define SAVAGE_BD_STRIDE_SHIFT 0
0252 #define SAVAGE_BD_BPP_SHIFT   16
0253 #define SAVAGE_BD_TILE_SHIFT  24
0254 #define SAVAGE_BD_BW_DISABLE  (1<<28)
0255 /* common: */
0256 #define SAVAGE_BD_TILE_LINEAR       0
0257 /* savage4, MX, IX, 3D */
0258 #define SAVAGE_BD_TILE_16BPP        2
0259 #define SAVAGE_BD_TILE_32BPP        3
0260 /* twister, prosavage, DDR, supersavage, 2000 */
0261 #define SAVAGE_BD_TILE_DEST     1
0262 #define SAVAGE_BD_TILE_TEXTURE      2
0263 /* GBD - BCI enable */
0264 /* savage4, MX, IX, 3D */
0265 #define SAVAGE_GBD_BCI_ENABLE                    8
0266 /* twister, prosavage, DDR, supersavage, 2000 */
0267 #define SAVAGE_GBD_BCI_ENABLE_TWISTER            0
0268
0269 #define SAVAGE_GBD_BIG_ENDIAN                    4
0270 #define SAVAGE_GBD_LITTLE_ENDIAN                 0
0271 #define SAVAGE_GBD_64                            1
0272
0273 /*  Global Bitmap Descriptor */
0274 #define SAVAGE_BCI_GLB_BD_LOW             0x8168
0275 #define SAVAGE_BCI_GLB_BD_HIGH            0x816C
0276
0277 /*
0278  * BCI registers
0279  */
0280 /* Savage4/Twister/ProSavage 3D registers */
0281 #define SAVAGE_DRAWLOCALCTRL_S4     0x1e
0282 #define SAVAGE_TEXPALADDR_S4        0x1f
0283 #define SAVAGE_TEXCTRL0_S4      0x20
0284 #define SAVAGE_TEXCTRL1_S4      0x21
0285 #define SAVAGE_TEXADDR0_S4      0x22
0286 #define SAVAGE_TEXADDR1_S4      0x23
0287 #define SAVAGE_TEXBLEND0_S4     0x24
0288 #define SAVAGE_TEXBLEND1_S4     0x25
0289 #define SAVAGE_TEXXPRCLR_S4     0x26    /* never used */
0290 #define SAVAGE_TEXDESCR_S4      0x27
0291 #define SAVAGE_FOGTABLE_S4      0x28
0292 #define SAVAGE_FOGCTRL_S4       0x30
0293 #define SAVAGE_STENCILCTRL_S4       0x31
0294 #define SAVAGE_ZBUFCTRL_S4      0x32
0295 #define SAVAGE_ZBUFOFF_S4       0x33
0296 #define SAVAGE_DESTCTRL_S4      0x34
0297 #define SAVAGE_DRAWCTRL0_S4     0x35
0298 #define SAVAGE_DRAWCTRL1_S4     0x36
0299 #define SAVAGE_ZWATERMARK_S4        0x37
0300 #define SAVAGE_DESTTEXRWWATERMARK_S4    0x38
0301 #define SAVAGE_TEXBLENDCOLOR_S4     0x39
0302 /* Savage3D/MX/IX 3D registers */
0303 #define SAVAGE_TEXPALADDR_S3D       0x18
0304 #define SAVAGE_TEXXPRCLR_S3D        0x19    /* never used */
0305 #define SAVAGE_TEXADDR_S3D      0x1A
0306 #define SAVAGE_TEXDESCR_S3D     0x1B
0307 #define SAVAGE_TEXCTRL_S3D      0x1C
0308 #define SAVAGE_FOGTABLE_S3D     0x20
0309 #define SAVAGE_FOGCTRL_S3D      0x30
0310 #define SAVAGE_DRAWCTRL_S3D     0x31
0311 #define SAVAGE_ZBUFCTRL_S3D     0x32
0312 #define SAVAGE_ZBUFOFF_S3D      0x33
0313 #define SAVAGE_DESTCTRL_S3D     0x34
0314 #define SAVAGE_SCSTART_S3D      0x35
0315 #define SAVAGE_SCEND_S3D        0x36
0316 #define SAVAGE_ZWATERMARK_S3D       0x37
0317 #define SAVAGE_DESTTEXRWWATERMARK_S3D   0x38
0318 /* common stuff */
0319 #define SAVAGE_VERTBUFADDR      0x3e
0320 #define SAVAGE_BITPLANEWTMASK       0xd7
0321 #define SAVAGE_DMABUFADDR       0x51
0322
0323 /* texture enable bits (needed for tex addr checking) */
0324 #define SAVAGE_TEXCTRL_TEXEN_MASK   0x00010000  /* S3D */
0325 #define SAVAGE_TEXDESCR_TEX0EN_MASK 0x02000000  /* S4 */
0326 #define SAVAGE_TEXDESCR_TEX1EN_MASK 0x04000000  /* S4 */
0327
0328 /* Global fields in Savage4/Twister/ProSavage 3D registers:
0329  *
0330  * All texture registers and DrawLocalCtrl are local. All other
0331  * registers are global. */
0332
0333 /* Global fields in Savage3D/MX/IX 3D registers:
0334  *
0335  * All texture registers are local. DrawCtrl and ZBufCtrl are
0336  * partially local. All other registers are global.
0337  *
0338  * DrawCtrl global fields: cullMode, alphaTestCmpFunc, alphaTestEn, alphaRefVal
0339  * ZBufCtrl global fields: zCmpFunc, zBufEn
0340  */
0341 #define SAVAGE_DRAWCTRL_S3D_GLOBAL  0x03f3c00c
0342 #define SAVAGE_ZBUFCTRL_S3D_GLOBAL  0x00000027
0343
0344 /* Masks for scissor bits (drawCtrl[01] on s4, scissorStart/End on s3d)
0345  */
0346 #define SAVAGE_SCISSOR_MASK_S4      0x00fff7ff
0347 #define SAVAGE_SCISSOR_MASK_S3D     0x07ff07ff
0348
0349 /*
0350  * BCI commands
0351  */
0352 #define BCI_CMD_NOP                  0x40000000
0353 #define BCI_CMD_RECT                 0x48000000
0354 #define BCI_CMD_RECT_XP              0x01000000
0355 #define BCI_CMD_RECT_YP              0x02000000
0356 #define BCI_CMD_SCANLINE             0x50000000
0357 #define BCI_CMD_LINE                 0x5C000000
0358 #define BCI_CMD_LINE_LAST_PIXEL      0x58000000
0359 #define BCI_CMD_BYTE_TEXT            0x63000000
0360 #define BCI_CMD_NT_BYTE_TEXT         0x67000000
0361 #define BCI_CMD_BIT_TEXT             0x6C000000
0362 #define BCI_CMD_GET_ROP(cmd)         (((cmd) >> 16) & 0xFF)
0363 #define BCI_CMD_SET_ROP(cmd, rop)    ((cmd) |= ((rop & 0xFF) << 16))
0364 #define BCI_CMD_SEND_COLOR           0x00008000
0365
0366 #define BCI_CMD_CLIP_NONE            0x00000000
0367 #define BCI_CMD_CLIP_CURRENT         0x00002000
0368 #define BCI_CMD_CLIP_LR              0x00004000
0369 #define BCI_CMD_CLIP_NEW             0x00006000
0370
0371 #define BCI_CMD_DEST_GBD             0x00000000
0372 #define BCI_CMD_DEST_PBD             0x00000800
0373 #define BCI_CMD_DEST_PBD_NEW         0x00000C00
0374 #define BCI_CMD_DEST_SBD             0x00001000
0375 #define BCI_CMD_DEST_SBD_NEW         0x00001400
0376
0377 #define BCI_CMD_SRC_TRANSPARENT      0x00000200
0378 #define BCI_CMD_SRC_SOLID            0x00000000
0379 #define BCI_CMD_SRC_GBD              0x00000020
0380 #define BCI_CMD_SRC_COLOR            0x00000040
0381 #define BCI_CMD_SRC_MONO             0x00000060
0382 #define BCI_CMD_SRC_PBD_COLOR        0x00000080
0383 #define BCI_CMD_SRC_PBD_MONO         0x000000A0
0384 #define BCI_CMD_SRC_PBD_COLOR_NEW    0x000000C0
0385 #define BCI_CMD_SRC_PBD_MONO_NEW     0x000000E0
0386 #define BCI_CMD_SRC_SBD_COLOR        0x00000100
0387 #define BCI_CMD_SRC_SBD_MONO         0x00000120
0388 #define BCI_CMD_SRC_SBD_COLOR_NEW    0x00000140
0389 #define BCI_CMD_SRC_SBD_MONO_NEW     0x00000160
0390
0391 #define BCI_CMD_PAT_TRANSPARENT      0x00000010
0392 #define BCI_CMD_PAT_NONE             0x00000000
0393 #define BCI_CMD_PAT_COLOR            0x00000002
0394 #define BCI_CMD_PAT_MONO             0x00000003
0395 #define BCI_CMD_PAT_PBD_COLOR        0x00000004
0396 #define BCI_CMD_PAT_PBD_MONO         0x00000005
0397 #define BCI_CMD_PAT_PBD_COLOR_NEW    0x00000006
0398 #define BCI_CMD_PAT_PBD_MONO_NEW     0x00000007
0399 #define BCI_CMD_PAT_SBD_COLOR        0x00000008
0400 #define BCI_CMD_PAT_SBD_MONO         0x00000009
0401 #define BCI_CMD_PAT_SBD_COLOR_NEW    0x0000000A
0402 #define BCI_CMD_PAT_SBD_MONO_NEW     0x0000000B
0403
0404 #define BCI_BD_BW_DISABLE            0x10000000
0405 #define BCI_BD_TILE_MASK             0x03000000
0406 #define BCI_BD_TILE_NONE             0x00000000
0407 #define BCI_BD_TILE_16               0x02000000
0408 #define BCI_BD_TILE_32               0x03000000
0409 #define BCI_BD_GET_BPP(bd)           (((bd) >> 16) & 0xFF)
0410 #define BCI_BD_SET_BPP(bd, bpp)      ((bd) |= (((bpp) & 0xFF) << 16))
0411 #define BCI_BD_GET_STRIDE(bd)        ((bd) & 0xFFFF)
0412 #define BCI_BD_SET_STRIDE(bd, st)    ((bd) |= ((st) & 0xFFFF))
0413
0414 #define BCI_CMD_SET_REGISTER            0x96000000
0415
0416 #define BCI_CMD_WAIT                    0xC0000000
0417 #define BCI_CMD_WAIT_3D                 0x00010000
0418 #define BCI_CMD_WAIT_2D                 0x00020000
0419
0420 #define BCI_CMD_UPDATE_EVENT_TAG        0x98000000
0421
0422 #define BCI_CMD_DRAW_PRIM               0x80000000
0423 #define BCI_CMD_DRAW_INDEXED_PRIM       0x88000000
0424 #define BCI_CMD_DRAW_CONT               0x01000000
0425 #define BCI_CMD_DRAW_TRILIST            0x00000000
0426 #define BCI_CMD_DRAW_TRISTRIP           0x02000000
0427 #define BCI_CMD_DRAW_TRIFAN             0x04000000
0428 #define BCI_CMD_DRAW_SKIPFLAGS          0x000000ff
0429 #define BCI_CMD_DRAW_NO_Z       0x00000001
0430 #define BCI_CMD_DRAW_NO_W       0x00000002
0431 #define BCI_CMD_DRAW_NO_CD      0x00000004
0432 #define BCI_CMD_DRAW_NO_CS      0x00000008
0433 #define BCI_CMD_DRAW_NO_U0      0x00000010
0434 #define BCI_CMD_DRAW_NO_V0      0x00000020
0435 #define BCI_CMD_DRAW_NO_UV0     0x00000030
0436 #define BCI_CMD_DRAW_NO_U1      0x00000040
0437 #define BCI_CMD_DRAW_NO_V1      0x00000080
0438 #define BCI_CMD_DRAW_NO_UV1     0x000000c0
0439
0440 #define BCI_CMD_DMA         0xa8000000
0441
0442 #define BCI_W_H(w, h)                ((((h) << 16) | (w)) & 0x0FFF0FFF)
0443 #define BCI_X_Y(x, y)                ((((y) << 16) | (x)) & 0x0FFF0FFF)
0444 #define BCI_X_W(x, y)                ((((w) << 16) | (x)) & 0x0FFF0FFF)
0445 #define BCI_CLIP_LR(l, r)            ((((r) << 16) | (l)) & 0x0FFF0FFF)
0446 #define BCI_CLIP_TL(t, l)            ((((t) << 16) | (l)) & 0x0FFF0FFF)
0447 #define BCI_CLIP_BR(b, r)            ((((b) << 16) | (r)) & 0x0FFF0FFF)
0448
0449 #define BCI_LINE_X_Y(x, y)           (((y) << 16) | ((x) & 0xFFFF))
0450 #define BCI_LINE_STEPS(diag, axi)    (((axi) << 16) | ((diag) & 0xFFFF))
0451 #define BCI_LINE_MISC(maj, ym, xp, yp, err) \
0452     (((maj) & 0x1FFF) | \
0453     ((ym) ? 1<<13 : 0) | \
0454     ((xp) ? 1<<14 : 0) | \
0455     ((yp) ? 1<<15 : 0) | \
0456     ((err) << 16))
0457
0458 /*
0459  * common commands
0460  */
0461 #define BCI_SET_REGISTERS( first, n )           \
0462     BCI_WRITE(BCI_CMD_SET_REGISTER |        \
0463           ((uint32_t)(n) & 0xff) << 16 |    \
0464           ((uint32_t)(first) & 0xffff))
0465 #define DMA_SET_REGISTERS( first, n )           \
0466     DMA_WRITE(BCI_CMD_SET_REGISTER |        \
0467           ((uint32_t)(n) & 0xff) << 16 |    \
0468           ((uint32_t)(first) & 0xffff))
0469
0470 #define BCI_DRAW_PRIMITIVE(n, type, skip)         \
0471         BCI_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \
0472           ((n) << 16))
0473 #define DMA_DRAW_PRIMITIVE(n, type, skip)         \
0474         DMA_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \
0475           ((n) << 16))
0476
0477 #define BCI_DRAW_INDICES_S3D(n, type, i0)         \
0478         BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) |  \
0479           ((n) << 16) | (i0))
0480
0481 #define BCI_DRAW_INDICES_S4(n, type, skip)        \
0482         BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) |  \
0483                   (skip) | ((n) << 16))
0484
0485 #define BCI_DMA(n)  \
0486     BCI_WRITE(BCI_CMD_DMA | (((n) >> 1) - 1))
0487
0488 /*
0489  * access to MMIO
0490  */
0491 #define SAVAGE_READ(reg) \
0492        readl(((void __iomem *)dev_priv->mmio->handle) + (reg))
0493 #define SAVAGE_WRITE(reg) \
0494     writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
0495
0496 /*
0497  * access to the burst command interface (BCI)
0498  */
0499 #define SAVAGE_BCI_DEBUG 1
0500
0501 #define BCI_LOCALS    volatile uint32_t *bci_ptr;
0502
0503 #define BEGIN_BCI( n ) do {         \
0504     dev_priv->wait_fifo(dev_priv, (n)); \
0505     bci_ptr = dev_priv->bci_ptr;        \
0506 } while(0)
0507
0508 #define BCI_WRITE( val ) *bci_ptr++ = (uint32_t)(val)
0509
0510 /*
0511  * command DMA support
0512  */
0513 #define SAVAGE_DMA_DEBUG 1
0514
0515 #define DMA_LOCALS   uint32_t *dma_ptr;
0516
0517 #define BEGIN_DMA( n ) do {                     \
0518     unsigned int cur = dev_priv->current_dma_page;          \
0519     unsigned int rest = SAVAGE_DMA_PAGE_SIZE -          \
0520         dev_priv->dma_pages[cur].used;              \
0521     if ((n) > rest) {                       \
0522         dma_ptr = savage_dma_alloc(dev_priv, (n));      \
0523     } else { /* fast path for small allocations */          \
0524         dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle +   \
0525             cur * SAVAGE_DMA_PAGE_SIZE +            \
0526             dev_priv->dma_pages[cur].used;          \
0527         if (dev_priv->dma_pages[cur].used == 0)         \
0528             savage_dma_wait(dev_priv, cur);         \
0529         dev_priv->dma_pages[cur].used += (n);           \
0530     }                               \
0531 } while(0)
0532
0533 #define DMA_WRITE( val ) *dma_ptr++ = (uint32_t)(val)
0534
0535 #define DMA_COPY(src, n) do {                   \
0536     memcpy(dma_ptr, (src), (n)*4);              \
0537     dma_ptr += n;                       \
0538 } while(0)
0539
0540 #if SAVAGE_DMA_DEBUG
0541 #define DMA_COMMIT() do {                       \
0542     unsigned int cur = dev_priv->current_dma_page;          \
0543     uint32_t *expected = (uint32_t *)dev_priv->cmd_dma->handle +    \
0544             cur * SAVAGE_DMA_PAGE_SIZE +            \
0545             dev_priv->dma_pages[cur].used;          \
0546     if (dma_ptr != expected) {                  \
0547         DRM_ERROR("DMA allocation and use don't match: "    \
0548               "%p != %p\n", expected, dma_ptr);     \
0549         savage_dma_reset(dev_priv);             \
0550     }                               \
0551 } while(0)
0552 #else
0553 #define DMA_COMMIT() do {/* nothing */} while(0)
0554 #endif
0555
0556 #define DMA_FLUSH() dev_priv->dma_flush(dev_priv)
0557
0558 /* Buffer aging via event tag
0559  */
0560
0561 #define UPDATE_EVENT_COUNTER( ) do {            \
0562     if (dev_priv->status_ptr) {         \
0563         uint16_t count;             \
0564         /* coordinate with Xserver */       \
0565         count = dev_priv->status_ptr[1023]; \
0566         if (count < dev_priv->event_counter)    \
0567             dev_priv->event_wrap++;     \
0568         dev_priv->event_counter = count;    \
0569     }                       \
0570 } while(0)
0571
0572 #define SET_AGE( age, e, w ) do {   \
0573     (age)->event = e;       \
0574     (age)->wrap = w;        \
0575 } while(0)
0576
0577 #define TEST_AGE( age, e, w )               \
0578     ( (age)->wrap < (w) || ( (age)->wrap == (w) && (age)->event <= (e) ) )
0579
0580 #endif              /* __SAVAGE_DRV_H__ */