drm/rockchip/rockchip_lvds.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
0004  * Author:
0005  *      Sandy Huang <hjc@rock-chips.com>
0006  *      Mark Yao <mark.yao@rock-chips.com>
0007  */
0008
0009 #ifndef _ROCKCHIP_LVDS_
0010 #define _ROCKCHIP_LVDS_
0011
0012 #define RK3288_LVDS_CH0_REG0            0x00
0013 #define RK3288_LVDS_CH0_REG0_LVDS_EN        BIT(7)
0014 #define RK3288_LVDS_CH0_REG0_TTL_EN     BIT(6)
0015 #define RK3288_LVDS_CH0_REG0_LANECK_EN      BIT(5)
0016 #define RK3288_LVDS_CH0_REG0_LANE4_EN       BIT(4)
0017 #define RK3288_LVDS_CH0_REG0_LANE3_EN       BIT(3)
0018 #define RK3288_LVDS_CH0_REG0_LANE2_EN       BIT(2)
0019 #define RK3288_LVDS_CH0_REG0_LANE1_EN       BIT(1)
0020 #define RK3288_LVDS_CH0_REG0_LANE0_EN       BIT(0)
0021
0022 #define RK3288_LVDS_CH0_REG1            0x04
0023 #define RK3288_LVDS_CH0_REG1_LANECK_BIAS    BIT(5)
0024 #define RK3288_LVDS_CH0_REG1_LANE4_BIAS     BIT(4)
0025 #define RK3288_LVDS_CH0_REG1_LANE3_BIAS     BIT(3)
0026 #define RK3288_LVDS_CH0_REG1_LANE2_BIAS     BIT(2)
0027 #define RK3288_LVDS_CH0_REG1_LANE1_BIAS     BIT(1)
0028 #define RK3288_LVDS_CH0_REG1_LANE0_BIAS     BIT(0)
0029
0030 #define RK3288_LVDS_CH0_REG2            0x08
0031 #define RK3288_LVDS_CH0_REG2_RESERVE_ON     BIT(7)
0032 #define RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE   BIT(6)
0033 #define RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE    BIT(5)
0034 #define RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE    BIT(4)
0035 #define RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE    BIT(3)
0036 #define RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE    BIT(2)
0037 #define RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE    BIT(1)
0038 #define RK3288_LVDS_CH0_REG2_PLL_FBDIV8     BIT(0)
0039
0040 #define RK3288_LVDS_CH0_REG3            0x0c
0041 #define RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK 0xff
0042
0043 #define RK3288_LVDS_CH0_REG4            0x10
0044 #define RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE    BIT(5)
0045 #define RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE BIT(4)
0046 #define RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE BIT(3)
0047 #define RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE BIT(2)
0048 #define RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE BIT(1)
0049 #define RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE BIT(0)
0050
0051 #define RK3288_LVDS_CH0_REG5            0x14
0052 #define RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA    BIT(5)
0053 #define RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA BIT(4)
0054 #define RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA BIT(3)
0055 #define RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA BIT(2)
0056 #define RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA BIT(1)
0057 #define RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA BIT(0)
0058
0059 #define RK3288_LVDS_CFG_REGC            0x30
0060 #define RK3288_LVDS_CFG_REGC_PLL_ENABLE     0x00
0061 #define RK3288_LVDS_CFG_REGC_PLL_DISABLE    0xff
0062
0063 #define RK3288_LVDS_CH0_REGD            0x34
0064 #define RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK    0x1f
0065
0066 #define RK3288_LVDS_CH0_REG20           0x80
0067 #define RK3288_LVDS_CH0_REG20_MSB       0x45
0068 #define RK3288_LVDS_CH0_REG20_LSB       0x44
0069
0070 #define RK3288_LVDS_CFG_REG21           0x84
0071 #define RK3288_LVDS_CFG_REG21_TX_ENABLE     0x92
0072 #define RK3288_LVDS_CFG_REG21_TX_DISABLE    0x00
0073 #define RK3288_LVDS_CH1_OFFSET          0x100
0074
0075 #define RK3288_LVDS_GRF_SOC_CON6        0x025C
0076 #define RK3288_LVDS_GRF_SOC_CON7        0x0260
0077
0078 /* fbdiv value is split over 2 registers, with bit8 in reg2 */
0079 #define RK3288_LVDS_PLL_FBDIV_REG2(_fbd) \
0080         (_fbd & BIT(8) ? RK3288_LVDS_CH0_REG2_PLL_FBDIV8 : 0)
0081 #define RK3288_LVDS_PLL_FBDIV_REG3(_fbd) \
0082         (_fbd & RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK)
0083 #define RK3288_LVDS_PLL_PREDIV_REGD(_pd) \
0084         (_pd & RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK)
0085
0086 #define RK3288_LVDS_SOC_CON6_SEL_VOP_LIT    BIT(3)
0087
0088 #define LVDS_FMT_MASK               (0x07 << 16)
0089 #define LVDS_MSB                BIT(3)
0090 #define LVDS_DUAL               BIT(4)
0091 #define LVDS_FMT_1              BIT(5)
0092 #define LVDS_TTL_EN             BIT(6)
0093 #define LVDS_START_PHASE_RST_1          BIT(7)
0094 #define LVDS_DCLK_INV               BIT(8)
0095 #define LVDS_CH0_EN             BIT(11)
0096 #define LVDS_CH1_EN             BIT(12)
0097 #define LVDS_PWRDN              BIT(15)
0098
0099 #define LVDS_24BIT              (0 << 1)
0100 #define LVDS_18BIT              (1 << 1)
0101 #define LVDS_FORMAT_VESA            (0 << 0)
0102 #define LVDS_FORMAT_JEIDA           (1 << 0)
0103
0104 #define LVDS_VESA_24                0
0105 #define LVDS_JEIDA_24               1
0106 #define LVDS_VESA_18                2
0107 #define LVDS_JEIDA_18               3
0108
0109 #define HIWORD_UPDATE(v, h, l)  ((GENMASK(h, l) << 16) | ((v) << (l)))
0110
0111 #define PX30_LVDS_GRF_PD_VO_CON0        0x434
0112 #define   PX30_LVDS_TIE_CLKS(val)       HIWORD_UPDATE(val,  8,  8)
0113 #define   PX30_LVDS_INVERT_CLKS(val)        HIWORD_UPDATE(val,  9,  9)
0114 #define   PX30_LVDS_INVERT_DCLK(val)        HIWORD_UPDATE(val,  5,  5)
0115
0116 #define PX30_LVDS_GRF_PD_VO_CON1        0x438
0117 #define   PX30_LVDS_FORMAT(val)         HIWORD_UPDATE(val, 14, 13)
0118 #define   PX30_LVDS_MODE_EN(val)        HIWORD_UPDATE(val, 12, 12)
0119 #define   PX30_LVDS_MSBSEL(val)         HIWORD_UPDATE(val, 11, 11)
0120 #define   PX30_LVDS_P2S_EN(val)         HIWORD_UPDATE(val,  6,  6)
0121 #define   PX30_LVDS_VOP_SEL(val)        HIWORD_UPDATE(val,  1,  1)
0122
0123 #endif /* _ROCKCHIP_LVDS_ */