drm/rockchip/rockchip_drm_vop.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
0004  * Author:Mark Yao <mark.yao@rock-chips.com>
0005  */
0006
0007 #ifndef _ROCKCHIP_DRM_VOP_H
0008 #define _ROCKCHIP_DRM_VOP_H
0009
0010 /*
0011  * major: IP major version, used for IP structure
0012  * minor: big feature change under same structure
0013  */
0014 #define VOP_VERSION(major, minor)   ((major) << 8 | (minor))
0015 #define VOP_MAJOR(version)      ((version) >> 8)
0016 #define VOP_MINOR(version)      ((version) & 0xff)
0017
0018 #define NUM_YUV2YUV_COEFFICIENTS 12
0019
0020 /* AFBC supports a number of configurable modes. Relevant to us is block size
0021  * (16x16 or 32x8), storage modifiers (SPARSE, SPLIT), and the YUV-like
0022  * colourspace transform (YTR). 16x16 SPARSE mode is always used. SPLIT mode
0023  * could be enabled via the hreg_block_split register, but is not currently
0024  * handled. The colourspace transform is implicitly always assumed by the
0025  * decoder, so consumers must use this transform as well.
0026  *
0027  * Failure to match modifiers will cause errors displaying AFBC buffers
0028  * produced by conformant AFBC producers, including Mesa.
0029  */
0030 #define ROCKCHIP_AFBC_MOD \
0031     DRM_FORMAT_MOD_ARM_AFBC( \
0032         AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | AFBC_FORMAT_MOD_SPARSE \
0033             | AFBC_FORMAT_MOD_YTR \
0034     )
0035
0036 enum vop_data_format {
0037     VOP_FMT_ARGB8888 = 0,
0038     VOP_FMT_RGB888,
0039     VOP_FMT_RGB565,
0040     VOP_FMT_YUV420SP = 4,
0041     VOP_FMT_YUV422SP,
0042     VOP_FMT_YUV444SP,
0043 };
0044
0045 struct vop_reg {
0046     uint32_t mask;
0047     uint16_t offset;
0048     uint8_t shift;
0049     bool write_mask;
0050     bool relaxed;
0051 };
0052
0053 struct vop_afbc {
0054     struct vop_reg enable;
0055     struct vop_reg win_sel;
0056     struct vop_reg format;
0057     struct vop_reg rb_swap;
0058     struct vop_reg uv_swap;
0059     struct vop_reg auto_gating_en;
0060     struct vop_reg block_split_en;
0061     struct vop_reg pic_vir_width;
0062     struct vop_reg tile_num;
0063     struct vop_reg hreg_block_split;
0064     struct vop_reg pic_offset;
0065     struct vop_reg pic_size;
0066     struct vop_reg dsp_offset;
0067     struct vop_reg transform_offset;
0068     struct vop_reg hdr_ptr;
0069     struct vop_reg half_block_en;
0070     struct vop_reg xmirror;
0071     struct vop_reg ymirror;
0072     struct vop_reg rotate_270;
0073     struct vop_reg rotate_90;
0074     struct vop_reg rstn;
0075 };
0076
0077 struct vop_modeset {
0078     struct vop_reg htotal_pw;
0079     struct vop_reg hact_st_end;
0080     struct vop_reg hpost_st_end;
0081     struct vop_reg vtotal_pw;
0082     struct vop_reg vact_st_end;
0083     struct vop_reg vpost_st_end;
0084 };
0085
0086 struct vop_output {
0087     struct vop_reg pin_pol;
0088     struct vop_reg dp_pin_pol;
0089     struct vop_reg dp_dclk_pol;
0090     struct vop_reg edp_pin_pol;
0091     struct vop_reg edp_dclk_pol;
0092     struct vop_reg hdmi_pin_pol;
0093     struct vop_reg hdmi_dclk_pol;
0094     struct vop_reg mipi_pin_pol;
0095     struct vop_reg mipi_dclk_pol;
0096     struct vop_reg rgb_pin_pol;
0097     struct vop_reg rgb_dclk_pol;
0098     struct vop_reg dp_en;
0099     struct vop_reg edp_en;
0100     struct vop_reg hdmi_en;
0101     struct vop_reg mipi_en;
0102     struct vop_reg mipi_dual_channel_en;
0103     struct vop_reg rgb_en;
0104 };
0105
0106 struct vop_common {
0107     struct vop_reg cfg_done;
0108     struct vop_reg dsp_blank;
0109     struct vop_reg data_blank;
0110     struct vop_reg pre_dither_down;
0111     struct vop_reg dither_down_sel;
0112     struct vop_reg dither_down_mode;
0113     struct vop_reg dither_down_en;
0114     struct vop_reg dither_up;
0115     struct vop_reg dsp_lut_en;
0116     struct vop_reg gate_en;
0117     struct vop_reg mmu_en;
0118     struct vop_reg out_mode;
0119     struct vop_reg standby;
0120 };
0121
0122 struct vop_misc {
0123     struct vop_reg global_regdone_en;
0124 };
0125
0126 struct vop_intr {
0127     const int *intrs;
0128     uint32_t nintrs;
0129
0130     struct vop_reg line_flag_num[2];
0131     struct vop_reg enable;
0132     struct vop_reg clear;
0133     struct vop_reg status;
0134 };
0135
0136 struct vop_scl_extension {
0137     struct vop_reg cbcr_vsd_mode;
0138     struct vop_reg cbcr_vsu_mode;
0139     struct vop_reg cbcr_hsd_mode;
0140     struct vop_reg cbcr_ver_scl_mode;
0141     struct vop_reg cbcr_hor_scl_mode;
0142     struct vop_reg yrgb_vsd_mode;
0143     struct vop_reg yrgb_vsu_mode;
0144     struct vop_reg yrgb_hsd_mode;
0145     struct vop_reg yrgb_ver_scl_mode;
0146     struct vop_reg yrgb_hor_scl_mode;
0147     struct vop_reg line_load_mode;
0148     struct vop_reg cbcr_axi_gather_num;
0149     struct vop_reg yrgb_axi_gather_num;
0150     struct vop_reg vsd_cbcr_gt2;
0151     struct vop_reg vsd_cbcr_gt4;
0152     struct vop_reg vsd_yrgb_gt2;
0153     struct vop_reg vsd_yrgb_gt4;
0154     struct vop_reg bic_coe_sel;
0155     struct vop_reg cbcr_axi_gather_en;
0156     struct vop_reg yrgb_axi_gather_en;
0157     struct vop_reg lb_mode;
0158 };
0159
0160 struct vop_scl_regs {
0161     const struct vop_scl_extension *ext;
0162
0163     struct vop_reg scale_yrgb_x;
0164     struct vop_reg scale_yrgb_y;
0165     struct vop_reg scale_cbcr_x;
0166     struct vop_reg scale_cbcr_y;
0167 };
0168
0169 struct vop_yuv2yuv_phy {
0170     struct vop_reg y2r_coefficients[NUM_YUV2YUV_COEFFICIENTS];
0171 };
0172
0173 struct vop_win_phy {
0174     const struct vop_scl_regs *scl;
0175     const uint32_t *data_formats;
0176     uint32_t nformats;
0177     const uint64_t *format_modifiers;
0178
0179     struct vop_reg enable;
0180     struct vop_reg gate;
0181     struct vop_reg format;
0182     struct vop_reg rb_swap;
0183     struct vop_reg uv_swap;
0184     struct vop_reg act_info;
0185     struct vop_reg dsp_info;
0186     struct vop_reg dsp_st;
0187     struct vop_reg yrgb_mst;
0188     struct vop_reg uv_mst;
0189     struct vop_reg yrgb_vir;
0190     struct vop_reg uv_vir;
0191     struct vop_reg y_mir_en;
0192     struct vop_reg x_mir_en;
0193
0194     struct vop_reg dst_alpha_ctl;
0195     struct vop_reg src_alpha_ctl;
0196     struct vop_reg alpha_pre_mul;
0197     struct vop_reg alpha_mode;
0198     struct vop_reg alpha_en;
0199     struct vop_reg channel;
0200 };
0201
0202 struct vop_win_yuv2yuv_data {
0203     uint32_t base;
0204     const struct vop_yuv2yuv_phy *phy;
0205     struct vop_reg y2r_en;
0206 };
0207
0208 struct vop_win_data {
0209     uint32_t base;
0210     const struct vop_win_phy *phy;
0211     enum drm_plane_type type;
0212 };
0213
0214 struct vop_data {
0215     uint32_t version;
0216     const struct vop_intr *intr;
0217     const struct vop_common *common;
0218     const struct vop_misc *misc;
0219     const struct vop_modeset *modeset;
0220     const struct vop_output *output;
0221     const struct vop_afbc *afbc;
0222     const struct vop_win_yuv2yuv_data *win_yuv2yuv;
0223     const struct vop_win_data *win;
0224     unsigned int win_size;
0225     unsigned int lut_size;
0226
0227 #define VOP_FEATURE_OUTPUT_RGB10    BIT(0)
0228 #define VOP_FEATURE_INTERNAL_RGB    BIT(1)
0229     u64 feature;
0230 };
0231
0232 /* interrupt define */
0233 #define DSP_HOLD_VALID_INTR     (1 << 0)
0234 #define FS_INTR             (1 << 1)
0235 #define LINE_FLAG_INTR          (1 << 2)
0236 #define BUS_ERROR_INTR          (1 << 3)
0237
0238 #define INTR_MASK           (DSP_HOLD_VALID_INTR | FS_INTR | \
0239                      LINE_FLAG_INTR | BUS_ERROR_INTR)
0240
0241 #define DSP_HOLD_VALID_INTR_EN(x)   ((x) << 4)
0242 #define FS_INTR_EN(x)           ((x) << 5)
0243 #define LINE_FLAG_INTR_EN(x)        ((x) << 6)
0244 #define BUS_ERROR_INTR_EN(x)        ((x) << 7)
0245 #define DSP_HOLD_VALID_INTR_MASK    (1 << 4)
0246 #define FS_INTR_MASK            (1 << 5)
0247 #define LINE_FLAG_INTR_MASK     (1 << 6)
0248 #define BUS_ERROR_INTR_MASK     (1 << 7)
0249
0250 #define INTR_CLR_SHIFT          8
0251 #define DSP_HOLD_VALID_INTR_CLR     (1 << (INTR_CLR_SHIFT + 0))
0252 #define FS_INTR_CLR         (1 << (INTR_CLR_SHIFT + 1))
0253 #define LINE_FLAG_INTR_CLR      (1 << (INTR_CLR_SHIFT + 2))
0254 #define BUS_ERROR_INTR_CLR      (1 << (INTR_CLR_SHIFT + 3))
0255
0256 #define DSP_LINE_NUM(x)         (((x) & 0x1fff) << 12)
0257 #define DSP_LINE_NUM_MASK       (0x1fff << 12)
0258
0259 /* src alpha ctrl define */
0260 #define SRC_FADING_VALUE(x)     (((x) & 0xff) << 24)
0261 #define SRC_GLOBAL_ALPHA(x)     (((x) & 0xff) << 16)
0262 #define SRC_FACTOR_M0(x)        (((x) & 0x7) << 6)
0263 #define SRC_ALPHA_CAL_M0(x)     (((x) & 0x1) << 5)
0264 #define SRC_BLEND_M0(x)         (((x) & 0x3) << 3)
0265 #define SRC_ALPHA_M0(x)         (((x) & 0x1) << 2)
0266 #define SRC_COLOR_M0(x)         (((x) & 0x1) << 1)
0267 #define SRC_ALPHA_EN(x)         (((x) & 0x1) << 0)
0268 /* dst alpha ctrl define */
0269 #define DST_FACTOR_M0(x)        (((x) & 0x7) << 6)
0270
0271 /*
0272  * display output interface supported by rockchip lcdc
0273  */
0274 #define ROCKCHIP_OUT_MODE_P888  0
0275 #define ROCKCHIP_OUT_MODE_P666  1
0276 #define ROCKCHIP_OUT_MODE_P565  2
0277 /* for use special outface */
0278 #define ROCKCHIP_OUT_MODE_AAAA  15
0279
0280 /* output flags */
0281 #define ROCKCHIP_OUTPUT_DSI_DUAL    BIT(0)
0282
0283 enum alpha_mode {
0284     ALPHA_STRAIGHT,
0285     ALPHA_INVERSE,
0286 };
0287
0288 enum global_blend_mode {
0289     ALPHA_GLOBAL,
0290     ALPHA_PER_PIX,
0291     ALPHA_PER_PIX_GLOBAL,
0292 };
0293
0294 enum alpha_cal_mode {
0295     ALPHA_SATURATION,
0296     ALPHA_NO_SATURATION,
0297 };
0298
0299 enum color_mode {
0300     ALPHA_SRC_PRE_MUL,
0301     ALPHA_SRC_NO_PRE_MUL,
0302 };
0303
0304 enum factor_mode {
0305     ALPHA_ZERO,
0306     ALPHA_ONE,
0307     ALPHA_SRC,
0308     ALPHA_SRC_INVERSE,
0309     ALPHA_SRC_GLOBAL,
0310 };
0311
0312 enum scale_mode {
0313     SCALE_NONE = 0x0,
0314     SCALE_UP   = 0x1,
0315     SCALE_DOWN = 0x2
0316 };
0317
0318 enum lb_mode {
0319     LB_YUV_3840X5 = 0x0,
0320     LB_YUV_2560X8 = 0x1,
0321     LB_RGB_3840X2 = 0x2,
0322     LB_RGB_2560X4 = 0x3,
0323     LB_RGB_1920X5 = 0x4,
0324     LB_RGB_1280X8 = 0x5
0325 };
0326
0327 enum sacle_up_mode {
0328     SCALE_UP_BIL = 0x0,
0329     SCALE_UP_BIC = 0x1
0330 };
0331
0332 enum scale_down_mode {
0333     SCALE_DOWN_BIL = 0x0,
0334     SCALE_DOWN_AVG = 0x1
0335 };
0336
0337 enum dither_down_mode {
0338     RGB888_TO_RGB565 = 0x0,
0339     RGB888_TO_RGB666 = 0x1
0340 };
0341
0342 enum dither_down_mode_sel {
0343     DITHER_DOWN_ALLEGRO = 0x0,
0344     DITHER_DOWN_FRC = 0x1
0345 };
0346
0347 enum vop_pol {
0348     HSYNC_POSITIVE = 0,
0349     VSYNC_POSITIVE = 1,
0350     DEN_NEGATIVE   = 2
0351 };
0352
0353 #define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
0354 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT   12
0355 #define SCL_MAX_VSKIPLINES      4
0356 #define MIN_SCL_FT_AFTER_VSKIP      1
0357
0358 static inline uint16_t scl_cal_scale(int src, int dst, int shift)
0359 {
0360     return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
0361 }
0362
0363 static inline uint16_t scl_cal_scale2(int src, int dst)
0364 {
0365     return ((src - 1) << 12) / (dst - 1);
0366 }
0367
0368 #define GET_SCL_FT_BILI_DN(src, dst)    scl_cal_scale(src, dst, 12)
0369 #define GET_SCL_FT_BILI_UP(src, dst)    scl_cal_scale(src, dst, 16)
0370 #define GET_SCL_FT_BIC(src, dst)    scl_cal_scale(src, dst, 16)
0371
0372 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
0373                          int vskiplines)
0374 {
0375     int act_height;
0376
0377     act_height = DIV_ROUND_UP(src_h, vskiplines);
0378
0379     if (act_height == dst_h)
0380         return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines;
0381
0382     return GET_SCL_FT_BILI_DN(act_height, dst_h);
0383 }
0384
0385 static inline enum scale_mode scl_get_scl_mode(int src, int dst)
0386 {
0387     if (src < dst)
0388         return SCALE_UP;
0389     else if (src > dst)
0390         return SCALE_DOWN;
0391
0392     return SCALE_NONE;
0393 }
0394
0395 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
0396 {
0397     uint32_t vskiplines;
0398
0399     for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
0400         if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
0401             break;
0402
0403     return vskiplines;
0404 }
0405
0406 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
0407 {
0408     int lb_mode;
0409
0410     if (is_yuv) {
0411         if (width > 1280)
0412             lb_mode = LB_YUV_3840X5;
0413         else
0414             lb_mode = LB_YUV_2560X8;
0415     } else {
0416         if (width > 2560)
0417             lb_mode = LB_RGB_3840X2;
0418         else if (width > 1920)
0419             lb_mode = LB_RGB_2560X4;
0420         else
0421             lb_mode = LB_RGB_1920X5;
0422     }
0423
0424     return lb_mode;
0425 }
0426
0427 extern const struct component_ops vop_component_ops;
0428 #endif /* _ROCKCHIP_DRM_VOP_H */