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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
0004  */
0005 
0006 #include <linux/clk.h>
0007 #include <linux/mfd/syscon.h>
0008 #include <linux/module.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/phy/phy.h>
0011 #include <linux/regmap.h>
0012 #include <linux/regulator/consumer.h>
0013 
0014 #include <drm/bridge/dw_hdmi.h>
0015 #include <drm/drm_edid.h>
0016 #include <drm/drm_of.h>
0017 #include <drm/drm_probe_helper.h>
0018 #include <drm/drm_simple_kms_helper.h>
0019 
0020 #include "rockchip_drm_drv.h"
0021 #include "rockchip_drm_vop.h"
0022 
0023 #define RK3228_GRF_SOC_CON2     0x0408
0024 #define RK3228_HDMI_SDAIN_MSK       BIT(14)
0025 #define RK3228_HDMI_SCLIN_MSK       BIT(13)
0026 #define RK3228_GRF_SOC_CON6     0x0418
0027 #define RK3228_HDMI_HPD_VSEL        BIT(6)
0028 #define RK3228_HDMI_SDA_VSEL        BIT(5)
0029 #define RK3228_HDMI_SCL_VSEL        BIT(4)
0030 
0031 #define RK3288_GRF_SOC_CON6     0x025C
0032 #define RK3288_HDMI_LCDC_SEL        BIT(4)
0033 #define RK3328_GRF_SOC_CON2     0x0408
0034 
0035 #define RK3328_HDMI_SDAIN_MSK       BIT(11)
0036 #define RK3328_HDMI_SCLIN_MSK       BIT(10)
0037 #define RK3328_HDMI_HPD_IOE     BIT(2)
0038 #define RK3328_GRF_SOC_CON3     0x040c
0039 /* need to be unset if hdmi or i2c should control voltage */
0040 #define RK3328_HDMI_SDA5V_GRF       BIT(15)
0041 #define RK3328_HDMI_SCL5V_GRF       BIT(14)
0042 #define RK3328_HDMI_HPD5V_GRF       BIT(13)
0043 #define RK3328_HDMI_CEC5V_GRF       BIT(12)
0044 #define RK3328_GRF_SOC_CON4     0x0410
0045 #define RK3328_HDMI_HPD_SARADC      BIT(13)
0046 #define RK3328_HDMI_CEC_5V      BIT(11)
0047 #define RK3328_HDMI_SDA_5V      BIT(10)
0048 #define RK3328_HDMI_SCL_5V      BIT(9)
0049 #define RK3328_HDMI_HPD_5V      BIT(8)
0050 
0051 #define RK3399_GRF_SOC_CON20        0x6250
0052 #define RK3399_HDMI_LCDC_SEL        BIT(6)
0053 
0054 #define RK3568_GRF_VO_CON1      0x0364
0055 #define RK3568_HDMI_SDAIN_MSK       BIT(15)
0056 #define RK3568_HDMI_SCLIN_MSK       BIT(14)
0057 
0058 #define HIWORD_UPDATE(val, mask)    (val | (mask) << 16)
0059 
0060 /**
0061  * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
0062  * @lcdsel_grf_reg: grf register offset of lcdc select
0063  * @lcdsel_big: reg value of selecting vop big for HDMI
0064  * @lcdsel_lit: reg value of selecting vop little for HDMI
0065  */
0066 struct rockchip_hdmi_chip_data {
0067     int lcdsel_grf_reg;
0068     u32 lcdsel_big;
0069     u32 lcdsel_lit;
0070 };
0071 
0072 struct rockchip_hdmi {
0073     struct device *dev;
0074     struct regmap *regmap;
0075     struct rockchip_encoder encoder;
0076     const struct rockchip_hdmi_chip_data *chip_data;
0077     struct clk *ref_clk;
0078     struct clk *grf_clk;
0079     struct dw_hdmi *hdmi;
0080     struct regulator *avdd_0v9;
0081     struct regulator *avdd_1v8;
0082     struct phy *phy;
0083 };
0084 
0085 static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder)
0086 {
0087     struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
0088 
0089     return container_of(rkencoder, struct rockchip_hdmi, encoder);
0090 }
0091 
0092 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
0093     {
0094         27000000, {
0095             { 0x00b3, 0x0000},
0096             { 0x2153, 0x0000},
0097             { 0x40f3, 0x0000}
0098         },
0099     }, {
0100         36000000, {
0101             { 0x00b3, 0x0000},
0102             { 0x2153, 0x0000},
0103             { 0x40f3, 0x0000}
0104         },
0105     }, {
0106         40000000, {
0107             { 0x00b3, 0x0000},
0108             { 0x2153, 0x0000},
0109             { 0x40f3, 0x0000}
0110         },
0111     }, {
0112         54000000, {
0113             { 0x0072, 0x0001},
0114             { 0x2142, 0x0001},
0115             { 0x40a2, 0x0001},
0116         },
0117     }, {
0118         65000000, {
0119             { 0x0072, 0x0001},
0120             { 0x2142, 0x0001},
0121             { 0x40a2, 0x0001},
0122         },
0123     }, {
0124         66000000, {
0125             { 0x013e, 0x0003},
0126             { 0x217e, 0x0002},
0127             { 0x4061, 0x0002}
0128         },
0129     }, {
0130         74250000, {
0131             { 0x0072, 0x0001},
0132             { 0x2145, 0x0002},
0133             { 0x4061, 0x0002}
0134         },
0135     }, {
0136         83500000, {
0137             { 0x0072, 0x0001},
0138         },
0139     }, {
0140         108000000, {
0141             { 0x0051, 0x0002},
0142             { 0x2145, 0x0002},
0143             { 0x4061, 0x0002}
0144         },
0145     }, {
0146         106500000, {
0147             { 0x0051, 0x0002},
0148             { 0x2145, 0x0002},
0149             { 0x4061, 0x0002}
0150         },
0151     }, {
0152         146250000, {
0153             { 0x0051, 0x0002},
0154             { 0x2145, 0x0002},
0155             { 0x4061, 0x0002}
0156         },
0157     }, {
0158         148500000, {
0159             { 0x0051, 0x0003},
0160             { 0x214c, 0x0003},
0161             { 0x4064, 0x0003}
0162         },
0163     }, {
0164         ~0UL, {
0165             { 0x00a0, 0x000a },
0166             { 0x2001, 0x000f },
0167             { 0x4002, 0x000f },
0168         },
0169     }
0170 };
0171 
0172 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
0173     /*      pixelclk    bpp8    bpp10   bpp12 */
0174     {
0175         40000000,  { 0x0018, 0x0018, 0x0018 },
0176     }, {
0177         65000000,  { 0x0028, 0x0028, 0x0028 },
0178     }, {
0179         66000000,  { 0x0038, 0x0038, 0x0038 },
0180     }, {
0181         74250000,  { 0x0028, 0x0038, 0x0038 },
0182     }, {
0183         83500000,  { 0x0028, 0x0038, 0x0038 },
0184     }, {
0185         146250000, { 0x0038, 0x0038, 0x0038 },
0186     }, {
0187         148500000, { 0x0000, 0x0038, 0x0038 },
0188     }, {
0189         ~0UL,      { 0x0000, 0x0000, 0x0000},
0190     }
0191 };
0192 
0193 static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
0194     /*pixelclk   symbol   term   vlev*/
0195     { 74250000,  0x8009, 0x0004, 0x0272},
0196     { 148500000, 0x802b, 0x0004, 0x028d},
0197     { 297000000, 0x8039, 0x0005, 0x028d},
0198     { ~0UL,      0x0000, 0x0000, 0x0000}
0199 };
0200 
0201 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
0202 {
0203     struct device_node *np = hdmi->dev->of_node;
0204 
0205     hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
0206     if (IS_ERR(hdmi->regmap)) {
0207         DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,grf\n");
0208         return PTR_ERR(hdmi->regmap);
0209     }
0210 
0211     hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "ref");
0212     if (!hdmi->ref_clk)
0213         hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "vpll");
0214 
0215     if (PTR_ERR(hdmi->ref_clk) == -EPROBE_DEFER) {
0216         return -EPROBE_DEFER;
0217     } else if (IS_ERR(hdmi->ref_clk)) {
0218         DRM_DEV_ERROR(hdmi->dev, "failed to get reference clock\n");
0219         return PTR_ERR(hdmi->ref_clk);
0220     }
0221 
0222     hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
0223     if (PTR_ERR(hdmi->grf_clk) == -ENOENT) {
0224         hdmi->grf_clk = NULL;
0225     } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {
0226         return -EPROBE_DEFER;
0227     } else if (IS_ERR(hdmi->grf_clk)) {
0228         DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n");
0229         return PTR_ERR(hdmi->grf_clk);
0230     }
0231 
0232     hdmi->avdd_0v9 = devm_regulator_get(hdmi->dev, "avdd-0v9");
0233     if (IS_ERR(hdmi->avdd_0v9))
0234         return PTR_ERR(hdmi->avdd_0v9);
0235 
0236     hdmi->avdd_1v8 = devm_regulator_get(hdmi->dev, "avdd-1v8");
0237     if (IS_ERR(hdmi->avdd_1v8))
0238         return PTR_ERR(hdmi->avdd_1v8);
0239 
0240     return 0;
0241 }
0242 
0243 static enum drm_mode_status
0244 dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data,
0245                 const struct drm_display_info *info,
0246                 const struct drm_display_mode *mode)
0247 {
0248     const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
0249     int pclk = mode->clock * 1000;
0250     bool valid = false;
0251     int i;
0252 
0253     for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
0254         if (pclk == mpll_cfg[i].mpixelclock) {
0255             valid = true;
0256             break;
0257         }
0258     }
0259 
0260     return (valid) ? MODE_OK : MODE_BAD;
0261 }
0262 
0263 static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
0264 {
0265 }
0266 
0267 static bool
0268 dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
0269                     const struct drm_display_mode *mode,
0270                     struct drm_display_mode *adj_mode)
0271 {
0272     return true;
0273 }
0274 
0275 static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
0276                           struct drm_display_mode *mode,
0277                           struct drm_display_mode *adj_mode)
0278 {
0279     struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
0280 
0281     clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000);
0282 }
0283 
0284 static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
0285 {
0286     struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
0287     u32 val;
0288     int ret;
0289 
0290     if (hdmi->chip_data->lcdsel_grf_reg < 0)
0291         return;
0292 
0293     ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
0294     if (ret)
0295         val = hdmi->chip_data->lcdsel_lit;
0296     else
0297         val = hdmi->chip_data->lcdsel_big;
0298 
0299     ret = clk_prepare_enable(hdmi->grf_clk);
0300     if (ret < 0) {
0301         DRM_DEV_ERROR(hdmi->dev, "failed to enable grfclk %d\n", ret);
0302         return;
0303     }
0304 
0305     ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val);
0306     if (ret != 0)
0307         DRM_DEV_ERROR(hdmi->dev, "Could not write to GRF: %d\n", ret);
0308 
0309     clk_disable_unprepare(hdmi->grf_clk);
0310     DRM_DEV_DEBUG(hdmi->dev, "vop %s output to hdmi\n",
0311               ret ? "LIT" : "BIG");
0312 }
0313 
0314 static int
0315 dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
0316                       struct drm_crtc_state *crtc_state,
0317                       struct drm_connector_state *conn_state)
0318 {
0319     struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
0320 
0321     s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
0322     s->output_type = DRM_MODE_CONNECTOR_HDMIA;
0323 
0324     return 0;
0325 }
0326 
0327 static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
0328     .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
0329     .mode_set   = dw_hdmi_rockchip_encoder_mode_set,
0330     .enable     = dw_hdmi_rockchip_encoder_enable,
0331     .disable    = dw_hdmi_rockchip_encoder_disable,
0332     .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
0333 };
0334 
0335 static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data,
0336                     const struct drm_display_info *display,
0337                     const struct drm_display_mode *mode)
0338 {
0339     struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
0340 
0341     return phy_power_on(hdmi->phy);
0342 }
0343 
0344 static void dw_hdmi_rockchip_genphy_disable(struct dw_hdmi *dw_hdmi, void *data)
0345 {
0346     struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
0347 
0348     phy_power_off(hdmi->phy);
0349 }
0350 
0351 static void dw_hdmi_rk3228_setup_hpd(struct dw_hdmi *dw_hdmi, void *data)
0352 {
0353     struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
0354 
0355     dw_hdmi_phy_setup_hpd(dw_hdmi, data);
0356 
0357     regmap_write(hdmi->regmap,
0358         RK3228_GRF_SOC_CON6,
0359         HIWORD_UPDATE(RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |
0360                   RK3228_HDMI_SCL_VSEL,
0361                   RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |
0362                   RK3228_HDMI_SCL_VSEL));
0363 
0364     regmap_write(hdmi->regmap,
0365         RK3228_GRF_SOC_CON2,
0366         HIWORD_UPDATE(RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK,
0367                   RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK));
0368 }
0369 
0370 static enum drm_connector_status
0371 dw_hdmi_rk3328_read_hpd(struct dw_hdmi *dw_hdmi, void *data)
0372 {
0373     struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
0374     enum drm_connector_status status;
0375 
0376     status = dw_hdmi_phy_read_hpd(dw_hdmi, data);
0377 
0378     if (status == connector_status_connected)
0379         regmap_write(hdmi->regmap,
0380             RK3328_GRF_SOC_CON4,
0381             HIWORD_UPDATE(RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V,
0382                       RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V));
0383     else
0384         regmap_write(hdmi->regmap,
0385             RK3328_GRF_SOC_CON4,
0386             HIWORD_UPDATE(0, RK3328_HDMI_SDA_5V |
0387                      RK3328_HDMI_SCL_5V));
0388     return status;
0389 }
0390 
0391 static void dw_hdmi_rk3328_setup_hpd(struct dw_hdmi *dw_hdmi, void *data)
0392 {
0393     struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
0394 
0395     dw_hdmi_phy_setup_hpd(dw_hdmi, data);
0396 
0397     /* Enable and map pins to 3V grf-controlled io-voltage */
0398     regmap_write(hdmi->regmap,
0399         RK3328_GRF_SOC_CON4,
0400         HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V |
0401                  RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V |
0402                  RK3328_HDMI_HPD_5V));
0403     regmap_write(hdmi->regmap,
0404         RK3328_GRF_SOC_CON3,
0405         HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF |
0406                  RK3328_HDMI_HPD5V_GRF |
0407                  RK3328_HDMI_CEC5V_GRF));
0408     regmap_write(hdmi->regmap,
0409         RK3328_GRF_SOC_CON2,
0410         HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK,
0411                   RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK |
0412                   RK3328_HDMI_HPD_IOE));
0413 }
0414 
0415 static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = {
0416     .init       = dw_hdmi_rockchip_genphy_init,
0417     .disable    = dw_hdmi_rockchip_genphy_disable,
0418     .read_hpd   = dw_hdmi_phy_read_hpd,
0419     .update_hpd = dw_hdmi_phy_update_hpd,
0420     .setup_hpd  = dw_hdmi_rk3228_setup_hpd,
0421 };
0422 
0423 static struct rockchip_hdmi_chip_data rk3228_chip_data = {
0424     .lcdsel_grf_reg = -1,
0425 };
0426 
0427 static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
0428     .mode_valid = dw_hdmi_rockchip_mode_valid,
0429     .mpll_cfg = rockchip_mpll_cfg,
0430     .cur_ctr = rockchip_cur_ctr,
0431     .phy_config = rockchip_phy_config,
0432     .phy_data = &rk3228_chip_data,
0433     .phy_ops = &rk3228_hdmi_phy_ops,
0434     .phy_name = "inno_dw_hdmi_phy2",
0435     .phy_force_vendor = true,
0436 };
0437 
0438 static struct rockchip_hdmi_chip_data rk3288_chip_data = {
0439     .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
0440     .lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
0441     .lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SEL, RK3288_HDMI_LCDC_SEL),
0442 };
0443 
0444 static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
0445     .mode_valid = dw_hdmi_rockchip_mode_valid,
0446     .mpll_cfg   = rockchip_mpll_cfg,
0447     .cur_ctr    = rockchip_cur_ctr,
0448     .phy_config = rockchip_phy_config,
0449     .phy_data = &rk3288_chip_data,
0450 };
0451 
0452 static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = {
0453     .init       = dw_hdmi_rockchip_genphy_init,
0454     .disable    = dw_hdmi_rockchip_genphy_disable,
0455     .read_hpd   = dw_hdmi_rk3328_read_hpd,
0456     .update_hpd = dw_hdmi_phy_update_hpd,
0457     .setup_hpd  = dw_hdmi_rk3328_setup_hpd,
0458 };
0459 
0460 static struct rockchip_hdmi_chip_data rk3328_chip_data = {
0461     .lcdsel_grf_reg = -1,
0462 };
0463 
0464 static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
0465     .mode_valid = dw_hdmi_rockchip_mode_valid,
0466     .mpll_cfg = rockchip_mpll_cfg,
0467     .cur_ctr = rockchip_cur_ctr,
0468     .phy_config = rockchip_phy_config,
0469     .phy_data = &rk3328_chip_data,
0470     .phy_ops = &rk3328_hdmi_phy_ops,
0471     .phy_name = "inno_dw_hdmi_phy2",
0472     .phy_force_vendor = true,
0473     .use_drm_infoframe = true,
0474 };
0475 
0476 static struct rockchip_hdmi_chip_data rk3399_chip_data = {
0477     .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
0478     .lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL),
0479     .lcdsel_lit = HIWORD_UPDATE(RK3399_HDMI_LCDC_SEL, RK3399_HDMI_LCDC_SEL),
0480 };
0481 
0482 static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
0483     .mode_valid = dw_hdmi_rockchip_mode_valid,
0484     .mpll_cfg   = rockchip_mpll_cfg,
0485     .cur_ctr    = rockchip_cur_ctr,
0486     .phy_config = rockchip_phy_config,
0487     .phy_data = &rk3399_chip_data,
0488     .use_drm_infoframe = true,
0489 };
0490 
0491 static struct rockchip_hdmi_chip_data rk3568_chip_data = {
0492     .lcdsel_grf_reg = -1,
0493 };
0494 
0495 static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {
0496     .mode_valid = dw_hdmi_rockchip_mode_valid,
0497     .mpll_cfg   = rockchip_mpll_cfg,
0498     .cur_ctr    = rockchip_cur_ctr,
0499     .phy_config = rockchip_phy_config,
0500     .phy_data = &rk3568_chip_data,
0501     .use_drm_infoframe = true,
0502 };
0503 
0504 static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
0505     { .compatible = "rockchip,rk3228-dw-hdmi",
0506       .data = &rk3228_hdmi_drv_data
0507     },
0508     { .compatible = "rockchip,rk3288-dw-hdmi",
0509       .data = &rk3288_hdmi_drv_data
0510     },
0511     { .compatible = "rockchip,rk3328-dw-hdmi",
0512       .data = &rk3328_hdmi_drv_data
0513     },
0514     { .compatible = "rockchip,rk3399-dw-hdmi",
0515       .data = &rk3399_hdmi_drv_data
0516     },
0517     { .compatible = "rockchip,rk3568-dw-hdmi",
0518       .data = &rk3568_hdmi_drv_data
0519     },
0520     {},
0521 };
0522 MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
0523 
0524 static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
0525                  void *data)
0526 {
0527     struct platform_device *pdev = to_platform_device(dev);
0528     struct dw_hdmi_plat_data *plat_data;
0529     const struct of_device_id *match;
0530     struct drm_device *drm = data;
0531     struct drm_encoder *encoder;
0532     struct rockchip_hdmi *hdmi;
0533     int ret;
0534 
0535     if (!pdev->dev.of_node)
0536         return -ENODEV;
0537 
0538     hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
0539     if (!hdmi)
0540         return -ENOMEM;
0541 
0542     match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
0543     plat_data = devm_kmemdup(&pdev->dev, match->data,
0544                          sizeof(*plat_data), GFP_KERNEL);
0545     if (!plat_data)
0546         return -ENOMEM;
0547 
0548     hdmi->dev = &pdev->dev;
0549     hdmi->chip_data = plat_data->phy_data;
0550     plat_data->phy_data = hdmi;
0551     encoder = &hdmi->encoder.encoder;
0552 
0553     encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
0554     rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder,
0555                           dev->of_node, 0, 0);
0556 
0557     /*
0558      * If we failed to find the CRTC(s) which this encoder is
0559      * supposed to be connected to, it's because the CRTC has
0560      * not been registered yet.  Defer probing, and hope that
0561      * the required CRTC is added later.
0562      */
0563     if (encoder->possible_crtcs == 0)
0564         return -EPROBE_DEFER;
0565 
0566     ret = rockchip_hdmi_parse_dt(hdmi);
0567     if (ret) {
0568         DRM_DEV_ERROR(hdmi->dev, "Unable to parse OF data\n");
0569         return ret;
0570     }
0571 
0572     hdmi->phy = devm_phy_optional_get(dev, "hdmi");
0573     if (IS_ERR(hdmi->phy)) {
0574         ret = PTR_ERR(hdmi->phy);
0575         if (ret != -EPROBE_DEFER)
0576             DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n");
0577         return ret;
0578     }
0579 
0580     ret = regulator_enable(hdmi->avdd_0v9);
0581     if (ret) {
0582         DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd0v9: %d\n", ret);
0583         goto err_avdd_0v9;
0584     }
0585 
0586     ret = regulator_enable(hdmi->avdd_1v8);
0587     if (ret) {
0588         DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd1v8: %d\n", ret);
0589         goto err_avdd_1v8;
0590     }
0591 
0592     ret = clk_prepare_enable(hdmi->ref_clk);
0593     if (ret) {
0594         DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n",
0595                   ret);
0596         goto err_clk;
0597     }
0598 
0599     if (hdmi->chip_data == &rk3568_chip_data) {
0600         regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
0601                  HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
0602                        RK3568_HDMI_SCLIN_MSK,
0603                        RK3568_HDMI_SDAIN_MSK |
0604                        RK3568_HDMI_SCLIN_MSK));
0605     }
0606 
0607     drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
0608     drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
0609 
0610     platform_set_drvdata(pdev, hdmi);
0611 
0612     hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
0613 
0614     /*
0615      * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
0616      * which would have called the encoder cleanup.  Do it manually.
0617      */
0618     if (IS_ERR(hdmi->hdmi)) {
0619         ret = PTR_ERR(hdmi->hdmi);
0620         goto err_bind;
0621     }
0622 
0623     return 0;
0624 
0625 err_bind:
0626     drm_encoder_cleanup(encoder);
0627     clk_disable_unprepare(hdmi->ref_clk);
0628 err_clk:
0629     regulator_disable(hdmi->avdd_1v8);
0630 err_avdd_1v8:
0631     regulator_disable(hdmi->avdd_0v9);
0632 err_avdd_0v9:
0633     return ret;
0634 }
0635 
0636 static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
0637                     void *data)
0638 {
0639     struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
0640 
0641     dw_hdmi_unbind(hdmi->hdmi);
0642     clk_disable_unprepare(hdmi->ref_clk);
0643 
0644     regulator_disable(hdmi->avdd_1v8);
0645     regulator_disable(hdmi->avdd_0v9);
0646 }
0647 
0648 static const struct component_ops dw_hdmi_rockchip_ops = {
0649     .bind   = dw_hdmi_rockchip_bind,
0650     .unbind = dw_hdmi_rockchip_unbind,
0651 };
0652 
0653 static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
0654 {
0655     return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
0656 }
0657 
0658 static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
0659 {
0660     component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
0661 
0662     return 0;
0663 }
0664 
0665 static int __maybe_unused dw_hdmi_rockchip_resume(struct device *dev)
0666 {
0667     struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
0668 
0669     dw_hdmi_resume(hdmi->hdmi);
0670 
0671     return 0;
0672 }
0673 
0674 static const struct dev_pm_ops dw_hdmi_rockchip_pm = {
0675     SET_SYSTEM_SLEEP_PM_OPS(NULL, dw_hdmi_rockchip_resume)
0676 };
0677 
0678 struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
0679     .probe  = dw_hdmi_rockchip_probe,
0680     .remove = dw_hdmi_rockchip_remove,
0681     .driver = {
0682         .name = "dwhdmi-rockchip",
0683         .pm = &dw_hdmi_rockchip_pm,
0684         .of_match_table = dw_hdmi_rockchip_dt_ids,
0685     },
0686 };
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