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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
0004  * Author:
0005  *      Chris Zhong <zyw@rock-chips.com>
0006  *      Nickey Yang <nickey.yang@rock-chips.com>
0007  */
0008 
0009 #include <linux/clk.h>
0010 #include <linux/iopoll.h>
0011 #include <linux/math64.h>
0012 #include <linux/mfd/syscon.h>
0013 #include <linux/module.h>
0014 #include <linux/of_device.h>
0015 #include <linux/phy/phy.h>
0016 #include <linux/pm_runtime.h>
0017 #include <linux/regmap.h>
0018 
0019 #include <video/mipi_display.h>
0020 
0021 #include <drm/bridge/dw_mipi_dsi.h>
0022 #include <drm/drm_mipi_dsi.h>
0023 #include <drm/drm_of.h>
0024 #include <drm/drm_simple_kms_helper.h>
0025 
0026 #include "rockchip_drm_drv.h"
0027 #include "rockchip_drm_vop.h"
0028 
0029 #define DSI_PHY_RSTZ            0xa0
0030 #define PHY_DISFORCEPLL         0
0031 #define PHY_ENFORCEPLL          BIT(3)
0032 #define PHY_DISABLECLK          0
0033 #define PHY_ENABLECLK           BIT(2)
0034 #define PHY_RSTZ            0
0035 #define PHY_UNRSTZ          BIT(1)
0036 #define PHY_SHUTDOWNZ           0
0037 #define PHY_UNSHUTDOWNZ         BIT(0)
0038 
0039 #define DSI_PHY_IF_CFG          0xa4
0040 #define N_LANES(n)          ((((n) - 1) & 0x3) << 0)
0041 #define PHY_STOP_WAIT_TIME(cycle)   (((cycle) & 0xff) << 8)
0042 
0043 #define DSI_PHY_STATUS          0xb0
0044 #define LOCK                BIT(0)
0045 #define STOP_STATE_CLK_LANE     BIT(2)
0046 
0047 #define DSI_PHY_TST_CTRL0       0xb4
0048 #define PHY_TESTCLK         BIT(1)
0049 #define PHY_UNTESTCLK           0
0050 #define PHY_TESTCLR         BIT(0)
0051 #define PHY_UNTESTCLR           0
0052 
0053 #define DSI_PHY_TST_CTRL1       0xb8
0054 #define PHY_TESTEN          BIT(16)
0055 #define PHY_UNTESTEN            0
0056 #define PHY_TESTDOUT(n)         (((n) & 0xff) << 8)
0057 #define PHY_TESTDIN(n)          (((n) & 0xff) << 0)
0058 
0059 #define DSI_INT_ST0         0xbc
0060 #define DSI_INT_ST1         0xc0
0061 #define DSI_INT_MSK0            0xc4
0062 #define DSI_INT_MSK1            0xc8
0063 
0064 #define PHY_STATUS_TIMEOUT_US       10000
0065 #define CMD_PKT_STATUS_TIMEOUT_US   20000
0066 
0067 #define BYPASS_VCO_RANGE    BIT(7)
0068 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
0069 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
0070 #define VCO_IN_CAP_CON_LOW  (0x1 << 1)
0071 #define VCO_IN_CAP_CON_HIGH (0x2 << 1)
0072 #define REF_BIAS_CUR_SEL    BIT(0)
0073 
0074 #define CP_CURRENT_3UA  0x1
0075 #define CP_CURRENT_4_5UA    0x2
0076 #define CP_CURRENT_7_5UA    0x6
0077 #define CP_CURRENT_6UA  0x9
0078 #define CP_CURRENT_12UA 0xb
0079 #define CP_CURRENT_SEL(val) ((val) & 0xf)
0080 #define CP_PROGRAM_EN       BIT(7)
0081 
0082 #define LPF_RESISTORS_15_5KOHM  0x1
0083 #define LPF_RESISTORS_13KOHM    0x2
0084 #define LPF_RESISTORS_11_5KOHM  0x4
0085 #define LPF_RESISTORS_10_5KOHM  0x8
0086 #define LPF_RESISTORS_8KOHM 0x10
0087 #define LPF_PROGRAM_EN      BIT(6)
0088 #define LPF_RESISTORS_SEL(val)  ((val) & 0x3f)
0089 
0090 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
0091 
0092 #define INPUT_DIVIDER(val)  (((val) - 1) & 0x7f)
0093 #define LOW_PROGRAM_EN      0
0094 #define HIGH_PROGRAM_EN     BIT(7)
0095 #define LOOP_DIV_LOW_SEL(val)   (((val) - 1) & 0x1f)
0096 #define LOOP_DIV_HIGH_SEL(val)  ((((val) - 1) >> 5) & 0xf)
0097 #define PLL_LOOP_DIV_EN     BIT(5)
0098 #define PLL_INPUT_DIV_EN    BIT(4)
0099 
0100 #define POWER_CONTROL       BIT(6)
0101 #define INTERNAL_REG_CURRENT    BIT(3)
0102 #define BIAS_BLOCK_ON       BIT(2)
0103 #define BANDGAP_ON      BIT(0)
0104 
0105 #define TER_RESISTOR_HIGH   BIT(7)
0106 #define TER_RESISTOR_LOW    0
0107 #define LEVEL_SHIFTERS_ON   BIT(6)
0108 #define TER_CAL_DONE        BIT(5)
0109 #define SETRD_MAX       (0x7 << 2)
0110 #define POWER_MANAGE        BIT(1)
0111 #define TER_RESISTORS_ON    BIT(0)
0112 
0113 #define BIASEXTR_SEL(val)   ((val) & 0x7)
0114 #define BANDGAP_SEL(val)    ((val) & 0x7)
0115 #define TLP_PROGRAM_EN      BIT(7)
0116 #define THS_PRE_PROGRAM_EN  BIT(7)
0117 #define THS_ZERO_PROGRAM_EN BIT(6)
0118 
0119 #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL        0x10
0120 #define PLL_CP_CONTROL_PLL_LOCK_BYPASS          0x11
0121 #define PLL_LPF_AND_CP_CONTROL              0x12
0122 #define PLL_INPUT_DIVIDER_RATIO             0x17
0123 #define PLL_LOOP_DIVIDER_RATIO              0x18
0124 #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL   0x19
0125 #define BANDGAP_AND_BIAS_CONTROL            0x20
0126 #define TERMINATION_RESISTER_CONTROL            0x21
0127 #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY     0x22
0128 #define HS_RX_CONTROL_OF_LANE_CLK           0x34
0129 #define HS_RX_CONTROL_OF_LANE_0             0x44
0130 #define HS_RX_CONTROL_OF_LANE_1             0x54
0131 #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60
0132 #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61
0133 #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62
0134 #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL   0x63
0135 #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL    0x64
0136 #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL      0x65
0137 #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL  0x70
0138 #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL  0x71
0139 #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL  0x72
0140 #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL    0x73
0141 #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL     0x74
0142 #define HS_RX_DATA_LANE_THS_SETTLE_CONTROL      0x75
0143 #define HS_RX_CONTROL_OF_LANE_2             0x84
0144 #define HS_RX_CONTROL_OF_LANE_3             0x94
0145 
0146 #define DW_MIPI_NEEDS_PHY_CFG_CLK   BIT(0)
0147 #define DW_MIPI_NEEDS_GRF_CLK       BIT(1)
0148 
0149 #define PX30_GRF_PD_VO_CON1     0x0438
0150 #define PX30_DSI_FORCETXSTOPMODE    (0xf << 7)
0151 #define PX30_DSI_FORCERXMODE        BIT(6)
0152 #define PX30_DSI_TURNDISABLE        BIT(5)
0153 #define PX30_DSI_LCDC_SEL       BIT(0)
0154 
0155 #define RK3288_GRF_SOC_CON6     0x025c
0156 #define RK3288_DSI0_LCDC_SEL        BIT(6)
0157 #define RK3288_DSI1_LCDC_SEL        BIT(9)
0158 
0159 #define RK3399_GRF_SOC_CON20        0x6250
0160 #define RK3399_DSI0_LCDC_SEL        BIT(0)
0161 #define RK3399_DSI1_LCDC_SEL        BIT(4)
0162 
0163 #define RK3399_GRF_SOC_CON22        0x6258
0164 #define RK3399_DSI0_TURNREQUEST     (0xf << 12)
0165 #define RK3399_DSI0_TURNDISABLE     (0xf << 8)
0166 #define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4)
0167 #define RK3399_DSI0_FORCERXMODE     (0xf << 0)
0168 
0169 #define RK3399_GRF_SOC_CON23        0x625c
0170 #define RK3399_DSI1_TURNDISABLE     (0xf << 12)
0171 #define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8)
0172 #define RK3399_DSI1_FORCERXMODE     (0xf << 4)
0173 #define RK3399_DSI1_ENABLE      (0xf << 0)
0174 
0175 #define RK3399_GRF_SOC_CON24        0x6260
0176 #define RK3399_TXRX_MASTERSLAVEZ    BIT(7)
0177 #define RK3399_TXRX_ENABLECLK       BIT(6)
0178 #define RK3399_TXRX_BASEDIR     BIT(5)
0179 #define RK3399_TXRX_SRC_SEL_ISP0    BIT(4)
0180 #define RK3399_TXRX_TURNREQUEST     GENMASK(3, 0)
0181 
0182 #define HIWORD_UPDATE(val, mask)    (val | (mask) << 16)
0183 
0184 enum {
0185     DW_DSI_USAGE_IDLE,
0186     DW_DSI_USAGE_DSI,
0187     DW_DSI_USAGE_PHY,
0188 };
0189 
0190 enum {
0191     BANDGAP_97_07,
0192     BANDGAP_98_05,
0193     BANDGAP_99_02,
0194     BANDGAP_100_00,
0195     BANDGAP_93_17,
0196     BANDGAP_94_15,
0197     BANDGAP_95_12,
0198     BANDGAP_96_10,
0199 };
0200 
0201 enum {
0202     BIASEXTR_87_1,
0203     BIASEXTR_91_5,
0204     BIASEXTR_95_9,
0205     BIASEXTR_100,
0206     BIASEXTR_105_94,
0207     BIASEXTR_111_88,
0208     BIASEXTR_118_8,
0209     BIASEXTR_127_7,
0210 };
0211 
0212 struct rockchip_dw_dsi_chip_data {
0213     u32 reg;
0214 
0215     u32 lcdsel_grf_reg;
0216     u32 lcdsel_big;
0217     u32 lcdsel_lit;
0218 
0219     u32 enable_grf_reg;
0220     u32 enable;
0221 
0222     u32 lanecfg1_grf_reg;
0223     u32 lanecfg1;
0224     u32 lanecfg2_grf_reg;
0225     u32 lanecfg2;
0226 
0227     int (*dphy_rx_init)(struct phy *phy);
0228     int (*dphy_rx_power_on)(struct phy *phy);
0229     int (*dphy_rx_power_off)(struct phy *phy);
0230 
0231     unsigned int flags;
0232     unsigned int max_data_lanes;
0233 };
0234 
0235 struct dw_mipi_dsi_rockchip {
0236     struct device *dev;
0237     struct rockchip_encoder encoder;
0238     void __iomem *base;
0239 
0240     struct regmap *grf_regmap;
0241     struct clk *pclk;
0242     struct clk *pllref_clk;
0243     struct clk *grf_clk;
0244     struct clk *phy_cfg_clk;
0245 
0246     /* dual-channel */
0247     bool is_slave;
0248     struct dw_mipi_dsi_rockchip *slave;
0249 
0250     /* optional external dphy */
0251     struct phy *phy;
0252     union phy_configure_opts phy_opts;
0253 
0254     /* being a phy for other mipi hosts */
0255     unsigned int usage_mode;
0256     struct mutex usage_mutex;
0257     struct phy *dphy;
0258     struct phy_configure_opts_mipi_dphy dphy_config;
0259 
0260     unsigned int lane_mbps; /* per lane */
0261     u16 input_div;
0262     u16 feedback_div;
0263     u32 format;
0264 
0265     struct dw_mipi_dsi *dmd;
0266     const struct rockchip_dw_dsi_chip_data *cdata;
0267     struct dw_mipi_dsi_plat_data pdata;
0268 
0269     bool dsi_bound;
0270 };
0271 
0272 static struct dw_mipi_dsi_rockchip *to_dsi(struct drm_encoder *encoder)
0273 {
0274     struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
0275 
0276     return container_of(rkencoder, struct dw_mipi_dsi_rockchip, encoder);
0277 }
0278 
0279 struct dphy_pll_parameter_map {
0280     unsigned int max_mbps;
0281     u8 hsfreqrange;
0282     u8 icpctrl;
0283     u8 lpfctrl;
0284 };
0285 
0286 /* The table is based on 27MHz DPHY pll reference clock. */
0287 static const struct dphy_pll_parameter_map dppa_map[] = {
0288     {  89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
0289     {  99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
0290     { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
0291     { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
0292     { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
0293     { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
0294     { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
0295     { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
0296     { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
0297     { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
0298     { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
0299     { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
0300     { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
0301     { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
0302     { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
0303     { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
0304     { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
0305     { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
0306     { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
0307     { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
0308     { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
0309     { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
0310     { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
0311     { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
0312     { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
0313     { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
0314     { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
0315     { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
0316     { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
0317     {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
0318     {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
0319     {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
0320     {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
0321     {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
0322     {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
0323     {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
0324     {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
0325     {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
0326     {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }
0327 };
0328 
0329 static int max_mbps_to_parameter(unsigned int max_mbps)
0330 {
0331     int i;
0332 
0333     for (i = 0; i < ARRAY_SIZE(dppa_map); i++)
0334         if (dppa_map[i].max_mbps >= max_mbps)
0335             return i;
0336 
0337     return -EINVAL;
0338 }
0339 
0340 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val)
0341 {
0342     writel(val, dsi->base + reg);
0343 }
0344 
0345 static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg)
0346 {
0347     return readl(dsi->base + reg);
0348 }
0349 
0350 static inline void dsi_update_bits(struct dw_mipi_dsi_rockchip *dsi, u32 reg,
0351                    u32 mask, u32 val)
0352 {
0353     dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
0354 }
0355 
0356 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi,
0357                   u8 test_code,
0358                   u8 test_data)
0359 {
0360     /*
0361      * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
0362      * is latched internally as the current test code. Test data is
0363      * programmed internally by rising edge on TESTCLK.
0364      */
0365     dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
0366 
0367     dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
0368                       PHY_TESTDIN(test_code));
0369 
0370     dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
0371 
0372     dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
0373                       PHY_TESTDIN(test_data));
0374 
0375     dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
0376 }
0377 
0378 /*
0379  * ns2bc - Nanoseconds to byte clock cycles
0380  */
0381 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns)
0382 {
0383     return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
0384 }
0385 
0386 /*
0387  * ns2ui - Nanoseconds to UI time periods
0388  */
0389 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns)
0390 {
0391     return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
0392 }
0393 
0394 static int dw_mipi_dsi_phy_init(void *priv_data)
0395 {
0396     struct dw_mipi_dsi_rockchip *dsi = priv_data;
0397     int ret, i, vco;
0398 
0399     if (dsi->phy)
0400         return 0;
0401 
0402     /*
0403      * Get vco from frequency(lane_mbps)
0404      * vco  frequency table
0405      * 000 - between   80 and  200 MHz
0406      * 001 - between  200 and  300 MHz
0407      * 010 - between  300 and  500 MHz
0408      * 011 - between  500 and  700 MHz
0409      * 100 - between  700 and  900 MHz
0410      * 101 - between  900 and 1100 MHz
0411      * 110 - between 1100 and 1300 MHz
0412      * 111 - between 1300 and 1500 MHz
0413      */
0414     vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
0415 
0416     i = max_mbps_to_parameter(dsi->lane_mbps);
0417     if (i < 0) {
0418         DRM_DEV_ERROR(dsi->dev,
0419                   "failed to get parameter for %dmbps clock\n",
0420                   dsi->lane_mbps);
0421         return i;
0422     }
0423 
0424     ret = clk_prepare_enable(dsi->phy_cfg_clk);
0425     if (ret) {
0426         DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");
0427         return ret;
0428     }
0429 
0430     dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,
0431                   BYPASS_VCO_RANGE |
0432                   VCO_RANGE_CON_SEL(vco) |
0433                   VCO_IN_CAP_CON_LOW |
0434                   REF_BIAS_CUR_SEL);
0435 
0436     dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,
0437                   CP_CURRENT_SEL(dppa_map[i].icpctrl));
0438     dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,
0439                   CP_PROGRAM_EN | LPF_PROGRAM_EN |
0440                   LPF_RESISTORS_SEL(dppa_map[i].lpfctrl));
0441 
0442     dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
0443                   HSFREQRANGE_SEL(dppa_map[i].hsfreqrange));
0444 
0445     dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,
0446                   INPUT_DIVIDER(dsi->input_div));
0447     dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
0448                   LOOP_DIV_LOW_SEL(dsi->feedback_div) |
0449                   LOW_PROGRAM_EN);
0450     /*
0451      * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately
0452      * to make the configured LSB effective according to IP simulation
0453      * and lab test results.
0454      * Only in this way can we get correct mipi phy pll frequency.
0455      */
0456     dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
0457                   PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
0458     dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
0459                   LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
0460                   HIGH_PROGRAM_EN);
0461     dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
0462                   PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
0463 
0464     dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
0465                   LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7));
0466     dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
0467                   HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10));
0468 
0469     dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL,
0470                   POWER_CONTROL | INTERNAL_REG_CURRENT |
0471                   BIAS_BLOCK_ON | BANDGAP_ON);
0472 
0473     dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
0474                   TER_RESISTOR_LOW | TER_CAL_DONE |
0475                   SETRD_MAX | TER_RESISTORS_ON);
0476     dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
0477                   TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
0478                   SETRD_MAX | POWER_MANAGE |
0479                   TER_RESISTORS_ON);
0480 
0481     dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,
0482                   TLP_PROGRAM_EN | ns2bc(dsi, 500));
0483     dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,
0484                   THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
0485     dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,
0486                   THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
0487     dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,
0488                   THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
0489     dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,
0490                   BIT(5) | ns2bc(dsi, 100));
0491     dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL,
0492                   BIT(5) | (ns2bc(dsi, 60) + 7));
0493 
0494     dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,
0495                   TLP_PROGRAM_EN | ns2bc(dsi, 500));
0496     dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL,
0497                   THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20));
0498     dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL,
0499                   THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
0500     dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL,
0501                   THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
0502     dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,
0503                   BIT(5) | ns2bc(dsi, 100));
0504 
0505     clk_disable_unprepare(dsi->phy_cfg_clk);
0506 
0507     return ret;
0508 }
0509 
0510 static void dw_mipi_dsi_phy_power_on(void *priv_data)
0511 {
0512     struct dw_mipi_dsi_rockchip *dsi = priv_data;
0513     int ret;
0514 
0515     ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
0516     if (ret) {
0517         DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret);
0518         return;
0519     }
0520 
0521     phy_configure(dsi->phy, &dsi->phy_opts);
0522     phy_power_on(dsi->phy);
0523 }
0524 
0525 static void dw_mipi_dsi_phy_power_off(void *priv_data)
0526 {
0527     struct dw_mipi_dsi_rockchip *dsi = priv_data;
0528 
0529     phy_power_off(dsi->phy);
0530 }
0531 
0532 static int
0533 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
0534               unsigned long mode_flags, u32 lanes, u32 format,
0535               unsigned int *lane_mbps)
0536 {
0537     struct dw_mipi_dsi_rockchip *dsi = priv_data;
0538     int bpp;
0539     unsigned long mpclk, tmp;
0540     unsigned int target_mbps = 1000;
0541     unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps;
0542     unsigned long best_freq = 0;
0543     unsigned long fvco_min, fvco_max, fin, fout;
0544     unsigned int min_prediv, max_prediv;
0545     unsigned int _prediv, best_prediv;
0546     unsigned long _fbdiv, best_fbdiv;
0547     unsigned long min_delta = ULONG_MAX;
0548 
0549     dsi->format = format;
0550     bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
0551     if (bpp < 0) {
0552         DRM_DEV_ERROR(dsi->dev,
0553                   "failed to get bpp for pixel format %d\n",
0554                   dsi->format);
0555         return bpp;
0556     }
0557 
0558     mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
0559     if (mpclk) {
0560         /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
0561         tmp = mpclk * (bpp / lanes) * 10 / 8;
0562         if (tmp < max_mbps)
0563             target_mbps = tmp;
0564         else
0565             DRM_DEV_ERROR(dsi->dev,
0566                       "DPHY clock frequency is out of range\n");
0567     }
0568 
0569     /* for external phy only a the mipi_dphy_config is necessary */
0570     if (dsi->phy) {
0571         phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8,
0572                          bpp, lanes,
0573                          &dsi->phy_opts.mipi_dphy);
0574         dsi->lane_mbps = target_mbps;
0575         *lane_mbps = dsi->lane_mbps;
0576 
0577         return 0;
0578     }
0579 
0580     fin = clk_get_rate(dsi->pllref_clk);
0581     fout = target_mbps * USEC_PER_SEC;
0582 
0583     /* constraint: 5Mhz <= Fref / N <= 40MHz */
0584     min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
0585     max_prediv = fin / (5 * USEC_PER_SEC);
0586 
0587     /* constraint: 80MHz <= Fvco <= 1500Mhz */
0588     fvco_min = 80 * USEC_PER_SEC;
0589     fvco_max = 1500 * USEC_PER_SEC;
0590 
0591     for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
0592         u64 tmp;
0593         u32 delta;
0594         /* Fvco = Fref * M / N */
0595         tmp = (u64)fout * _prediv;
0596         do_div(tmp, fin);
0597         _fbdiv = tmp;
0598         /*
0599          * Due to the use of a "by 2 pre-scaler," the range of the
0600          * feedback multiplication value M is limited to even division
0601          * numbers, and m must be greater than 6, not bigger than 512.
0602          */
0603         if (_fbdiv < 6 || _fbdiv > 512)
0604             continue;
0605 
0606         _fbdiv += _fbdiv % 2;
0607 
0608         tmp = (u64)_fbdiv * fin;
0609         do_div(tmp, _prediv);
0610         if (tmp < fvco_min || tmp > fvco_max)
0611             continue;
0612 
0613         delta = abs(fout - tmp);
0614         if (delta < min_delta) {
0615             best_prediv = _prediv;
0616             best_fbdiv = _fbdiv;
0617             min_delta = delta;
0618             best_freq = tmp;
0619         }
0620     }
0621 
0622     if (best_freq) {
0623         dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC);
0624         *lane_mbps = dsi->lane_mbps;
0625         dsi->input_div = best_prediv;
0626         dsi->feedback_div = best_fbdiv;
0627     } else {
0628         DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n");
0629         return -EINVAL;
0630     }
0631 
0632     return 0;
0633 }
0634 
0635 struct hstt {
0636     unsigned int maxfreq;
0637     struct dw_mipi_dsi_dphy_timing timing;
0638 };
0639 
0640 #define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp)  \
0641 {                   \
0642     .maxfreq = _maxfreq,        \
0643     .timing = {         \
0644         .clk_lp2hs = _c_lp2hs,  \
0645         .clk_hs2lp = _c_hs2lp,  \
0646         .data_lp2hs = _d_lp2hs, \
0647         .data_hs2lp = _d_hs2lp, \
0648     }               \
0649 }
0650 
0651 /* Table A-3 High-Speed Transition Times */
0652 static struct hstt hstt_table[] = {
0653     HSTT(  90,  32, 20,  26, 13),
0654     HSTT( 100,  35, 23,  28, 14),
0655     HSTT( 110,  32, 22,  26, 13),
0656     HSTT( 130,  31, 20,  27, 13),
0657     HSTT( 140,  33, 22,  26, 14),
0658     HSTT( 150,  33, 21,  26, 14),
0659     HSTT( 170,  32, 20,  27, 13),
0660     HSTT( 180,  36, 23,  30, 15),
0661     HSTT( 200,  40, 22,  33, 15),
0662     HSTT( 220,  40, 22,  33, 15),
0663     HSTT( 240,  44, 24,  36, 16),
0664     HSTT( 250,  48, 24,  38, 17),
0665     HSTT( 270,  48, 24,  38, 17),
0666     HSTT( 300,  50, 27,  41, 18),
0667     HSTT( 330,  56, 28,  45, 18),
0668     HSTT( 360,  59, 28,  48, 19),
0669     HSTT( 400,  61, 30,  50, 20),
0670     HSTT( 450,  67, 31,  55, 21),
0671     HSTT( 500,  73, 31,  59, 22),
0672     HSTT( 550,  79, 36,  63, 24),
0673     HSTT( 600,  83, 37,  68, 25),
0674     HSTT( 650,  90, 38,  73, 27),
0675     HSTT( 700,  95, 40,  77, 28),
0676     HSTT( 750, 102, 40,  84, 28),
0677     HSTT( 800, 106, 42,  87, 30),
0678     HSTT( 850, 113, 44,  93, 31),
0679     HSTT( 900, 118, 47,  98, 32),
0680     HSTT( 950, 124, 47, 102, 34),
0681     HSTT(1000, 130, 49, 107, 35),
0682     HSTT(1050, 135, 51, 111, 37),
0683     HSTT(1100, 139, 51, 114, 38),
0684     HSTT(1150, 146, 54, 120, 40),
0685     HSTT(1200, 153, 57, 125, 41),
0686     HSTT(1250, 158, 58, 130, 42),
0687     HSTT(1300, 163, 58, 135, 44),
0688     HSTT(1350, 168, 60, 140, 45),
0689     HSTT(1400, 172, 64, 144, 47),
0690     HSTT(1450, 176, 65, 148, 48),
0691     HSTT(1500, 181, 66, 153, 50)
0692 };
0693 
0694 static int
0695 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
0696                struct dw_mipi_dsi_dphy_timing *timing)
0697 {
0698     int i;
0699 
0700     for (i = 0; i < ARRAY_SIZE(hstt_table); i++)
0701         if (lane_mbps < hstt_table[i].maxfreq)
0702             break;
0703 
0704     if (i == ARRAY_SIZE(hstt_table))
0705         i--;
0706 
0707     *timing = hstt_table[i].timing;
0708 
0709     return 0;
0710 }
0711 
0712 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
0713     .init = dw_mipi_dsi_phy_init,
0714     .power_on = dw_mipi_dsi_phy_power_on,
0715     .power_off = dw_mipi_dsi_phy_power_off,
0716     .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
0717     .get_timing = dw_mipi_dsi_phy_get_timing,
0718 };
0719 
0720 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi)
0721 {
0722     if (dsi->cdata->lanecfg1_grf_reg)
0723         regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg,
0724                           dsi->cdata->lanecfg1);
0725 
0726     if (dsi->cdata->lanecfg2_grf_reg)
0727         regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg,
0728                           dsi->cdata->lanecfg2);
0729 
0730     if (dsi->cdata->enable_grf_reg)
0731         regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg,
0732                           dsi->cdata->enable);
0733 }
0734 
0735 static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi,
0736                         int mux)
0737 {
0738     regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,
0739         mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);
0740 }
0741 
0742 static int
0743 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
0744                  struct drm_crtc_state *crtc_state,
0745                  struct drm_connector_state *conn_state)
0746 {
0747     struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
0748     struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
0749 
0750     switch (dsi->format) {
0751     case MIPI_DSI_FMT_RGB888:
0752         s->output_mode = ROCKCHIP_OUT_MODE_P888;
0753         break;
0754     case MIPI_DSI_FMT_RGB666:
0755         s->output_mode = ROCKCHIP_OUT_MODE_P666;
0756         break;
0757     case MIPI_DSI_FMT_RGB565:
0758         s->output_mode = ROCKCHIP_OUT_MODE_P565;
0759         break;
0760     default:
0761         WARN_ON(1);
0762         return -EINVAL;
0763     }
0764 
0765     s->output_type = DRM_MODE_CONNECTOR_DSI;
0766     if (dsi->slave)
0767         s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL;
0768 
0769     return 0;
0770 }
0771 
0772 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
0773 {
0774     struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
0775     int ret, mux;
0776 
0777     mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node,
0778                         &dsi->encoder.encoder);
0779     if (mux < 0)
0780         return;
0781 
0782     /*
0783      * For the RK3399, the clk of grf must be enabled before writing grf
0784      * register. And for RK3288 or other soc, this grf_clk must be NULL,
0785      * the clk_prepare_enable return true directly.
0786      */
0787     ret = clk_prepare_enable(dsi->grf_clk);
0788     if (ret) {
0789         DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
0790         return;
0791     }
0792 
0793     dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux);
0794     if (dsi->slave)
0795         dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux);
0796 
0797     clk_disable_unprepare(dsi->grf_clk);
0798 }
0799 
0800 static const struct drm_encoder_helper_funcs
0801 dw_mipi_dsi_encoder_helper_funcs = {
0802     .atomic_check = dw_mipi_dsi_encoder_atomic_check,
0803     .enable = dw_mipi_dsi_encoder_enable,
0804 };
0805 
0806 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi,
0807                        struct drm_device *drm_dev)
0808 {
0809     struct drm_encoder *encoder = &dsi->encoder.encoder;
0810     int ret;
0811 
0812     encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
0813                                  dsi->dev->of_node);
0814 
0815     ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI);
0816     if (ret) {
0817         DRM_ERROR("Failed to initialize encoder with drm\n");
0818         return ret;
0819     }
0820 
0821     drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs);
0822 
0823     return 0;
0824 }
0825 
0826 static struct device
0827 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi)
0828 {
0829     const struct of_device_id *match;
0830     struct device_node *node = NULL, *local;
0831 
0832     match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev);
0833 
0834     local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0);
0835     if (!local)
0836         return NULL;
0837 
0838     while ((node = of_find_compatible_node(node, NULL,
0839                            match->compatible))) {
0840         struct device_node *remote;
0841 
0842         /* found ourself */
0843         if (node == dsi->dev->of_node)
0844             continue;
0845 
0846         remote = of_graph_get_remote_node(node, 1, 0);
0847         if (!remote)
0848             continue;
0849 
0850         /* same display device in port1-ep0 for both */
0851         if (remote == local) {
0852             struct dw_mipi_dsi_rockchip *dsi2;
0853             struct platform_device *pdev;
0854 
0855             pdev = of_find_device_by_node(node);
0856 
0857             /*
0858              * we have found the second, so will either return it
0859              * or return with an error. In any case won't need the
0860              * nodes anymore nor continue the loop.
0861              */
0862             of_node_put(remote);
0863             of_node_put(node);
0864             of_node_put(local);
0865 
0866             if (!pdev)
0867                 return ERR_PTR(-EPROBE_DEFER);
0868 
0869             dsi2 = platform_get_drvdata(pdev);
0870             if (!dsi2) {
0871                 platform_device_put(pdev);
0872                 return ERR_PTR(-EPROBE_DEFER);
0873             }
0874 
0875             return &pdev->dev;
0876         }
0877 
0878         of_node_put(remote);
0879     }
0880 
0881     of_node_put(local);
0882 
0883     return NULL;
0884 }
0885 
0886 static int dw_mipi_dsi_rockchip_bind(struct device *dev,
0887                      struct device *master,
0888                      void *data)
0889 {
0890     struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
0891     struct drm_device *drm_dev = data;
0892     struct device *second;
0893     bool master1, master2;
0894     int ret;
0895 
0896     second = dw_mipi_dsi_rockchip_find_second(dsi);
0897     if (IS_ERR(second))
0898         return PTR_ERR(second);
0899 
0900     if (second) {
0901         master1 = of_property_read_bool(dsi->dev->of_node,
0902                         "clock-master");
0903         master2 = of_property_read_bool(second->of_node,
0904                         "clock-master");
0905 
0906         if (master1 && master2) {
0907             DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n");
0908             return -EINVAL;
0909         }
0910 
0911         if (!master1 && !master2) {
0912             DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n");
0913             return -EINVAL;
0914         }
0915 
0916         /* we are the slave in dual-DSI */
0917         if (!master1) {
0918             dsi->is_slave = true;
0919             return 0;
0920         }
0921 
0922         dsi->slave = dev_get_drvdata(second);
0923         if (!dsi->slave) {
0924             DRM_DEV_ERROR(dev, "could not get slaves data\n");
0925             return -ENODEV;
0926         }
0927 
0928         dsi->slave->is_slave = true;
0929         dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd);
0930         put_device(second);
0931     }
0932 
0933     pm_runtime_get_sync(dsi->dev);
0934     if (dsi->slave)
0935         pm_runtime_get_sync(dsi->slave->dev);
0936 
0937     ret = clk_prepare_enable(dsi->pllref_clk);
0938     if (ret) {
0939         DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret);
0940         goto out_pm_runtime;
0941     }
0942 
0943     /*
0944      * With the GRF clock running, write lane and dual-mode configurations
0945      * that won't change immediately. If we waited until enable() to do
0946      * this, things like panel preparation would not be able to send
0947      * commands over DSI.
0948      */
0949     ret = clk_prepare_enable(dsi->grf_clk);
0950     if (ret) {
0951         DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
0952         goto out_pll_clk;
0953     }
0954 
0955     dw_mipi_dsi_rockchip_config(dsi);
0956     if (dsi->slave)
0957         dw_mipi_dsi_rockchip_config(dsi->slave);
0958 
0959     clk_disable_unprepare(dsi->grf_clk);
0960 
0961     ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev);
0962     if (ret) {
0963         DRM_DEV_ERROR(dev, "Failed to create drm encoder\n");
0964         goto out_pll_clk;
0965     }
0966 
0967     ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder);
0968     if (ret) {
0969         DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
0970         goto out_pll_clk;
0971     }
0972 
0973     dsi->dsi_bound = true;
0974 
0975     return 0;
0976 
0977 out_pll_clk:
0978     clk_disable_unprepare(dsi->pllref_clk);
0979 out_pm_runtime:
0980     pm_runtime_put(dsi->dev);
0981     if (dsi->slave)
0982         pm_runtime_put(dsi->slave->dev);
0983 
0984     return ret;
0985 }
0986 
0987 static void dw_mipi_dsi_rockchip_unbind(struct device *dev,
0988                     struct device *master,
0989                     void *data)
0990 {
0991     struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
0992 
0993     if (dsi->is_slave)
0994         return;
0995 
0996     dsi->dsi_bound = false;
0997 
0998     dw_mipi_dsi_unbind(dsi->dmd);
0999 
1000     clk_disable_unprepare(dsi->pllref_clk);
1001 
1002     pm_runtime_put(dsi->dev);
1003     if (dsi->slave)
1004         pm_runtime_put(dsi->slave->dev);
1005 }
1006 
1007 static const struct component_ops dw_mipi_dsi_rockchip_ops = {
1008     .bind   = dw_mipi_dsi_rockchip_bind,
1009     .unbind = dw_mipi_dsi_rockchip_unbind,
1010 };
1011 
1012 static int dw_mipi_dsi_rockchip_host_attach(void *priv_data,
1013                         struct mipi_dsi_device *device)
1014 {
1015     struct dw_mipi_dsi_rockchip *dsi = priv_data;
1016     struct device *second;
1017     int ret;
1018 
1019     mutex_lock(&dsi->usage_mutex);
1020 
1021     if (dsi->usage_mode != DW_DSI_USAGE_IDLE) {
1022         DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n");
1023         mutex_unlock(&dsi->usage_mutex);
1024         return -EBUSY;
1025     }
1026 
1027     dsi->usage_mode = DW_DSI_USAGE_DSI;
1028     mutex_unlock(&dsi->usage_mutex);
1029 
1030     ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops);
1031     if (ret) {
1032         DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n",
1033                     ret);
1034         return ret;
1035     }
1036 
1037     second = dw_mipi_dsi_rockchip_find_second(dsi);
1038     if (IS_ERR(second))
1039         return PTR_ERR(second);
1040     if (second) {
1041         ret = component_add(second, &dw_mipi_dsi_rockchip_ops);
1042         if (ret) {
1043             DRM_DEV_ERROR(second,
1044                       "Failed to register component: %d\n",
1045                       ret);
1046             return ret;
1047         }
1048     }
1049 
1050     return 0;
1051 }
1052 
1053 static int dw_mipi_dsi_rockchip_host_detach(void *priv_data,
1054                         struct mipi_dsi_device *device)
1055 {
1056     struct dw_mipi_dsi_rockchip *dsi = priv_data;
1057     struct device *second;
1058 
1059     second = dw_mipi_dsi_rockchip_find_second(dsi);
1060     if (second && !IS_ERR(second))
1061         component_del(second, &dw_mipi_dsi_rockchip_ops);
1062 
1063     component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);
1064 
1065     mutex_lock(&dsi->usage_mutex);
1066     dsi->usage_mode = DW_DSI_USAGE_IDLE;
1067     mutex_unlock(&dsi->usage_mutex);
1068 
1069     return 0;
1070 }
1071 
1072 static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = {
1073     .attach = dw_mipi_dsi_rockchip_host_attach,
1074     .detach = dw_mipi_dsi_rockchip_host_detach,
1075 };
1076 
1077 static int dw_mipi_dsi_rockchip_dphy_bind(struct device *dev,
1078                       struct device *master,
1079                       void *data)
1080 {
1081     /*
1082      * Nothing to do when used as a dphy.
1083      * Just make the rest of Rockchip-DRM happy
1084      * by being here.
1085      */
1086 
1087     return 0;
1088 }
1089 
1090 static void dw_mipi_dsi_rockchip_dphy_unbind(struct device *dev,
1091                          struct device *master,
1092                          void *data)
1093 {
1094     /* Nothing to do when used as a dphy. */
1095 }
1096 
1097 static const struct component_ops dw_mipi_dsi_rockchip_dphy_ops = {
1098     .bind   = dw_mipi_dsi_rockchip_dphy_bind,
1099     .unbind = dw_mipi_dsi_rockchip_dphy_unbind,
1100 };
1101 
1102 static int dw_mipi_dsi_dphy_init(struct phy *phy)
1103 {
1104     struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1105     int ret;
1106 
1107     mutex_lock(&dsi->usage_mutex);
1108 
1109     if (dsi->usage_mode != DW_DSI_USAGE_IDLE) {
1110         DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n");
1111         mutex_unlock(&dsi->usage_mutex);
1112         return -EBUSY;
1113     }
1114 
1115     dsi->usage_mode = DW_DSI_USAGE_PHY;
1116     mutex_unlock(&dsi->usage_mutex);
1117 
1118     ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops);
1119     if (ret < 0)
1120         goto err_graph;
1121 
1122     if (dsi->cdata->dphy_rx_init) {
1123         ret = clk_prepare_enable(dsi->pclk);
1124         if (ret < 0)
1125             goto err_init;
1126 
1127         ret = clk_prepare_enable(dsi->grf_clk);
1128         if (ret) {
1129             clk_disable_unprepare(dsi->pclk);
1130             goto err_init;
1131         }
1132 
1133         ret = dsi->cdata->dphy_rx_init(phy);
1134         clk_disable_unprepare(dsi->grf_clk);
1135         clk_disable_unprepare(dsi->pclk);
1136         if (ret < 0)
1137             goto err_init;
1138     }
1139 
1140     return 0;
1141 
1142 err_init:
1143     component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops);
1144 err_graph:
1145     mutex_lock(&dsi->usage_mutex);
1146     dsi->usage_mode = DW_DSI_USAGE_IDLE;
1147     mutex_unlock(&dsi->usage_mutex);
1148 
1149     return ret;
1150 }
1151 
1152 static int dw_mipi_dsi_dphy_exit(struct phy *phy)
1153 {
1154     struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1155 
1156     component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops);
1157 
1158     mutex_lock(&dsi->usage_mutex);
1159     dsi->usage_mode = DW_DSI_USAGE_IDLE;
1160     mutex_unlock(&dsi->usage_mutex);
1161 
1162     return 0;
1163 }
1164 
1165 static int dw_mipi_dsi_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
1166 {
1167     struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy;
1168     struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1169     int ret;
1170 
1171     ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);
1172     if (ret)
1173         return ret;
1174 
1175     dsi->dphy_config = *config;
1176     dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1);
1177 
1178     return 0;
1179 }
1180 
1181 static int dw_mipi_dsi_dphy_power_on(struct phy *phy)
1182 {
1183     struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1184     int i, ret;
1185 
1186     DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n",
1187               dsi->dphy_config.lanes, dsi->lane_mbps);
1188 
1189     i = max_mbps_to_parameter(dsi->lane_mbps);
1190     if (i < 0) {
1191         DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n",
1192                   dsi->lane_mbps);
1193         return i;
1194     }
1195 
1196     ret = pm_runtime_get_sync(dsi->dev);
1197     if (ret < 0) {
1198         DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret);
1199         return ret;
1200     }
1201 
1202     ret = clk_prepare_enable(dsi->pclk);
1203     if (ret) {
1204         DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret);
1205         goto err_pclk;
1206     }
1207 
1208     ret = clk_prepare_enable(dsi->grf_clk);
1209     if (ret) {
1210         DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
1211         goto err_grf_clk;
1212     }
1213 
1214     ret = clk_prepare_enable(dsi->phy_cfg_clk);
1215     if (ret) {
1216         DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret);
1217         goto err_phy_cfg_clk;
1218     }
1219 
1220     /* do soc-variant specific init */
1221     if (dsi->cdata->dphy_rx_power_on) {
1222         ret = dsi->cdata->dphy_rx_power_on(phy);
1223         if (ret < 0) {
1224             DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret);
1225             goto err_pwr_on;
1226         }
1227     }
1228 
1229     /*
1230      * Configure hsfreqrange according to frequency values
1231      * Set clock lane and hsfreqrange by lane0(test code 0x44)
1232      */
1233     dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_CLK, 0);
1234     dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
1235                   HSFREQRANGE_SEL(dppa_map[i].hsfreqrange));
1236     dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_1, 0);
1237     dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_2, 0);
1238     dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_3, 0);
1239 
1240     /* Normal operation */
1241     dw_mipi_dsi_phy_write(dsi, 0x0, 0);
1242 
1243     clk_disable_unprepare(dsi->phy_cfg_clk);
1244     clk_disable_unprepare(dsi->grf_clk);
1245 
1246     return ret;
1247 
1248 err_pwr_on:
1249     clk_disable_unprepare(dsi->phy_cfg_clk);
1250 err_phy_cfg_clk:
1251     clk_disable_unprepare(dsi->grf_clk);
1252 err_grf_clk:
1253     clk_disable_unprepare(dsi->pclk);
1254 err_pclk:
1255     pm_runtime_put(dsi->dev);
1256     return ret;
1257 }
1258 
1259 static int dw_mipi_dsi_dphy_power_off(struct phy *phy)
1260 {
1261     struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1262     int ret;
1263 
1264     ret = clk_prepare_enable(dsi->grf_clk);
1265     if (ret) {
1266         DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
1267         return ret;
1268     }
1269 
1270     if (dsi->cdata->dphy_rx_power_off) {
1271         ret = dsi->cdata->dphy_rx_power_off(phy);
1272         if (ret < 0)
1273             DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret);
1274     }
1275 
1276     clk_disable_unprepare(dsi->grf_clk);
1277     clk_disable_unprepare(dsi->pclk);
1278 
1279     pm_runtime_put(dsi->dev);
1280 
1281     return ret;
1282 }
1283 
1284 static const struct phy_ops dw_mipi_dsi_dphy_ops = {
1285     .configure  = dw_mipi_dsi_dphy_configure,
1286     .power_on   = dw_mipi_dsi_dphy_power_on,
1287     .power_off  = dw_mipi_dsi_dphy_power_off,
1288     .init       = dw_mipi_dsi_dphy_init,
1289     .exit       = dw_mipi_dsi_dphy_exit,
1290 };
1291 
1292 static int __maybe_unused dw_mipi_dsi_rockchip_resume(struct device *dev)
1293 {
1294     struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
1295     int ret;
1296 
1297     /*
1298      * Re-configure DSI state, if we were previously initialized. We need
1299      * to do this before rockchip_drm_drv tries to re-enable() any panels.
1300      */
1301     if (dsi->dsi_bound) {
1302         ret = clk_prepare_enable(dsi->grf_clk);
1303         if (ret) {
1304             DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
1305             return ret;
1306         }
1307 
1308         dw_mipi_dsi_rockchip_config(dsi);
1309         if (dsi->slave)
1310             dw_mipi_dsi_rockchip_config(dsi->slave);
1311 
1312         clk_disable_unprepare(dsi->grf_clk);
1313     }
1314 
1315     return 0;
1316 }
1317 
1318 static const struct dev_pm_ops dw_mipi_dsi_rockchip_pm_ops = {
1319     SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, dw_mipi_dsi_rockchip_resume)
1320 };
1321 
1322 static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
1323 {
1324     struct device *dev = &pdev->dev;
1325     struct device_node *np = dev->of_node;
1326     struct dw_mipi_dsi_rockchip *dsi;
1327     struct phy_provider *phy_provider;
1328     struct resource *res;
1329     const struct rockchip_dw_dsi_chip_data *cdata =
1330                 of_device_get_match_data(dev);
1331     int ret, i;
1332 
1333     dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1334     if (!dsi)
1335         return -ENOMEM;
1336 
1337     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1338     dsi->base = devm_ioremap_resource(dev, res);
1339     if (IS_ERR(dsi->base)) {
1340         DRM_DEV_ERROR(dev, "Unable to get dsi registers\n");
1341         return PTR_ERR(dsi->base);
1342     }
1343 
1344     i = 0;
1345     while (cdata[i].reg) {
1346         if (cdata[i].reg == res->start) {
1347             dsi->cdata = &cdata[i];
1348             break;
1349         }
1350 
1351         i++;
1352     }
1353 
1354     if (!dsi->cdata) {
1355         DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name);
1356         return -EINVAL;
1357     }
1358 
1359     /* try to get a possible external dphy */
1360     dsi->phy = devm_phy_optional_get(dev, "dphy");
1361     if (IS_ERR(dsi->phy)) {
1362         ret = PTR_ERR(dsi->phy);
1363         DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret);
1364         return ret;
1365     }
1366 
1367     dsi->pclk = devm_clk_get(dev, "pclk");
1368     if (IS_ERR(dsi->pclk)) {
1369         ret = PTR_ERR(dsi->pclk);
1370         DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret);
1371         return ret;
1372     }
1373 
1374     dsi->pllref_clk = devm_clk_get(dev, "ref");
1375     if (IS_ERR(dsi->pllref_clk)) {
1376         if (dsi->phy) {
1377             /*
1378              * if external phy is present, pll will be
1379              * generated there.
1380              */
1381             dsi->pllref_clk = NULL;
1382         } else {
1383             ret = PTR_ERR(dsi->pllref_clk);
1384             DRM_DEV_ERROR(dev,
1385                       "Unable to get pll reference clock: %d\n",
1386                       ret);
1387             return ret;
1388         }
1389     }
1390 
1391     if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
1392         dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1393         if (IS_ERR(dsi->phy_cfg_clk)) {
1394             ret = PTR_ERR(dsi->phy_cfg_clk);
1395             DRM_DEV_ERROR(dev,
1396                       "Unable to get phy_cfg_clk: %d\n", ret);
1397             return ret;
1398         }
1399     }
1400 
1401     if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) {
1402         dsi->grf_clk = devm_clk_get(dev, "grf");
1403         if (IS_ERR(dsi->grf_clk)) {
1404             ret = PTR_ERR(dsi->grf_clk);
1405             DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret);
1406             return ret;
1407         }
1408     }
1409 
1410     dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1411     if (IS_ERR(dsi->grf_regmap)) {
1412         DRM_DEV_ERROR(dev, "Unable to get rockchip,grf\n");
1413         return PTR_ERR(dsi->grf_regmap);
1414     }
1415 
1416     dsi->dev = dev;
1417     dsi->pdata.base = dsi->base;
1418     dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes;
1419     dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops;
1420     dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops;
1421     dsi->pdata.priv_data = dsi;
1422     platform_set_drvdata(pdev, dsi);
1423 
1424     mutex_init(&dsi->usage_mutex);
1425 
1426     dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops);
1427     if (IS_ERR(dsi->dphy)) {
1428         DRM_DEV_ERROR(&pdev->dev, "failed to create PHY\n");
1429         return PTR_ERR(dsi->dphy);
1430     }
1431 
1432     phy_set_drvdata(dsi->dphy, dsi);
1433     phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1434     if (IS_ERR(phy_provider))
1435         return PTR_ERR(phy_provider);
1436 
1437     dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata);
1438     if (IS_ERR(dsi->dmd)) {
1439         ret = PTR_ERR(dsi->dmd);
1440         if (ret != -EPROBE_DEFER)
1441             DRM_DEV_ERROR(dev,
1442                       "Failed to probe dw_mipi_dsi: %d\n", ret);
1443         return ret;
1444     }
1445 
1446     return 0;
1447 }
1448 
1449 static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev)
1450 {
1451     struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev);
1452 
1453     dw_mipi_dsi_remove(dsi->dmd);
1454 
1455     return 0;
1456 }
1457 
1458 static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = {
1459     {
1460         .reg = 0xff450000,
1461         .lcdsel_grf_reg = PX30_GRF_PD_VO_CON1,
1462         .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
1463         .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
1464                         PX30_DSI_LCDC_SEL),
1465 
1466         .lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1,
1467         .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
1468                          PX30_DSI_FORCERXMODE |
1469                          PX30_DSI_FORCETXSTOPMODE),
1470 
1471         .max_data_lanes = 4,
1472     },
1473     { /* sentinel */ }
1474 };
1475 
1476 static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
1477     {
1478         .reg = 0xff960000,
1479         .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1480         .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
1481         .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
1482 
1483         .max_data_lanes = 4,
1484     },
1485     {
1486         .reg = 0xff964000,
1487         .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1488         .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
1489         .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
1490 
1491         .max_data_lanes = 4,
1492     },
1493     { /* sentinel */ }
1494 };
1495 
1496 static int rk3399_dphy_tx1rx1_init(struct phy *phy)
1497 {
1498     struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1499 
1500     /*
1501      * Set TX1RX1 source to isp1.
1502      * Assume ISP0 is supplied by the RX0 dphy.
1503      */
1504     regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1505              HIWORD_UPDATE(0, RK3399_TXRX_SRC_SEL_ISP0));
1506     regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1507              HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));
1508     regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1509              HIWORD_UPDATE(0, RK3399_TXRX_BASEDIR));
1510     regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1511              HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));
1512 
1513     return 0;
1514 }
1515 
1516 static int rk3399_dphy_tx1rx1_power_on(struct phy *phy)
1517 {
1518     struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1519 
1520     /* tester reset pulse */
1521     dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_TESTCLR);
1522     usleep_range(100, 150);
1523 
1524     regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1525              HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));
1526     regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1527              HIWORD_UPDATE(RK3399_TXRX_BASEDIR, RK3399_TXRX_BASEDIR));
1528 
1529     regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1530              HIWORD_UPDATE(0, RK3399_DSI1_FORCERXMODE));
1531     regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1532              HIWORD_UPDATE(0, RK3399_DSI1_FORCETXSTOPMODE));
1533 
1534     /* Disable lane turn around, which is ignored in receive mode */
1535     regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1536              HIWORD_UPDATE(0, RK3399_TXRX_TURNREQUEST));
1537     regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1538              HIWORD_UPDATE(RK3399_DSI1_TURNDISABLE,
1539                    RK3399_DSI1_TURNDISABLE));
1540     usleep_range(100, 150);
1541 
1542     dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
1543     usleep_range(100, 150);
1544 
1545     /* Enable dphy lanes */
1546     regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1547              HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0),
1548                    RK3399_DSI1_ENABLE));
1549 
1550     usleep_range(100, 150);
1551 
1552     return 0;
1553 }
1554 
1555 static int rk3399_dphy_tx1rx1_power_off(struct phy *phy)
1556 {
1557     struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1558 
1559     regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1560              HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));
1561 
1562     return 0;
1563 }
1564 
1565 static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
1566     {
1567         .reg = 0xff960000,
1568         .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1569         .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
1570         .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,
1571                         RK3399_DSI0_LCDC_SEL),
1572 
1573         .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22,
1574         .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
1575                          RK3399_DSI0_TURNDISABLE |
1576                          RK3399_DSI0_FORCETXSTOPMODE |
1577                          RK3399_DSI0_FORCERXMODE),
1578 
1579         .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1580         .max_data_lanes = 4,
1581     },
1582     {
1583         .reg = 0xff968000,
1584         .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1585         .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
1586         .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL,
1587                         RK3399_DSI1_LCDC_SEL),
1588 
1589         .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23,
1590         .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |
1591                          RK3399_DSI1_FORCETXSTOPMODE |
1592                          RK3399_DSI1_FORCERXMODE |
1593                          RK3399_DSI1_ENABLE),
1594 
1595         .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24,
1596         .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ |
1597                       RK3399_TXRX_ENABLECLK,
1598                       RK3399_TXRX_MASTERSLAVEZ |
1599                       RK3399_TXRX_ENABLECLK |
1600                       RK3399_TXRX_BASEDIR),
1601 
1602         .enable_grf_reg = RK3399_GRF_SOC_CON23,
1603         .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),
1604 
1605         .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1606         .max_data_lanes = 4,
1607 
1608         .dphy_rx_init = rk3399_dphy_tx1rx1_init,
1609         .dphy_rx_power_on = rk3399_dphy_tx1rx1_power_on,
1610         .dphy_rx_power_off = rk3399_dphy_tx1rx1_power_off,
1611     },
1612     { /* sentinel */ }
1613 };
1614 
1615 static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
1616     {
1617      .compatible = "rockchip,px30-mipi-dsi",
1618      .data = &px30_chip_data,
1619     }, {
1620      .compatible = "rockchip,rk3288-mipi-dsi",
1621      .data = &rk3288_chip_data,
1622     }, {
1623      .compatible = "rockchip,rk3399-mipi-dsi",
1624      .data = &rk3399_chip_data,
1625     },
1626     { /* sentinel */ }
1627 };
1628 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids);
1629 
1630 struct platform_driver dw_mipi_dsi_rockchip_driver = {
1631     .probe      = dw_mipi_dsi_rockchip_probe,
1632     .remove     = dw_mipi_dsi_rockchip_remove,
1633     .driver     = {
1634         .of_match_table = dw_mipi_dsi_rockchip_dt_ids,
1635         .pm = &dw_mipi_dsi_rockchip_pm_ops,
1636         .name   = "dw-mipi-dsi-rockchip",
1637     },
1638 };
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