drm/rockchip/cdn-dp-core.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2016 Chris Zhong <zyw@rock-chips.com>
0004  * Copyright (C) 2016 ROCKCHIP, Inc.
0005  */
0006
0007 #ifndef _CDN_DP_CORE_H
0008 #define _CDN_DP_CORE_H
0009
0010 #include <drm/display/drm_dp_helper.h>
0011 #include <drm/drm_panel.h>
0012 #include <drm/drm_probe_helper.h>
0013 #include <sound/hdmi-codec.h>
0014
0015 #include "rockchip_drm_drv.h"
0016
0017 #define MAX_PHY     2
0018
0019 enum audio_format {
0020     AFMT_I2S = 0,
0021     AFMT_SPDIF = 1,
0022     AFMT_UNUSED,
0023 };
0024
0025 struct audio_info {
0026     enum audio_format format;
0027     int sample_rate;
0028     int channels;
0029     int sample_width;
0030 };
0031
0032 enum vic_pxl_encoding_format {
0033     PXL_RGB = 0x1,
0034     YCBCR_4_4_4 = 0x2,
0035     YCBCR_4_2_2 = 0x4,
0036     YCBCR_4_2_0 = 0x8,
0037     Y_ONLY = 0x10,
0038 };
0039
0040 struct video_info {
0041     bool h_sync_polarity;
0042     bool v_sync_polarity;
0043     bool interlaced;
0044     int color_depth;
0045     enum vic_pxl_encoding_format color_fmt;
0046 };
0047
0048 struct cdn_firmware_header {
0049     u32 size_bytes; /* size of the entire header+image(s) in bytes */
0050     u32 header_size; /* size of just the header in bytes */
0051     u32 iram_size; /* size of iram */
0052     u32 dram_size; /* size of dram */
0053 };
0054
0055 struct cdn_dp_port {
0056     struct cdn_dp_device *dp;
0057     struct notifier_block event_nb;
0058     struct extcon_dev *extcon;
0059     struct phy *phy;
0060     u8 lanes;
0061     bool phy_enabled;
0062     u8 id;
0063 };
0064
0065 struct cdn_dp_device {
0066     struct device *dev;
0067     struct drm_device *drm_dev;
0068     struct drm_connector connector;
0069     struct rockchip_encoder encoder;
0070     struct drm_display_mode mode;
0071     struct platform_device *audio_pdev;
0072     struct work_struct event_work;
0073     struct edid *edid;
0074
0075     struct mutex lock;
0076     bool connected;
0077     bool active;
0078     bool suspended;
0079
0080     const struct firmware *fw;  /* cdn dp firmware */
0081     unsigned int fw_version;    /* cdn fw version */
0082     bool fw_loaded;
0083
0084     void __iomem *regs;
0085     struct regmap *grf;
0086     struct clk *core_clk;
0087     struct clk *pclk;
0088     struct clk *spdif_clk;
0089     struct clk *grf_clk;
0090     struct reset_control *spdif_rst;
0091     struct reset_control *dptx_rst;
0092     struct reset_control *apb_rst;
0093     struct reset_control *core_rst;
0094     struct audio_info audio_info;
0095     struct video_info video_info;
0096     struct cdn_dp_port *port[MAX_PHY];
0097     u8 ports;
0098     u8 max_lanes;
0099     unsigned int max_rate;
0100     u8 lanes;
0101     int active_port;
0102
0103     u8 dpcd[DP_RECEIVER_CAP_SIZE];
0104     bool sink_has_audio;
0105
0106     hdmi_codec_plugged_cb plugged_cb;
0107     struct device *codec_dev;
0108 };
0109 #endif  /* _CDN_DP_CORE_H */