drm/rockchip/analogix_dp-rockchip.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Rockchip SoC DP (Display Port) interface driver.
0004  *
0005  * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
0006  * Author: Andy Yan <andy.yan@rock-chips.com>
0007  *         Yakir Yang <ykk@rock-chips.com>
0008  *         Jeff Chen <jeff.chen@rock-chips.com>
0009  */
0010
0011 #include <linux/component.h>
0012 #include <linux/mfd/syscon.h>
0013 #include <linux/of_device.h>
0014 #include <linux/of_graph.h>
0015 #include <linux/regmap.h>
0016 #include <linux/reset.h>
0017 #include <linux/clk.h>
0018
0019 #include <video/of_videomode.h>
0020 #include <video/videomode.h>
0021
0022 #include <drm/display/drm_dp_helper.h>
0023 #include <drm/drm_atomic.h>
0024 #include <drm/drm_atomic_helper.h>
0025 #include <drm/bridge/analogix_dp.h>
0026 #include <drm/drm_of.h>
0027 #include <drm/drm_panel.h>
0028 #include <drm/drm_probe_helper.h>
0029 #include <drm/drm_simple_kms_helper.h>
0030
0031 #include "rockchip_drm_drv.h"
0032 #include "rockchip_drm_vop.h"
0033
0034 #define RK3288_GRF_SOC_CON6     0x25c
0035 #define RK3288_EDP_LCDC_SEL     BIT(5)
0036 #define RK3399_GRF_SOC_CON20        0x6250
0037 #define RK3399_EDP_LCDC_SEL     BIT(5)
0038
0039 #define HIWORD_UPDATE(val, mask)    (val | (mask) << 16)
0040
0041 #define PSR_WAIT_LINE_FLAG_TIMEOUT_MS   100
0042
0043 /**
0044  * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
0045  * @lcdsel_grf_reg: grf register offset of lcdc select
0046  * @lcdsel_big: reg value of selecting vop big for eDP
0047  * @lcdsel_lit: reg value of selecting vop little for eDP
0048  * @chip_type: specific chip type
0049  */
0050 struct rockchip_dp_chip_data {
0051     u32 lcdsel_grf_reg;
0052     u32 lcdsel_big;
0053     u32 lcdsel_lit;
0054     u32 chip_type;
0055 };
0056
0057 struct rockchip_dp_device {
0058     struct drm_device        *drm_dev;
0059     struct device            *dev;
0060     struct rockchip_encoder  encoder;
0061     struct drm_display_mode  mode;
0062
0063     struct clk               *pclk;
0064     struct clk               *grfclk;
0065     struct regmap            *grf;
0066     struct reset_control     *rst;
0067
0068     const struct rockchip_dp_chip_data *data;
0069
0070     struct analogix_dp_device *adp;
0071     struct analogix_dp_plat_data plat_data;
0072 };
0073
0074 static struct rockchip_dp_device *encoder_to_dp(struct drm_encoder *encoder)
0075 {
0076     struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
0077
0078     return container_of(rkencoder, struct rockchip_dp_device, encoder);
0079 }
0080
0081 static struct rockchip_dp_device *pdata_encoder_to_dp(struct analogix_dp_plat_data *plat_data)
0082 {
0083     return container_of(plat_data, struct rockchip_dp_device, plat_data);
0084 }
0085
0086 static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
0087 {
0088     reset_control_assert(dp->rst);
0089     usleep_range(10, 20);
0090     reset_control_deassert(dp->rst);
0091
0092     return 0;
0093 }
0094
0095 static int rockchip_dp_poweron_start(struct analogix_dp_plat_data *plat_data)
0096 {
0097     struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data);
0098     int ret;
0099
0100     ret = clk_prepare_enable(dp->pclk);
0101     if (ret < 0) {
0102         DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
0103         return ret;
0104     }
0105
0106     ret = rockchip_dp_pre_init(dp);
0107     if (ret < 0) {
0108         DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret);
0109         clk_disable_unprepare(dp->pclk);
0110         return ret;
0111     }
0112
0113     return ret;
0114 }
0115
0116 static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
0117 {
0118     struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data);
0119
0120     clk_disable_unprepare(dp->pclk);
0121
0122     return 0;
0123 }
0124
0125 static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
0126                  struct drm_connector *connector)
0127 {
0128     struct drm_display_info *di = &connector->display_info;
0129     /* VOP couldn't output YUV video format for eDP rightly */
0130     u32 mask = DRM_COLOR_FORMAT_YCBCR444 | DRM_COLOR_FORMAT_YCBCR422;
0131
0132     if ((di->color_formats & mask)) {
0133         DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n");
0134         di->color_formats &= ~mask;
0135         di->color_formats |= DRM_COLOR_FORMAT_RGB444;
0136         di->bpc = 8;
0137     }
0138
0139     return 0;
0140 }
0141
0142 static bool
0143 rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
0144                    const struct drm_display_mode *mode,
0145                    struct drm_display_mode *adjusted_mode)
0146 {
0147     /* do nothing */
0148     return true;
0149 }
0150
0151 static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
0152                          struct drm_display_mode *mode,
0153                          struct drm_display_mode *adjusted)
0154 {
0155     /* do nothing */
0156 }
0157
0158 static
0159 struct drm_crtc *rockchip_dp_drm_get_new_crtc(struct drm_encoder *encoder,
0160                           struct drm_atomic_state *state)
0161 {
0162     struct drm_connector *connector;
0163     struct drm_connector_state *conn_state;
0164
0165     connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
0166     if (!connector)
0167         return NULL;
0168
0169     conn_state = drm_atomic_get_new_connector_state(state, connector);
0170     if (!conn_state)
0171         return NULL;
0172
0173     return conn_state->crtc;
0174 }
0175
0176 static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder,
0177                        struct drm_atomic_state *state)
0178 {
0179     struct rockchip_dp_device *dp = encoder_to_dp(encoder);
0180     struct drm_crtc *crtc;
0181     struct drm_crtc_state *old_crtc_state;
0182     int ret;
0183     u32 val;
0184
0185     crtc = rockchip_dp_drm_get_new_crtc(encoder, state);
0186     if (!crtc)
0187         return;
0188
0189     old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
0190     /* Coming back from self refresh, nothing to do */
0191     if (old_crtc_state && old_crtc_state->self_refresh_active)
0192         return;
0193
0194     ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
0195     if (ret < 0)
0196         return;
0197
0198     if (ret)
0199         val = dp->data->lcdsel_lit;
0200     else
0201         val = dp->data->lcdsel_big;
0202
0203     DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
0204
0205     ret = clk_prepare_enable(dp->grfclk);
0206     if (ret < 0) {
0207         DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret);
0208         return;
0209     }
0210
0211     ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
0212     if (ret != 0)
0213         DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);
0214
0215     clk_disable_unprepare(dp->grfclk);
0216 }
0217
0218 static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder,
0219                         struct drm_atomic_state *state)
0220 {
0221     struct rockchip_dp_device *dp = encoder_to_dp(encoder);
0222     struct drm_crtc *crtc;
0223     struct drm_crtc_state *new_crtc_state = NULL;
0224     int ret;
0225
0226     crtc = rockchip_dp_drm_get_new_crtc(encoder, state);
0227     /* No crtc means we're doing a full shutdown */
0228     if (!crtc)
0229         return;
0230
0231     new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
0232     /* If we're not entering self-refresh, no need to wait for vact */
0233     if (!new_crtc_state || !new_crtc_state->self_refresh_active)
0234         return;
0235
0236     ret = rockchip_drm_wait_vact_end(crtc, PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
0237     if (ret)
0238         DRM_DEV_ERROR(dp->dev, "line flag irq timed out\n");
0239 }
0240
0241 static int
0242 rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
0243                       struct drm_crtc_state *crtc_state,
0244                       struct drm_connector_state *conn_state)
0245 {
0246     struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
0247     struct drm_display_info *di = &conn_state->connector->display_info;
0248
0249     /*
0250      * The hardware IC designed that VOP must output the RGB10 video
0251      * format to eDP controller, and if eDP panel only support RGB8,
0252      * then eDP controller should cut down the video data, not via VOP
0253      * controller, that's why we need to hardcode the VOP output mode
0254      * to RGA10 here.
0255      */
0256
0257     s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
0258     s->output_type = DRM_MODE_CONNECTOR_eDP;
0259     s->output_bpc = di->bpc;
0260
0261     return 0;
0262 }
0263
0264 static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
0265     .mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
0266     .mode_set = rockchip_dp_drm_encoder_mode_set,
0267     .atomic_enable = rockchip_dp_drm_encoder_enable,
0268     .atomic_disable = rockchip_dp_drm_encoder_disable,
0269     .atomic_check = rockchip_dp_drm_encoder_atomic_check,
0270 };
0271
0272 static int rockchip_dp_of_probe(struct rockchip_dp_device *dp)
0273 {
0274     struct device *dev = dp->dev;
0275     struct device_node *np = dev->of_node;
0276
0277     dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
0278     if (IS_ERR(dp->grf)) {
0279         DRM_DEV_ERROR(dev, "failed to get rockchip,grf property\n");
0280         return PTR_ERR(dp->grf);
0281     }
0282
0283     dp->grfclk = devm_clk_get(dev, "grf");
0284     if (PTR_ERR(dp->grfclk) == -ENOENT) {
0285         dp->grfclk = NULL;
0286     } else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
0287         return -EPROBE_DEFER;
0288     } else if (IS_ERR(dp->grfclk)) {
0289         DRM_DEV_ERROR(dev, "failed to get grf clock\n");
0290         return PTR_ERR(dp->grfclk);
0291     }
0292
0293     dp->pclk = devm_clk_get(dev, "pclk");
0294     if (IS_ERR(dp->pclk)) {
0295         DRM_DEV_ERROR(dev, "failed to get pclk property\n");
0296         return PTR_ERR(dp->pclk);
0297     }
0298
0299     dp->rst = devm_reset_control_get(dev, "dp");
0300     if (IS_ERR(dp->rst)) {
0301         DRM_DEV_ERROR(dev, "failed to get dp reset control\n");
0302         return PTR_ERR(dp->rst);
0303     }
0304
0305     return 0;
0306 }
0307
0308 static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
0309 {
0310     struct drm_encoder *encoder = &dp->encoder.encoder;
0311     struct drm_device *drm_dev = dp->drm_dev;
0312     struct device *dev = dp->dev;
0313     int ret;
0314
0315     encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
0316                                  dev->of_node);
0317     DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
0318
0319     ret = drm_simple_encoder_init(drm_dev, encoder,
0320                       DRM_MODE_ENCODER_TMDS);
0321     if (ret) {
0322         DRM_ERROR("failed to initialize encoder with drm\n");
0323         return ret;
0324     }
0325
0326     drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
0327
0328     return 0;
0329 }
0330
0331 static int rockchip_dp_bind(struct device *dev, struct device *master,
0332                 void *data)
0333 {
0334     struct rockchip_dp_device *dp = dev_get_drvdata(dev);
0335     struct drm_device *drm_dev = data;
0336     int ret;
0337
0338     dp->drm_dev = drm_dev;
0339
0340     ret = rockchip_dp_drm_create_encoder(dp);
0341     if (ret) {
0342         DRM_ERROR("failed to create drm encoder\n");
0343         return ret;
0344     }
0345
0346     dp->plat_data.encoder = &dp->encoder.encoder;
0347
0348     ret = analogix_dp_bind(dp->adp, drm_dev);
0349     if (ret)
0350         goto err_cleanup_encoder;
0351
0352     return 0;
0353 err_cleanup_encoder:
0354     dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder);
0355     return ret;
0356 }
0357
0358 static void rockchip_dp_unbind(struct device *dev, struct device *master,
0359                    void *data)
0360 {
0361     struct rockchip_dp_device *dp = dev_get_drvdata(dev);
0362
0363     analogix_dp_unbind(dp->adp);
0364     dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder);
0365 }
0366
0367 static const struct component_ops rockchip_dp_component_ops = {
0368     .bind = rockchip_dp_bind,
0369     .unbind = rockchip_dp_unbind,
0370 };
0371
0372 static int rockchip_dp_probe(struct platform_device *pdev)
0373 {
0374     struct device *dev = &pdev->dev;
0375     const struct rockchip_dp_chip_data *dp_data;
0376     struct drm_panel *panel = NULL;
0377     struct rockchip_dp_device *dp;
0378     int ret;
0379
0380     dp_data = of_device_get_match_data(dev);
0381     if (!dp_data)
0382         return -ENODEV;
0383
0384     ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
0385     if (ret < 0)
0386         return ret;
0387
0388     dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
0389     if (!dp)
0390         return -ENOMEM;
0391
0392     dp->dev = dev;
0393     dp->adp = ERR_PTR(-ENODEV);
0394     dp->data = dp_data;
0395     dp->plat_data.panel = panel;
0396     dp->plat_data.dev_type = dp->data->chip_type;
0397     dp->plat_data.power_on_start = rockchip_dp_poweron_start;
0398     dp->plat_data.power_off = rockchip_dp_powerdown;
0399     dp->plat_data.get_modes = rockchip_dp_get_modes;
0400
0401     ret = rockchip_dp_of_probe(dp);
0402     if (ret < 0)
0403         return ret;
0404
0405     platform_set_drvdata(pdev, dp);
0406
0407     dp->adp = analogix_dp_probe(dev, &dp->plat_data);
0408     if (IS_ERR(dp->adp))
0409         return PTR_ERR(dp->adp);
0410
0411     ret = component_add(dev, &rockchip_dp_component_ops);
0412     if (ret)
0413         goto err_dp_remove;
0414
0415     return 0;
0416
0417 err_dp_remove:
0418     analogix_dp_remove(dp->adp);
0419     return ret;
0420 }
0421
0422 static int rockchip_dp_remove(struct platform_device *pdev)
0423 {
0424     struct rockchip_dp_device *dp = platform_get_drvdata(pdev);
0425
0426     component_del(&pdev->dev, &rockchip_dp_component_ops);
0427     analogix_dp_remove(dp->adp);
0428
0429     return 0;
0430 }
0431
0432 #ifdef CONFIG_PM_SLEEP
0433 static int rockchip_dp_suspend(struct device *dev)
0434 {
0435     struct rockchip_dp_device *dp = dev_get_drvdata(dev);
0436
0437     if (IS_ERR(dp->adp))
0438         return 0;
0439
0440     return analogix_dp_suspend(dp->adp);
0441 }
0442
0443 static int rockchip_dp_resume(struct device *dev)
0444 {
0445     struct rockchip_dp_device *dp = dev_get_drvdata(dev);
0446
0447     if (IS_ERR(dp->adp))
0448         return 0;
0449
0450     return analogix_dp_resume(dp->adp);
0451 }
0452 #endif
0453
0454 static const struct dev_pm_ops rockchip_dp_pm_ops = {
0455 #ifdef CONFIG_PM_SLEEP
0456     .suspend_late = rockchip_dp_suspend,
0457     .resume_early = rockchip_dp_resume,
0458 #endif
0459 };
0460
0461 static const struct rockchip_dp_chip_data rk3399_edp = {
0462     .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
0463     .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
0464     .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
0465     .chip_type = RK3399_EDP,
0466 };
0467
0468 static const struct rockchip_dp_chip_data rk3288_dp = {
0469     .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
0470     .lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
0471     .lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
0472     .chip_type = RK3288_DP,
0473 };
0474
0475 static const struct of_device_id rockchip_dp_dt_ids[] = {
0476     {.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
0477     {.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
0478     {}
0479 };
0480 MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
0481
0482 struct platform_driver rockchip_dp_driver = {
0483     .probe = rockchip_dp_probe,
0484     .remove = rockchip_dp_remove,
0485     .driver = {
0486            .name = "rockchip-dp",
0487            .pm = &rockchip_dp_pm_ops,
0488            .of_match_table = rockchip_dp_dt_ids,
0489     },
0490 };