drm/rcar-du/rcar_mipi_dsi_regs.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * R-Car MIPI DSI Interface Registers Definitions
0004  *
0005  * Copyright (C) 2020 Renesas Electronics Corporation
0006  */
0007
0008 #ifndef __RCAR_MIPI_DSI_REGS_H__
0009 #define __RCAR_MIPI_DSI_REGS_H__
0010
0011 #define LINKSR              0x010
0012 #define LINKSR_LPBUSY           (1 << 1)
0013 #define LINKSR_HSBUSY           (1 << 0)
0014
0015 /*
0016  * Video Mode Register
0017  */
0018 #define TXVMSETR            0x180
0019 #define TXVMSETR_SYNSEQ_PULSES      (0 << 16)
0020 #define TXVMSETR_SYNSEQ_EVENTS      (1 << 16)
0021 #define TXVMSETR_VSTPM          (1 << 15)
0022 #define TXVMSETR_PIXWDTH        (1 << 8)
0023 #define TXVMSETR_VSEN_EN        (1 << 4)
0024 #define TXVMSETR_VSEN_DIS       (0 << 4)
0025 #define TXVMSETR_HFPBPEN_EN     (1 << 2)
0026 #define TXVMSETR_HFPBPEN_DIS        (0 << 2)
0027 #define TXVMSETR_HBPBPEN_EN     (1 << 1)
0028 #define TXVMSETR_HBPBPEN_DIS        (0 << 1)
0029 #define TXVMSETR_HSABPEN_EN     (1 << 0)
0030 #define TXVMSETR_HSABPEN_DIS        (0 << 0)
0031
0032 #define TXVMCR              0x190
0033 #define TXVMCR_VFCLR            (1 << 12)
0034 #define TXVMCR_EN_VIDEO         (1 << 0)
0035
0036 #define TXVMSR              0x1a0
0037 #define TXVMSR_STR          (1 << 16)
0038 #define TXVMSR_VFRDY            (1 << 12)
0039 #define TXVMSR_ACT          (1 << 8)
0040 #define TXVMSR_RDY          (1 << 0)
0041
0042 #define TXVMSCR             0x1a4
0043 #define TXVMSCR_STR         (1 << 16)
0044
0045 #define TXVMPSPHSETR            0x1c0
0046 #define TXVMPSPHSETR_DT_RGB16       (0x0e << 16)
0047 #define TXVMPSPHSETR_DT_RGB18       (0x1e << 16)
0048 #define TXVMPSPHSETR_DT_RGB18_LS    (0x2e << 16)
0049 #define TXVMPSPHSETR_DT_RGB24       (0x3e << 16)
0050 #define TXVMPSPHSETR_DT_YCBCR16     (0x2c << 16)
0051
0052 #define TXVMVPRMSET0R           0x1d0
0053 #define TXVMVPRMSET0R_HSPOL_HIG     (0 << 17)
0054 #define TXVMVPRMSET0R_HSPOL_LOW     (1 << 17)
0055 #define TXVMVPRMSET0R_VSPOL_HIG     (0 << 16)
0056 #define TXVMVPRMSET0R_VSPOL_LOW     (1 << 16)
0057 #define TXVMVPRMSET0R_CSPC_RGB      (0 << 4)
0058 #define TXVMVPRMSET0R_CSPC_YCbCr    (1 << 4)
0059 #define TXVMVPRMSET0R_BPP_16        (0 << 0)
0060 #define TXVMVPRMSET0R_BPP_18        (1 << 0)
0061 #define TXVMVPRMSET0R_BPP_24        (2 << 0)
0062
0063 #define TXVMVPRMSET1R           0x1d4
0064 #define TXVMVPRMSET1R_VACTIVE(x)    (((x) & 0x7fff) << 16)
0065 #define TXVMVPRMSET1R_VSA(x)        (((x) & 0xfff) << 0)
0066
0067 #define TXVMVPRMSET2R           0x1d8
0068 #define TXVMVPRMSET2R_VFP(x)        (((x) & 0x1fff) << 16)
0069 #define TXVMVPRMSET2R_VBP(x)        (((x) & 0x1fff) << 0)
0070
0071 #define TXVMVPRMSET3R           0x1dc
0072 #define TXVMVPRMSET3R_HACTIVE(x)    (((x) & 0x7fff) << 16)
0073 #define TXVMVPRMSET3R_HSA(x)        (((x) & 0xfff) << 0)
0074
0075 #define TXVMVPRMSET4R           0x1e0
0076 #define TXVMVPRMSET4R_HFP(x)        (((x) & 0x1fff) << 16)
0077 #define TXVMVPRMSET4R_HBP(x)        (((x) & 0x1fff) << 0)
0078
0079 /*
0080  * PHY-Protocol Interface (PPI) Registers
0081  */
0082 #define PPISETR             0x700
0083 #define PPISETR_DLEN_0          (0x1 << 0)
0084 #define PPISETR_DLEN_1          (0x3 << 0)
0085 #define PPISETR_DLEN_2          (0x7 << 0)
0086 #define PPISETR_DLEN_3          (0xf << 0)
0087 #define PPISETR_CLEN            (1 << 8)
0088
0089 #define PPICLCR             0x710
0090 #define PPICLCR_TXREQHS         (1 << 8)
0091 #define PPICLCR_TXULPSEXT       (1 << 1)
0092 #define PPICLCR_TXULPSCLK       (1 << 0)
0093
0094 #define PPICLSR             0x720
0095 #define PPICLSR_HSTOLP          (1 << 27)
0096 #define PPICLSR_TOHS            (1 << 26)
0097 #define PPICLSR_STPST           (1 << 0)
0098
0099 #define PPICLSCR            0x724
0100 #define PPICLSCR_HSTOLP         (1 << 27)
0101 #define PPICLSCR_TOHS           (1 << 26)
0102
0103 #define PPIDLSR             0x760
0104 #define PPIDLSR_STPST           (0xf << 0)
0105
0106 /*
0107  * Clocks registers
0108  */
0109 #define LPCLKSET            0x1000
0110 #define LPCLKSET_CKEN           (1 << 8)
0111 #define LPCLKSET_LPCLKDIV(x)        (((x) & 0x3f) << 0)
0112
0113 #define CFGCLKSET           0x1004
0114 #define CFGCLKSET_CKEN          (1 << 8)
0115 #define CFGCLKSET_CFGCLKDIV(x)      (((x) & 0x3f) << 0)
0116
0117 #define DOTCLKDIV           0x1008
0118 #define DOTCLKDIV_CKEN          (1 << 8)
0119 #define DOTCLKDIV_DOTCLKDIV(x)      (((x) & 0x3f) << 0)
0120
0121 #define VCLKSET             0x100c
0122 #define VCLKSET_CKEN            (1 << 16)
0123 #define VCLKSET_COLOR_RGB       (0 << 8)
0124 #define VCLKSET_COLOR_YCC       (1 << 8)
0125 #define VCLKSET_DIV(x)          (((x) & 0x3) << 4)
0126 #define VCLKSET_BPP_16          (0 << 2)
0127 #define VCLKSET_BPP_18          (1 << 2)
0128 #define VCLKSET_BPP_18L         (2 << 2)
0129 #define VCLKSET_BPP_24          (3 << 2)
0130 #define VCLKSET_LANE(x)         (((x) & 0x3) << 0)
0131
0132 #define VCLKEN              0x1010
0133 #define VCLKEN_CKEN         (1 << 0)
0134
0135 #define PHYSETUP            0x1014
0136 #define PHYSETUP_HSFREQRANGE(x)     (((x) & 0x7f) << 16)
0137 #define PHYSETUP_HSFREQRANGE_MASK   (0x7f << 16)
0138 #define PHYSETUP_CFGCLKFREQRANGE(x) (((x) & 0x3f) << 8)
0139 #define PHYSETUP_SHUTDOWNZ      (1 << 1)
0140 #define PHYSETUP_RSTZ           (1 << 0)
0141
0142 #define CLOCKSET1           0x101c
0143 #define CLOCKSET1_LOCK_PHY      (1 << 17)
0144 #define CLOCKSET1_LOCK          (1 << 16)
0145 #define CLOCKSET1_CLKSEL        (1 << 8)
0146 #define CLOCKSET1_CLKINSEL_EXTAL    (0 << 2)
0147 #define CLOCKSET1_CLKINSEL_DIG      (1 << 2)
0148 #define CLOCKSET1_CLKINSEL_DU       (1 << 3)
0149 #define CLOCKSET1_SHADOW_CLEAR      (1 << 1)
0150 #define CLOCKSET1_UPDATEPLL     (1 << 0)
0151
0152 #define CLOCKSET2           0x1020
0153 #define CLOCKSET2_M(x)          (((x) & 0xfff) << 16)
0154 #define CLOCKSET2_VCO_CNTRL(x)      (((x) & 0x3f) << 8)
0155 #define CLOCKSET2_N(x)          (((x) & 0xf) << 0)
0156
0157 #define CLOCKSET3           0x1024
0158 #define CLOCKSET3_PROP_CNTRL(x)     (((x) & 0x3f) << 24)
0159 #define CLOCKSET3_INT_CNTRL(x)      (((x) & 0x3f) << 16)
0160 #define CLOCKSET3_CPBIAS_CNTRL(x)   (((x) & 0x7f) << 8)
0161 #define CLOCKSET3_GMP_CNTRL(x)      (((x) & 0x3) << 0)
0162
0163 #define PHTW                0x1034
0164 #define PHTW_DWEN           (1 << 24)
0165 #define PHTW_TESTDIN_DATA(x)        (((x) & 0xff) << 16)
0166 #define PHTW_CWEN           (1 << 8)
0167 #define PHTW_TESTDIN_CODE(x)        (((x) & 0xff) << 0)
0168
0169 #define PHTC                0x103c
0170 #define PHTC_TESTCLR            (1 << 0)
0171
0172 #endif /* __RCAR_MIPI_DSI_REGS_H__ */