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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * R-Car MIPI DSI Encoder
0004  *
0005  * Copyright (C) 2020 Renesas Electronics Corporation
0006  */
0007 
0008 #include <linux/clk.h>
0009 #include <linux/delay.h>
0010 #include <linux/io.h>
0011 #include <linux/iopoll.h>
0012 #include <linux/module.h>
0013 #include <linux/of.h>
0014 #include <linux/of_device.h>
0015 #include <linux/of_graph.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/reset.h>
0018 #include <linux/slab.h>
0019 
0020 #include <drm/drm_atomic.h>
0021 #include <drm/drm_atomic_helper.h>
0022 #include <drm/drm_bridge.h>
0023 #include <drm/drm_mipi_dsi.h>
0024 #include <drm/drm_of.h>
0025 #include <drm/drm_panel.h>
0026 #include <drm/drm_probe_helper.h>
0027 
0028 #include "rcar_mipi_dsi_regs.h"
0029 
0030 struct rcar_mipi_dsi {
0031     struct device *dev;
0032     const struct rcar_mipi_dsi_device_info *info;
0033     struct reset_control *rstc;
0034 
0035     struct mipi_dsi_host host;
0036     struct drm_bridge bridge;
0037     struct drm_bridge *next_bridge;
0038     struct drm_connector connector;
0039 
0040     void __iomem *mmio;
0041     struct {
0042         struct clk *mod;
0043         struct clk *pll;
0044         struct clk *dsi;
0045     } clocks;
0046 
0047     enum mipi_dsi_pixel_format format;
0048     unsigned int num_data_lanes;
0049     unsigned int lanes;
0050 };
0051 
0052 static inline struct rcar_mipi_dsi *
0053 bridge_to_rcar_mipi_dsi(struct drm_bridge *bridge)
0054 {
0055     return container_of(bridge, struct rcar_mipi_dsi, bridge);
0056 }
0057 
0058 static inline struct rcar_mipi_dsi *
0059 host_to_rcar_mipi_dsi(struct mipi_dsi_host *host)
0060 {
0061     return container_of(host, struct rcar_mipi_dsi, host);
0062 }
0063 
0064 static const u32 phtw[] = {
0065     0x01020114, 0x01600115, /* General testing */
0066     0x01030116, 0x0102011d, /* General testing */
0067     0x011101a4, 0x018601a4, /* 1Gbps testing */
0068     0x014201a0, 0x010001a3, /* 1Gbps testing */
0069     0x0101011f,     /* 1Gbps testing */
0070 };
0071 
0072 static const u32 phtw2[] = {
0073     0x010c0130, 0x010c0140, /* General testing */
0074     0x010c0150, 0x010c0180, /* General testing */
0075     0x010c0190,
0076     0x010a0160, 0x010a0170,
0077     0x01800164, 0x01800174, /* 1Gbps testing */
0078 };
0079 
0080 static const u32 hsfreqrange_table[][2] = {
0081     { 80000000U,   0x00 }, { 90000000U,   0x10 }, { 100000000U,  0x20 },
0082     { 110000000U,  0x30 }, { 120000000U,  0x01 }, { 130000000U,  0x11 },
0083     { 140000000U,  0x21 }, { 150000000U,  0x31 }, { 160000000U,  0x02 },
0084     { 170000000U,  0x12 }, { 180000000U,  0x22 }, { 190000000U,  0x32 },
0085     { 205000000U,  0x03 }, { 220000000U,  0x13 }, { 235000000U,  0x23 },
0086     { 250000000U,  0x33 }, { 275000000U,  0x04 }, { 300000000U,  0x14 },
0087     { 325000000U,  0x25 }, { 350000000U,  0x35 }, { 400000000U,  0x05 },
0088     { 450000000U,  0x16 }, { 500000000U,  0x26 }, { 550000000U,  0x37 },
0089     { 600000000U,  0x07 }, { 650000000U,  0x18 }, { 700000000U,  0x28 },
0090     { 750000000U,  0x39 }, { 800000000U,  0x09 }, { 850000000U,  0x19 },
0091     { 900000000U,  0x29 }, { 950000000U,  0x3a }, { 1000000000U, 0x0a },
0092     { 1050000000U, 0x1a }, { 1100000000U, 0x2a }, { 1150000000U, 0x3b },
0093     { 1200000000U, 0x0b }, { 1250000000U, 0x1b }, { 1300000000U, 0x2b },
0094     { 1350000000U, 0x3c }, { 1400000000U, 0x0c }, { 1450000000U, 0x1c },
0095     { 1500000000U, 0x2c }, { 1550000000U, 0x3d }, { 1600000000U, 0x0d },
0096     { 1650000000U, 0x1d }, { 1700000000U, 0x2e }, { 1750000000U, 0x3e },
0097     { 1800000000U, 0x0e }, { 1850000000U, 0x1e }, { 1900000000U, 0x2f },
0098     { 1950000000U, 0x3f }, { 2000000000U, 0x0f }, { 2050000000U, 0x40 },
0099     { 2100000000U, 0x41 }, { 2150000000U, 0x42 }, { 2200000000U, 0x43 },
0100     { 2250000000U, 0x44 }, { 2300000000U, 0x45 }, { 2350000000U, 0x46 },
0101     { 2400000000U, 0x47 }, { 2450000000U, 0x48 }, { 2500000000U, 0x49 },
0102     { /* sentinel */ },
0103 };
0104 
0105 struct vco_cntrl_value {
0106     u32 min_freq;
0107     u32 max_freq;
0108     u16 value;
0109 };
0110 
0111 static const struct vco_cntrl_value vco_cntrl_table[] = {
0112     { .min_freq = 40000000U,   .max_freq = 55000000U,   .value = 0x3f },
0113     { .min_freq = 52500000U,   .max_freq = 80000000U,   .value = 0x39 },
0114     { .min_freq = 80000000U,   .max_freq = 110000000U,  .value = 0x2f },
0115     { .min_freq = 105000000U,  .max_freq = 160000000U,  .value = 0x29 },
0116     { .min_freq = 160000000U,  .max_freq = 220000000U,  .value = 0x1f },
0117     { .min_freq = 210000000U,  .max_freq = 320000000U,  .value = 0x19 },
0118     { .min_freq = 320000000U,  .max_freq = 440000000U,  .value = 0x0f },
0119     { .min_freq = 420000000U,  .max_freq = 660000000U,  .value = 0x09 },
0120     { .min_freq = 630000000U,  .max_freq = 1149000000U, .value = 0x03 },
0121     { .min_freq = 1100000000U, .max_freq = 1152000000U, .value = 0x01 },
0122     { .min_freq = 1150000000U, .max_freq = 1250000000U, .value = 0x01 },
0123     { /* sentinel */ },
0124 };
0125 
0126 static void rcar_mipi_dsi_write(struct rcar_mipi_dsi *dsi, u32 reg, u32 data)
0127 {
0128     iowrite32(data, dsi->mmio + reg);
0129 }
0130 
0131 static u32 rcar_mipi_dsi_read(struct rcar_mipi_dsi *dsi, u32 reg)
0132 {
0133     return ioread32(dsi->mmio + reg);
0134 }
0135 
0136 static void rcar_mipi_dsi_clr(struct rcar_mipi_dsi *dsi, u32 reg, u32 clr)
0137 {
0138     rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) & ~clr);
0139 }
0140 
0141 static void rcar_mipi_dsi_set(struct rcar_mipi_dsi *dsi, u32 reg, u32 set)
0142 {
0143     rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) | set);
0144 }
0145 
0146 static int rcar_mipi_dsi_phtw_test(struct rcar_mipi_dsi *dsi, u32 phtw)
0147 {
0148     u32 status;
0149     int ret;
0150 
0151     rcar_mipi_dsi_write(dsi, PHTW, phtw);
0152 
0153     ret = read_poll_timeout(rcar_mipi_dsi_read, status,
0154                 !(status & (PHTW_DWEN | PHTW_CWEN)),
0155                 2000, 10000, false, dsi, PHTW);
0156     if (ret < 0) {
0157         dev_err(dsi->dev, "PHY test interface write timeout (0x%08x)\n",
0158             phtw);
0159         return ret;
0160     }
0161 
0162     return ret;
0163 }
0164 
0165 /* -----------------------------------------------------------------------------
0166  * Hardware Setup
0167  */
0168 
0169 struct dsi_setup_info {
0170     unsigned long fout;
0171     u16 vco_cntrl;
0172     u16 prop_cntrl;
0173     u16 hsfreqrange;
0174     u16 div;
0175     unsigned int m;
0176     unsigned int n;
0177 };
0178 
0179 static void rcar_mipi_dsi_parameters_calc(struct rcar_mipi_dsi *dsi,
0180                       struct clk *clk, unsigned long target,
0181                       struct dsi_setup_info *setup_info)
0182 {
0183 
0184     const struct vco_cntrl_value *vco_cntrl;
0185     unsigned long fout_target;
0186     unsigned long fin, fout;
0187     unsigned long hsfreq;
0188     unsigned int best_err = -1;
0189     unsigned int divider;
0190     unsigned int n;
0191     unsigned int i;
0192     unsigned int err;
0193 
0194     /*
0195      * Calculate Fout = dot clock * ColorDepth / (2 * Lane Count)
0196      * The range out Fout is [40 - 1250] Mhz
0197      */
0198     fout_target = target * mipi_dsi_pixel_format_to_bpp(dsi->format)
0199             / (2 * dsi->lanes);
0200     if (fout_target < 40000000 || fout_target > 1250000000)
0201         return;
0202 
0203     /* Find vco_cntrl */
0204     for (vco_cntrl = vco_cntrl_table; vco_cntrl->min_freq != 0; vco_cntrl++) {
0205         if (fout_target > vco_cntrl->min_freq &&
0206             fout_target <= vco_cntrl->max_freq) {
0207             setup_info->vco_cntrl = vco_cntrl->value;
0208             if (fout_target >= 1150000000)
0209                 setup_info->prop_cntrl = 0x0c;
0210             else
0211                 setup_info->prop_cntrl = 0x0b;
0212             break;
0213         }
0214     }
0215 
0216     /* Add divider */
0217     setup_info->div = (setup_info->vco_cntrl & 0x30) >> 4;
0218 
0219     /* Find hsfreqrange */
0220     hsfreq = fout_target * 2;
0221     for (i = 0; i < ARRAY_SIZE(hsfreqrange_table); i++) {
0222         if (hsfreqrange_table[i][0] >= hsfreq) {
0223             setup_info->hsfreqrange = hsfreqrange_table[i][1];
0224             break;
0225         }
0226     }
0227 
0228     /*
0229      * Calculate n and m for PLL clock
0230      * Following the HW manual the ranges of n and m are
0231      * n = [3-8] and m = [64-625]
0232      */
0233     fin = clk_get_rate(clk);
0234     divider = 1 << setup_info->div;
0235     for (n = 3; n < 9; n++) {
0236         unsigned long fpfd;
0237         unsigned int m;
0238 
0239         fpfd = fin / n;
0240 
0241         for (m = 64; m < 626; m++) {
0242             fout = fpfd * m / divider;
0243             err = abs((long)(fout - fout_target) * 10000 /
0244                   (long)fout_target);
0245             if (err < best_err) {
0246                 setup_info->m = m - 2;
0247                 setup_info->n = n - 1;
0248                 setup_info->fout = fout;
0249                 best_err = err;
0250                 if (err == 0)
0251                     goto done;
0252             }
0253         }
0254     }
0255 
0256 done:
0257     dev_dbg(dsi->dev,
0258         "%pC %lu Hz -> Fout %lu Hz (target %lu Hz, error %d.%02u%%), PLL M/N/DIV %u/%u/%u\n",
0259         clk, fin, setup_info->fout, fout_target, best_err / 100,
0260         best_err % 100, setup_info->m, setup_info->n, setup_info->div);
0261     dev_dbg(dsi->dev,
0262         "vco_cntrl = 0x%x\tprop_cntrl = 0x%x\thsfreqrange = 0x%x\n",
0263         setup_info->vco_cntrl, setup_info->prop_cntrl,
0264         setup_info->hsfreqrange);
0265 }
0266 
0267 static void rcar_mipi_dsi_set_display_timing(struct rcar_mipi_dsi *dsi,
0268                          const struct drm_display_mode *mode)
0269 {
0270     u32 setr;
0271     u32 vprmset0r;
0272     u32 vprmset1r;
0273     u32 vprmset2r;
0274     u32 vprmset3r;
0275     u32 vprmset4r;
0276 
0277     /* Configuration for Pixel Stream and Packet Header */
0278     if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 24)
0279         rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB24);
0280     else if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 18)
0281         rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB18);
0282     else if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 16)
0283         rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB16);
0284     else {
0285         dev_warn(dsi->dev, "unsupported format");
0286         return;
0287     }
0288 
0289     /* Configuration for Blanking sequence and Input Pixel */
0290     setr = TXVMSETR_HSABPEN_EN | TXVMSETR_HBPBPEN_EN
0291          | TXVMSETR_HFPBPEN_EN | TXVMSETR_SYNSEQ_PULSES
0292          | TXVMSETR_PIXWDTH | TXVMSETR_VSTPM;
0293     rcar_mipi_dsi_write(dsi, TXVMSETR, setr);
0294 
0295     /* Configuration for Video Parameters */
0296     vprmset0r = (mode->flags & DRM_MODE_FLAG_PVSYNC ?
0297              TXVMVPRMSET0R_VSPOL_HIG : TXVMVPRMSET0R_VSPOL_LOW)
0298           | (mode->flags & DRM_MODE_FLAG_PHSYNC ?
0299              TXVMVPRMSET0R_HSPOL_HIG : TXVMVPRMSET0R_HSPOL_LOW)
0300           | TXVMVPRMSET0R_CSPC_RGB | TXVMVPRMSET0R_BPP_24;
0301 
0302     vprmset1r = TXVMVPRMSET1R_VACTIVE(mode->vdisplay)
0303           | TXVMVPRMSET1R_VSA(mode->vsync_end - mode->vsync_start);
0304 
0305     vprmset2r = TXVMVPRMSET2R_VFP(mode->vsync_start - mode->vdisplay)
0306           | TXVMVPRMSET2R_VBP(mode->vtotal - mode->vsync_end);
0307 
0308     vprmset3r = TXVMVPRMSET3R_HACTIVE(mode->hdisplay)
0309           | TXVMVPRMSET3R_HSA(mode->hsync_end - mode->hsync_start);
0310 
0311     vprmset4r = TXVMVPRMSET4R_HFP(mode->hsync_start - mode->hdisplay)
0312           | TXVMVPRMSET4R_HBP(mode->htotal - mode->hsync_end);
0313 
0314     rcar_mipi_dsi_write(dsi, TXVMVPRMSET0R, vprmset0r);
0315     rcar_mipi_dsi_write(dsi, TXVMVPRMSET1R, vprmset1r);
0316     rcar_mipi_dsi_write(dsi, TXVMVPRMSET2R, vprmset2r);
0317     rcar_mipi_dsi_write(dsi, TXVMVPRMSET3R, vprmset3r);
0318     rcar_mipi_dsi_write(dsi, TXVMVPRMSET4R, vprmset4r);
0319 }
0320 
0321 static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *dsi,
0322                  const struct drm_display_mode *mode)
0323 {
0324     struct dsi_setup_info setup_info = {};
0325     unsigned int timeout;
0326     int ret, i;
0327     int dsi_format;
0328     u32 phy_setup;
0329     u32 clockset2, clockset3;
0330     u32 ppisetr;
0331     u32 vclkset;
0332 
0333     /* Checking valid format */
0334     dsi_format = mipi_dsi_pixel_format_to_bpp(dsi->format);
0335     if (dsi_format < 0) {
0336         dev_warn(dsi->dev, "invalid format");
0337         return -EINVAL;
0338     }
0339 
0340     /* Parameters Calculation */
0341     rcar_mipi_dsi_parameters_calc(dsi, dsi->clocks.pll,
0342                       mode->clock * 1000, &setup_info);
0343 
0344     /* LPCLK enable */
0345     rcar_mipi_dsi_set(dsi, LPCLKSET, LPCLKSET_CKEN);
0346 
0347     /* CFGCLK enabled */
0348     rcar_mipi_dsi_set(dsi, CFGCLKSET, CFGCLKSET_CKEN);
0349 
0350     rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_RSTZ);
0351     rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
0352 
0353     rcar_mipi_dsi_set(dsi, PHTC, PHTC_TESTCLR);
0354     rcar_mipi_dsi_clr(dsi, PHTC, PHTC_TESTCLR);
0355 
0356     /* PHY setting */
0357     phy_setup = rcar_mipi_dsi_read(dsi, PHYSETUP);
0358     phy_setup &= ~PHYSETUP_HSFREQRANGE_MASK;
0359     phy_setup |= PHYSETUP_HSFREQRANGE(setup_info.hsfreqrange);
0360     rcar_mipi_dsi_write(dsi, PHYSETUP, phy_setup);
0361 
0362     for (i = 0; i < ARRAY_SIZE(phtw); i++) {
0363         ret = rcar_mipi_dsi_phtw_test(dsi, phtw[i]);
0364         if (ret < 0)
0365             return ret;
0366     }
0367 
0368     /* PLL Clock Setting */
0369     rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
0370     rcar_mipi_dsi_set(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
0371     rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
0372 
0373     clockset2 = CLOCKSET2_M(setup_info.m) | CLOCKSET2_N(setup_info.n)
0374           | CLOCKSET2_VCO_CNTRL(setup_info.vco_cntrl);
0375     clockset3 = CLOCKSET3_PROP_CNTRL(setup_info.prop_cntrl)
0376           | CLOCKSET3_INT_CNTRL(0)
0377           | CLOCKSET3_CPBIAS_CNTRL(0x10)
0378           | CLOCKSET3_GMP_CNTRL(1);
0379     rcar_mipi_dsi_write(dsi, CLOCKSET2, clockset2);
0380     rcar_mipi_dsi_write(dsi, CLOCKSET3, clockset3);
0381 
0382     rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
0383     rcar_mipi_dsi_set(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
0384     udelay(10);
0385     rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
0386 
0387     ppisetr = PPISETR_DLEN_3 | PPISETR_CLEN;
0388     rcar_mipi_dsi_write(dsi, PPISETR, ppisetr);
0389 
0390     rcar_mipi_dsi_set(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
0391     rcar_mipi_dsi_set(dsi, PHYSETUP, PHYSETUP_RSTZ);
0392     usleep_range(400, 500);
0393 
0394     /* Checking PPI clock status register */
0395     for (timeout = 10; timeout > 0; --timeout) {
0396         if ((rcar_mipi_dsi_read(dsi, PPICLSR) & PPICLSR_STPST) &&
0397             (rcar_mipi_dsi_read(dsi, PPIDLSR) & PPIDLSR_STPST) &&
0398             (rcar_mipi_dsi_read(dsi, CLOCKSET1) & CLOCKSET1_LOCK))
0399             break;
0400 
0401         usleep_range(1000, 2000);
0402     }
0403 
0404     if (!timeout) {
0405         dev_err(dsi->dev, "failed to enable PPI clock\n");
0406         return -ETIMEDOUT;
0407     }
0408 
0409     for (i = 0; i < ARRAY_SIZE(phtw2); i++) {
0410         ret = rcar_mipi_dsi_phtw_test(dsi, phtw2[i]);
0411         if (ret < 0)
0412             return ret;
0413     }
0414 
0415     /* Enable DOT clock */
0416     vclkset = VCLKSET_CKEN;
0417     rcar_mipi_dsi_set(dsi, VCLKSET, vclkset);
0418 
0419     if (dsi_format == 24)
0420         vclkset |= VCLKSET_BPP_24;
0421     else if (dsi_format == 18)
0422         vclkset |= VCLKSET_BPP_18;
0423     else if (dsi_format == 16)
0424         vclkset |= VCLKSET_BPP_16;
0425     else {
0426         dev_warn(dsi->dev, "unsupported format");
0427         return -EINVAL;
0428     }
0429     vclkset |= VCLKSET_COLOR_RGB | VCLKSET_DIV(setup_info.div)
0430         |  VCLKSET_LANE(dsi->lanes - 1);
0431 
0432     rcar_mipi_dsi_set(dsi, VCLKSET, vclkset);
0433 
0434     /* After setting VCLKSET register, enable VCLKEN */
0435     rcar_mipi_dsi_set(dsi, VCLKEN, VCLKEN_CKEN);
0436 
0437     dev_dbg(dsi->dev, "DSI device is started\n");
0438 
0439     return 0;
0440 }
0441 
0442 static void rcar_mipi_dsi_shutdown(struct rcar_mipi_dsi *dsi)
0443 {
0444     rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_RSTZ);
0445     rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
0446 
0447     dev_dbg(dsi->dev, "DSI device is shutdown\n");
0448 }
0449 
0450 static int rcar_mipi_dsi_clk_enable(struct rcar_mipi_dsi *dsi)
0451 {
0452     int ret;
0453 
0454     reset_control_deassert(dsi->rstc);
0455 
0456     ret = clk_prepare_enable(dsi->clocks.mod);
0457     if (ret < 0)
0458         goto err_reset;
0459 
0460     ret = clk_prepare_enable(dsi->clocks.dsi);
0461     if (ret < 0)
0462         goto err_clock;
0463 
0464     return 0;
0465 
0466 err_clock:
0467     clk_disable_unprepare(dsi->clocks.mod);
0468 err_reset:
0469     reset_control_assert(dsi->rstc);
0470     return ret;
0471 }
0472 
0473 static void rcar_mipi_dsi_clk_disable(struct rcar_mipi_dsi *dsi)
0474 {
0475     clk_disable_unprepare(dsi->clocks.dsi);
0476     clk_disable_unprepare(dsi->clocks.mod);
0477 
0478     reset_control_assert(dsi->rstc);
0479 }
0480 
0481 static int rcar_mipi_dsi_start_hs_clock(struct rcar_mipi_dsi *dsi)
0482 {
0483     /*
0484      * In HW manual, we need to check TxDDRClkHS-Q Stable? but it dont
0485      * write how to check. So we skip this check in this patch
0486      */
0487     u32 status;
0488     int ret;
0489 
0490     /* Start HS clock. */
0491     rcar_mipi_dsi_set(dsi, PPICLCR, PPICLCR_TXREQHS);
0492 
0493     ret = read_poll_timeout(rcar_mipi_dsi_read, status,
0494                 status & PPICLSR_TOHS,
0495                 2000, 10000, false, dsi, PPICLSR);
0496     if (ret < 0) {
0497         dev_err(dsi->dev, "failed to enable HS clock\n");
0498         return ret;
0499     }
0500 
0501     rcar_mipi_dsi_set(dsi, PPICLSCR, PPICLSCR_TOHS);
0502 
0503     return 0;
0504 }
0505 
0506 static int rcar_mipi_dsi_start_video(struct rcar_mipi_dsi *dsi)
0507 {
0508     u32 status;
0509     int ret;
0510 
0511     /* Wait for the link to be ready. */
0512     ret = read_poll_timeout(rcar_mipi_dsi_read, status,
0513                 !(status & (LINKSR_LPBUSY | LINKSR_HSBUSY)),
0514                 2000, 10000, false, dsi, LINKSR);
0515     if (ret < 0) {
0516         dev_err(dsi->dev, "Link failed to become ready\n");
0517         return ret;
0518     }
0519 
0520     /* De-assert video FIFO clear. */
0521     rcar_mipi_dsi_clr(dsi, TXVMCR, TXVMCR_VFCLR);
0522 
0523     ret = read_poll_timeout(rcar_mipi_dsi_read, status,
0524                 status & TXVMSR_VFRDY,
0525                 2000, 10000, false, dsi, TXVMSR);
0526     if (ret < 0) {
0527         dev_err(dsi->dev, "Failed to de-assert video FIFO clear\n");
0528         return ret;
0529     }
0530 
0531     /* Enable transmission in video mode. */
0532     rcar_mipi_dsi_set(dsi, TXVMCR, TXVMCR_EN_VIDEO);
0533 
0534     ret = read_poll_timeout(rcar_mipi_dsi_read, status,
0535                 status & TXVMSR_RDY,
0536                 2000, 10000, false, dsi, TXVMSR);
0537     if (ret < 0) {
0538         dev_err(dsi->dev, "Failed to enable video transmission\n");
0539         return ret;
0540     }
0541 
0542     return 0;
0543 }
0544 
0545 /* -----------------------------------------------------------------------------
0546  * Bridge
0547  */
0548 
0549 static int rcar_mipi_dsi_attach(struct drm_bridge *bridge,
0550                 enum drm_bridge_attach_flags flags)
0551 {
0552     struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
0553 
0554     return drm_bridge_attach(bridge->encoder, dsi->next_bridge, bridge,
0555                  flags);
0556 }
0557 
0558 static void rcar_mipi_dsi_atomic_enable(struct drm_bridge *bridge,
0559                     struct drm_bridge_state *old_bridge_state)
0560 {
0561     struct drm_atomic_state *state = old_bridge_state->base.state;
0562     struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
0563     const struct drm_display_mode *mode;
0564     struct drm_connector *connector;
0565     struct drm_crtc *crtc;
0566     int ret;
0567 
0568     connector = drm_atomic_get_new_connector_for_encoder(state,
0569                                  bridge->encoder);
0570     crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
0571     mode = &drm_atomic_get_new_crtc_state(state, crtc)->adjusted_mode;
0572 
0573     ret = rcar_mipi_dsi_clk_enable(dsi);
0574     if (ret < 0) {
0575         dev_err(dsi->dev, "failed to enable DSI clocks\n");
0576         return;
0577     }
0578 
0579     ret = rcar_mipi_dsi_startup(dsi, mode);
0580     if (ret < 0)
0581         goto err_dsi_startup;
0582 
0583     rcar_mipi_dsi_set_display_timing(dsi, mode);
0584 
0585     ret = rcar_mipi_dsi_start_hs_clock(dsi);
0586     if (ret < 0)
0587         goto err_dsi_start_hs;
0588 
0589     rcar_mipi_dsi_start_video(dsi);
0590 
0591     return;
0592 
0593 err_dsi_start_hs:
0594     rcar_mipi_dsi_shutdown(dsi);
0595 err_dsi_startup:
0596     rcar_mipi_dsi_clk_disable(dsi);
0597 }
0598 
0599 static void rcar_mipi_dsi_atomic_disable(struct drm_bridge *bridge,
0600                      struct drm_bridge_state *old_bridge_state)
0601 {
0602     struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
0603 
0604     rcar_mipi_dsi_shutdown(dsi);
0605     rcar_mipi_dsi_clk_disable(dsi);
0606 }
0607 
0608 static enum drm_mode_status
0609 rcar_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
0610                 const struct drm_display_info *info,
0611                 const struct drm_display_mode *mode)
0612 {
0613     if (mode->clock > 297000)
0614         return MODE_CLOCK_HIGH;
0615 
0616     return MODE_OK;
0617 }
0618 
0619 static const struct drm_bridge_funcs rcar_mipi_dsi_bridge_ops = {
0620     .attach = rcar_mipi_dsi_attach,
0621     .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
0622     .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
0623     .atomic_reset = drm_atomic_helper_bridge_reset,
0624     .atomic_enable = rcar_mipi_dsi_atomic_enable,
0625     .atomic_disable = rcar_mipi_dsi_atomic_disable,
0626     .mode_valid = rcar_mipi_dsi_bridge_mode_valid,
0627 };
0628 
0629 /* -----------------------------------------------------------------------------
0630  * Host setting
0631  */
0632 
0633 static int rcar_mipi_dsi_host_attach(struct mipi_dsi_host *host,
0634                      struct mipi_dsi_device *device)
0635 {
0636     struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host);
0637     int ret;
0638 
0639     if (device->lanes > dsi->num_data_lanes)
0640         return -EINVAL;
0641 
0642     dsi->lanes = device->lanes;
0643     dsi->format = device->format;
0644 
0645     dsi->next_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node,
0646                           1, 0);
0647     if (IS_ERR(dsi->next_bridge)) {
0648         ret = PTR_ERR(dsi->next_bridge);
0649         dev_err(dsi->dev, "failed to get next bridge: %d\n", ret);
0650         return ret;
0651     }
0652 
0653     /* Initialize the DRM bridge. */
0654     dsi->bridge.funcs = &rcar_mipi_dsi_bridge_ops;
0655     dsi->bridge.of_node = dsi->dev->of_node;
0656     drm_bridge_add(&dsi->bridge);
0657 
0658     return 0;
0659 }
0660 
0661 static int rcar_mipi_dsi_host_detach(struct mipi_dsi_host *host,
0662                     struct mipi_dsi_device *device)
0663 {
0664     struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host);
0665 
0666     drm_bridge_remove(&dsi->bridge);
0667 
0668     return 0;
0669 }
0670 
0671 static const struct mipi_dsi_host_ops rcar_mipi_dsi_host_ops = {
0672     .attach = rcar_mipi_dsi_host_attach,
0673     .detach = rcar_mipi_dsi_host_detach,
0674 };
0675 
0676 /* -----------------------------------------------------------------------------
0677  * Probe & Remove
0678  */
0679 
0680 static int rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi *dsi)
0681 {
0682     int ret;
0683 
0684     ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4);
0685     if (ret < 0) {
0686         dev_err(dsi->dev, "missing or invalid data-lanes property\n");
0687         return ret;
0688     }
0689 
0690     dsi->num_data_lanes = ret;
0691     return 0;
0692 }
0693 
0694 static struct clk *rcar_mipi_dsi_get_clock(struct rcar_mipi_dsi *dsi,
0695                        const char *name,
0696                        bool optional)
0697 {
0698     struct clk *clk;
0699 
0700     clk = devm_clk_get(dsi->dev, name);
0701     if (!IS_ERR(clk))
0702         return clk;
0703 
0704     if (PTR_ERR(clk) == -ENOENT && optional)
0705         return NULL;
0706 
0707     dev_err_probe(dsi->dev, PTR_ERR(clk), "failed to get %s clock\n",
0708               name ? name : "module");
0709 
0710     return clk;
0711 }
0712 
0713 static int rcar_mipi_dsi_get_clocks(struct rcar_mipi_dsi *dsi)
0714 {
0715     dsi->clocks.mod = rcar_mipi_dsi_get_clock(dsi, NULL, false);
0716     if (IS_ERR(dsi->clocks.mod))
0717         return PTR_ERR(dsi->clocks.mod);
0718 
0719     dsi->clocks.pll = rcar_mipi_dsi_get_clock(dsi, "pll", true);
0720     if (IS_ERR(dsi->clocks.pll))
0721         return PTR_ERR(dsi->clocks.pll);
0722 
0723     dsi->clocks.dsi = rcar_mipi_dsi_get_clock(dsi, "dsi", true);
0724     if (IS_ERR(dsi->clocks.dsi))
0725         return PTR_ERR(dsi->clocks.dsi);
0726 
0727     if (!dsi->clocks.pll && !dsi->clocks.dsi) {
0728         dev_err(dsi->dev, "no input clock (pll, dsi)\n");
0729         return -EINVAL;
0730     }
0731 
0732     return 0;
0733 }
0734 
0735 static int rcar_mipi_dsi_probe(struct platform_device *pdev)
0736 {
0737     struct rcar_mipi_dsi *dsi;
0738     struct resource *mem;
0739     int ret;
0740 
0741     dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
0742     if (dsi == NULL)
0743         return -ENOMEM;
0744 
0745     platform_set_drvdata(pdev, dsi);
0746 
0747     dsi->dev = &pdev->dev;
0748     dsi->info = of_device_get_match_data(&pdev->dev);
0749 
0750     ret = rcar_mipi_dsi_parse_dt(dsi);
0751     if (ret < 0)
0752         return ret;
0753 
0754     /* Acquire resources. */
0755     mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0756     dsi->mmio = devm_ioremap_resource(dsi->dev, mem);
0757     if (IS_ERR(dsi->mmio))
0758         return PTR_ERR(dsi->mmio);
0759 
0760     ret = rcar_mipi_dsi_get_clocks(dsi);
0761     if (ret < 0)
0762         return ret;
0763 
0764     dsi->rstc = devm_reset_control_get(dsi->dev, NULL);
0765     if (IS_ERR(dsi->rstc)) {
0766         dev_err(dsi->dev, "failed to get cpg reset\n");
0767         return PTR_ERR(dsi->rstc);
0768     }
0769 
0770     /* Initialize the DSI host. */
0771     dsi->host.dev = dsi->dev;
0772     dsi->host.ops = &rcar_mipi_dsi_host_ops;
0773     ret = mipi_dsi_host_register(&dsi->host);
0774     if (ret < 0)
0775         return ret;
0776 
0777     return 0;
0778 }
0779 
0780 static int rcar_mipi_dsi_remove(struct platform_device *pdev)
0781 {
0782     struct rcar_mipi_dsi *dsi = platform_get_drvdata(pdev);
0783 
0784     mipi_dsi_host_unregister(&dsi->host);
0785 
0786     return 0;
0787 }
0788 
0789 static const struct of_device_id rcar_mipi_dsi_of_table[] = {
0790     { .compatible = "renesas,r8a779a0-dsi-csi2-tx" },
0791     { }
0792 };
0793 
0794 MODULE_DEVICE_TABLE(of, rcar_mipi_dsi_of_table);
0795 
0796 static struct platform_driver rcar_mipi_dsi_platform_driver = {
0797     .probe          = rcar_mipi_dsi_probe,
0798     .remove         = rcar_mipi_dsi_remove,
0799     .driver         = {
0800         .name   = "rcar-mipi-dsi",
0801         .of_match_table = rcar_mipi_dsi_of_table,
0802     },
0803 };
0804 
0805 module_platform_driver(rcar_mipi_dsi_platform_driver);
0806 
0807 MODULE_DESCRIPTION("Renesas R-Car MIPI DSI Encoder Driver");
0808 MODULE_LICENSE("GPL");
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