drm/radeon/vce_v2_0.c

0001 /*
0002  * Copyright 2013 Advanced Micro Devices, Inc.
0003  * All Rights Reserved.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the
0007  * "Software"), to deal in the Software without restriction, including
0008  * without limitation the rights to use, copy, modify, merge, publish,
0009  * distribute, sub license, and/or sell copies of the Software, and to
0010  * permit persons to whom the Software is furnished to do so, subject to
0011  * the following conditions:
0012  *
0013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0014  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
0017  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
0018  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
0019  * USE OR OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * The above copyright notice and this permission notice (including the
0022  * next paragraph) shall be included in all copies or substantial portions
0023  * of the Software.
0024  *
0025  * Authors: Christian König <christian.koenig@amd.com>
0026  */
0027
0028 #include <linux/firmware.h>
0029
0030 #include "radeon.h"
0031 #include "radeon_asic.h"
0032 #include "cikd.h"
0033 #include "vce.h"
0034
0035 #define VCE_V2_0_FW_SIZE    (256 * 1024)
0036 #define VCE_V2_0_STACK_SIZE (64 * 1024)
0037 #define VCE_V2_0_DATA_SIZE  (23552 * RADEON_MAX_VCE_HANDLES)
0038
0039 static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated)
0040 {
0041     u32 tmp;
0042
0043     if (gated) {
0044         tmp = RREG32(VCE_CLOCK_GATING_B);
0045         tmp |= 0xe70000;
0046         WREG32(VCE_CLOCK_GATING_B, tmp);
0047
0048         tmp = RREG32(VCE_UENC_CLOCK_GATING);
0049         tmp |= 0xff000000;
0050         WREG32(VCE_UENC_CLOCK_GATING, tmp);
0051
0052         tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
0053         tmp &= ~0x3fc;
0054         WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
0055
0056         WREG32(VCE_CGTT_CLK_OVERRIDE, 0);
0057     } else {
0058         tmp = RREG32(VCE_CLOCK_GATING_B);
0059         tmp |= 0xe7;
0060         tmp &= ~0xe70000;
0061         WREG32(VCE_CLOCK_GATING_B, tmp);
0062
0063         tmp = RREG32(VCE_UENC_CLOCK_GATING);
0064         tmp |= 0x1fe000;
0065         tmp &= ~0xff000000;
0066         WREG32(VCE_UENC_CLOCK_GATING, tmp);
0067
0068         tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
0069         tmp |= 0x3fc;
0070         WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
0071     }
0072 }
0073
0074 static void vce_v2_0_set_dyn_cg(struct radeon_device *rdev, bool gated)
0075 {
0076     u32 orig, tmp;
0077
0078     tmp = RREG32(VCE_CLOCK_GATING_B);
0079     tmp &= ~0x00060006;
0080     if (gated) {
0081         tmp |= 0xe10000;
0082     } else {
0083         tmp |= 0xe1;
0084         tmp &= ~0xe10000;
0085     }
0086     WREG32(VCE_CLOCK_GATING_B, tmp);
0087
0088     orig = tmp = RREG32(VCE_UENC_CLOCK_GATING);
0089     tmp &= ~0x1fe000;
0090     tmp &= ~0xff000000;
0091     if (tmp != orig)
0092         WREG32(VCE_UENC_CLOCK_GATING, tmp);
0093
0094     orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
0095     tmp &= ~0x3fc;
0096     if (tmp != orig)
0097         WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
0098
0099     if (gated)
0100         WREG32(VCE_CGTT_CLK_OVERRIDE, 0);
0101 }
0102
0103 static void vce_v2_0_disable_cg(struct radeon_device *rdev)
0104 {
0105     WREG32(VCE_CGTT_CLK_OVERRIDE, 7);
0106 }
0107
0108 /*
0109  * Local variable sw_cg is used for debugging purposes, in case we
0110  * ran into problems with dynamic clock gating. Don't remove it.
0111  */
0112 void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable)
0113 {
0114     bool sw_cg = false;
0115
0116     if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_VCE_MGCG)) {
0117         if (sw_cg)
0118             vce_v2_0_set_sw_cg(rdev, true);
0119         else
0120             vce_v2_0_set_dyn_cg(rdev, true);
0121     } else {
0122         vce_v2_0_disable_cg(rdev);
0123
0124         if (sw_cg)
0125             vce_v2_0_set_sw_cg(rdev, false);
0126         else
0127             vce_v2_0_set_dyn_cg(rdev, false);
0128     }
0129 }
0130
0131 static void vce_v2_0_init_cg(struct radeon_device *rdev)
0132 {
0133     u32 tmp;
0134
0135     tmp = RREG32(VCE_CLOCK_GATING_A);
0136     tmp &= ~(CGC_CLK_GATE_DLY_TIMER_MASK | CGC_CLK_GATER_OFF_DLY_TIMER_MASK);
0137     tmp |= (CGC_CLK_GATE_DLY_TIMER(0) | CGC_CLK_GATER_OFF_DLY_TIMER(4));
0138     tmp |= CGC_UENC_WAIT_AWAKE;
0139     WREG32(VCE_CLOCK_GATING_A, tmp);
0140
0141     tmp = RREG32(VCE_UENC_CLOCK_GATING);
0142     tmp &= ~(CLOCK_ON_DELAY_MASK | CLOCK_OFF_DELAY_MASK);
0143     tmp |= (CLOCK_ON_DELAY(0) | CLOCK_OFF_DELAY(4));
0144     WREG32(VCE_UENC_CLOCK_GATING, tmp);
0145
0146     tmp = RREG32(VCE_CLOCK_GATING_B);
0147     tmp |= 0x10;
0148     tmp &= ~0x100000;
0149     WREG32(VCE_CLOCK_GATING_B, tmp);
0150 }
0151
0152 unsigned vce_v2_0_bo_size(struct radeon_device *rdev)
0153 {
0154     WARN_ON(rdev->vce_fw->size > VCE_V2_0_FW_SIZE);
0155     return VCE_V2_0_FW_SIZE + VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE;
0156 }
0157
0158 int vce_v2_0_resume(struct radeon_device *rdev)
0159 {
0160     uint64_t addr = rdev->vce.gpu_addr;
0161     uint32_t size;
0162
0163     WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16));
0164     WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
0165     WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
0166     WREG32(VCE_CLOCK_GATING_B, 0xf7);
0167
0168     WREG32(VCE_LMI_CTRL, 0x00398000);
0169     WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1);
0170     WREG32(VCE_LMI_SWAP_CNTL, 0);
0171     WREG32(VCE_LMI_SWAP_CNTL1, 0);
0172     WREG32(VCE_LMI_VM_CTRL, 0);
0173
0174     WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8);
0175
0176     addr &= 0xff;
0177     size = VCE_V2_0_FW_SIZE;
0178     WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
0179     WREG32(VCE_VCPU_CACHE_SIZE0, size);
0180
0181     addr += size;
0182     size = VCE_V2_0_STACK_SIZE;
0183     WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
0184     WREG32(VCE_VCPU_CACHE_SIZE1, size);
0185
0186     addr += size;
0187     size = VCE_V2_0_DATA_SIZE;
0188     WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
0189     WREG32(VCE_VCPU_CACHE_SIZE2, size);
0190
0191     WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100);
0192
0193     WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN,
0194          ~VCE_SYS_INT_TRAP_INTERRUPT_EN);
0195
0196     vce_v2_0_init_cg(rdev);
0197
0198     return 0;
0199 }