drm/radeon/vce_v1_0.c

0001 /*
0002  * Copyright 2013 Advanced Micro Devices, Inc.
0003  * All Rights Reserved.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the
0007  * "Software"), to deal in the Software without restriction, including
0008  * without limitation the rights to use, copy, modify, merge, publish,
0009  * distribute, sub license, and/or sell copies of the Software, and to
0010  * permit persons to whom the Software is furnished to do so, subject to
0011  * the following conditions:
0012  *
0013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0014  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
0017  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
0018  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
0019  * USE OR OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * The above copyright notice and this permission notice (including the
0022  * next paragraph) shall be included in all copies or substantial portions
0023  * of the Software.
0024  *
0025  * Authors: Christian König <christian.koenig@amd.com>
0026  */
0027
0028 #include <linux/firmware.h>
0029
0030 #include "radeon.h"
0031 #include "radeon_asic.h"
0032 #include "sid.h"
0033 #include "vce.h"
0034
0035 #define VCE_V1_0_FW_SIZE    (256 * 1024)
0036 #define VCE_V1_0_STACK_SIZE (64 * 1024)
0037 #define VCE_V1_0_DATA_SIZE  (7808 * (RADEON_MAX_VCE_HANDLES + 1))
0038
0039 struct vce_v1_0_fw_signature
0040 {
0041     int32_t off;
0042     uint32_t len;
0043     int32_t num;
0044     struct {
0045         uint32_t chip_id;
0046         uint32_t keyselect;
0047         uint32_t nonce[4];
0048         uint32_t sigval[4];
0049     } val[8];
0050 };
0051
0052 /**
0053  * vce_v1_0_get_rptr - get read pointer
0054  *
0055  * @rdev: radeon_device pointer
0056  * @ring: radeon_ring pointer
0057  *
0058  * Returns the current hardware read pointer
0059  */
0060 uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,
0061                struct radeon_ring *ring)
0062 {
0063     if (ring->idx == TN_RING_TYPE_VCE1_INDEX)
0064         return RREG32(VCE_RB_RPTR);
0065     else
0066         return RREG32(VCE_RB_RPTR2);
0067 }
0068
0069 /**
0070  * vce_v1_0_get_wptr - get write pointer
0071  *
0072  * @rdev: radeon_device pointer
0073  * @ring: radeon_ring pointer
0074  *
0075  * Returns the current hardware write pointer
0076  */
0077 uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
0078                struct radeon_ring *ring)
0079 {
0080     if (ring->idx == TN_RING_TYPE_VCE1_INDEX)
0081         return RREG32(VCE_RB_WPTR);
0082     else
0083         return RREG32(VCE_RB_WPTR2);
0084 }
0085
0086 /**
0087  * vce_v1_0_set_wptr - set write pointer
0088  *
0089  * @rdev: radeon_device pointer
0090  * @ring: radeon_ring pointer
0091  *
0092  * Commits the write pointer to the hardware
0093  */
0094 void vce_v1_0_set_wptr(struct radeon_device *rdev,
0095                struct radeon_ring *ring)
0096 {
0097     if (ring->idx == TN_RING_TYPE_VCE1_INDEX)
0098         WREG32(VCE_RB_WPTR, ring->wptr);
0099     else
0100         WREG32(VCE_RB_WPTR2, ring->wptr);
0101 }
0102
0103 void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable)
0104 {
0105     u32 tmp;
0106
0107     if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_VCE_MGCG)) {
0108         tmp = RREG32(VCE_CLOCK_GATING_A);
0109         tmp |= CGC_DYN_CLOCK_MODE;
0110         WREG32(VCE_CLOCK_GATING_A, tmp);
0111
0112         tmp = RREG32(VCE_UENC_CLOCK_GATING);
0113         tmp &= ~0x1ff000;
0114         tmp |= 0xff800000;
0115         WREG32(VCE_UENC_CLOCK_GATING, tmp);
0116
0117         tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
0118         tmp &= ~0x3ff;
0119         WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
0120     } else {
0121         tmp = RREG32(VCE_CLOCK_GATING_A);
0122         tmp &= ~CGC_DYN_CLOCK_MODE;
0123         WREG32(VCE_CLOCK_GATING_A, tmp);
0124
0125         tmp = RREG32(VCE_UENC_CLOCK_GATING);
0126         tmp |= 0x1ff000;
0127         tmp &= ~0xff800000;
0128         WREG32(VCE_UENC_CLOCK_GATING, tmp);
0129
0130         tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
0131         tmp |= 0x3ff;
0132         WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
0133     }
0134 }
0135
0136 static void vce_v1_0_init_cg(struct radeon_device *rdev)
0137 {
0138     u32 tmp;
0139
0140     tmp = RREG32(VCE_CLOCK_GATING_A);
0141     tmp |= CGC_DYN_CLOCK_MODE;
0142     WREG32(VCE_CLOCK_GATING_A, tmp);
0143
0144     tmp = RREG32(VCE_CLOCK_GATING_B);
0145     tmp |= 0x1e;
0146     tmp &= ~0xe100e1;
0147     WREG32(VCE_CLOCK_GATING_B, tmp);
0148
0149     tmp = RREG32(VCE_UENC_CLOCK_GATING);
0150     tmp &= ~0xff9ff000;
0151     WREG32(VCE_UENC_CLOCK_GATING, tmp);
0152
0153     tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
0154     tmp &= ~0x3ff;
0155     WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
0156 }
0157
0158 int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data)
0159 {
0160     struct vce_v1_0_fw_signature *sign = (void*)rdev->vce_fw->data;
0161     uint32_t chip_id;
0162     int i;
0163
0164     switch (rdev->family) {
0165     case CHIP_TAHITI:
0166         chip_id = 0x01000014;
0167         break;
0168     case CHIP_VERDE:
0169         chip_id = 0x01000015;
0170         break;
0171     case CHIP_PITCAIRN:
0172         chip_id = 0x01000016;
0173         break;
0174     case CHIP_ARUBA:
0175         chip_id = 0x01000017;
0176         break;
0177     default:
0178         return -EINVAL;
0179     }
0180
0181     for (i = 0; i < le32_to_cpu(sign->num); ++i) {
0182         if (le32_to_cpu(sign->val[i].chip_id) == chip_id)
0183             break;
0184     }
0185
0186     if (i == le32_to_cpu(sign->num))
0187         return -EINVAL;
0188
0189     data += (256 - 64) / 4;
0190     data[0] = sign->val[i].nonce[0];
0191     data[1] = sign->val[i].nonce[1];
0192     data[2] = sign->val[i].nonce[2];
0193     data[3] = sign->val[i].nonce[3];
0194     data[4] = cpu_to_le32(le32_to_cpu(sign->len) + 64);
0195
0196     memset(&data[5], 0, 44);
0197     memcpy(&data[16], &sign[1], rdev->vce_fw->size - sizeof(*sign));
0198
0199     data += (le32_to_cpu(sign->len) + 64) / 4;
0200     data[0] = sign->val[i].sigval[0];
0201     data[1] = sign->val[i].sigval[1];
0202     data[2] = sign->val[i].sigval[2];
0203     data[3] = sign->val[i].sigval[3];
0204
0205     rdev->vce.keyselect = le32_to_cpu(sign->val[i].keyselect);
0206
0207     return 0;
0208 }
0209
0210 unsigned vce_v1_0_bo_size(struct radeon_device *rdev)
0211 {
0212     WARN_ON(VCE_V1_0_FW_SIZE < rdev->vce_fw->size);
0213     return VCE_V1_0_FW_SIZE + VCE_V1_0_STACK_SIZE + VCE_V1_0_DATA_SIZE;
0214 }
0215
0216 int vce_v1_0_resume(struct radeon_device *rdev)
0217 {
0218     uint64_t addr = rdev->vce.gpu_addr;
0219     uint32_t size;
0220     int i;
0221
0222     WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16));
0223     WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
0224     WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
0225     WREG32(VCE_CLOCK_GATING_B, 0);
0226
0227     WREG32_P(VCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4);
0228
0229     WREG32(VCE_LMI_CTRL, 0x00398000);
0230     WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1);
0231     WREG32(VCE_LMI_SWAP_CNTL, 0);
0232     WREG32(VCE_LMI_SWAP_CNTL1, 0);
0233     WREG32(VCE_LMI_VM_CTRL, 0);
0234
0235     WREG32(VCE_VCPU_SCRATCH7, RADEON_MAX_VCE_HANDLES);
0236
0237     addr += 256;
0238     size = VCE_V1_0_FW_SIZE;
0239     WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
0240     WREG32(VCE_VCPU_CACHE_SIZE0, size);
0241
0242     addr += size;
0243     size = VCE_V1_0_STACK_SIZE;
0244     WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
0245     WREG32(VCE_VCPU_CACHE_SIZE1, size);
0246
0247     addr += size;
0248     size = VCE_V1_0_DATA_SIZE;
0249     WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
0250     WREG32(VCE_VCPU_CACHE_SIZE2, size);
0251
0252     WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100);
0253
0254     WREG32(VCE_LMI_FW_START_KEYSEL, rdev->vce.keyselect);
0255
0256     for (i = 0; i < 10; ++i) {
0257         mdelay(10);
0258         if (RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_DONE)
0259             break;
0260     }
0261
0262     if (i == 10)
0263         return -ETIMEDOUT;
0264
0265     if (!(RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_PASS))
0266         return -EINVAL;
0267
0268     for (i = 0; i < 10; ++i) {
0269         mdelay(10);
0270         if (!(RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_BUSY))
0271             break;
0272     }
0273
0274     if (i == 10)
0275         return -ETIMEDOUT;
0276
0277     vce_v1_0_init_cg(rdev);
0278
0279     return 0;
0280 }
0281
0282 /**
0283  * vce_v1_0_start - start VCE block
0284  *
0285  * @rdev: radeon_device pointer
0286  *
0287  * Setup and start the VCE block
0288  */
0289 int vce_v1_0_start(struct radeon_device *rdev)
0290 {
0291     struct radeon_ring *ring;
0292     int i, j, r;
0293
0294     /* set BUSY flag */
0295     WREG32_P(VCE_STATUS, 1, ~1);
0296
0297     ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
0298     WREG32(VCE_RB_RPTR, ring->wptr);
0299     WREG32(VCE_RB_WPTR, ring->wptr);
0300     WREG32(VCE_RB_BASE_LO, ring->gpu_addr);
0301     WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
0302     WREG32(VCE_RB_SIZE, ring->ring_size / 4);
0303
0304     ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
0305     WREG32(VCE_RB_RPTR2, ring->wptr);
0306     WREG32(VCE_RB_WPTR2, ring->wptr);
0307     WREG32(VCE_RB_BASE_LO2, ring->gpu_addr);
0308     WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
0309     WREG32(VCE_RB_SIZE2, ring->ring_size / 4);
0310
0311     WREG32_P(VCE_VCPU_CNTL, VCE_CLK_EN, ~VCE_CLK_EN);
0312
0313     WREG32_P(VCE_SOFT_RESET,
0314          VCE_ECPU_SOFT_RESET |
0315          VCE_FME_SOFT_RESET, ~(
0316          VCE_ECPU_SOFT_RESET |
0317          VCE_FME_SOFT_RESET));
0318
0319     mdelay(100);
0320
0321     WREG32_P(VCE_SOFT_RESET, 0, ~(
0322          VCE_ECPU_SOFT_RESET |
0323          VCE_FME_SOFT_RESET));
0324
0325     for (i = 0; i < 10; ++i) {
0326         uint32_t status;
0327         for (j = 0; j < 100; ++j) {
0328             status = RREG32(VCE_STATUS);
0329             if (status & 2)
0330                 break;
0331             mdelay(10);
0332         }
0333         r = 0;
0334         if (status & 2)
0335             break;
0336
0337         DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
0338         WREG32_P(VCE_SOFT_RESET, VCE_ECPU_SOFT_RESET, ~VCE_ECPU_SOFT_RESET);
0339         mdelay(10);
0340         WREG32_P(VCE_SOFT_RESET, 0, ~VCE_ECPU_SOFT_RESET);
0341         mdelay(10);
0342         r = -1;
0343     }
0344
0345     /* clear BUSY flag */
0346     WREG32_P(VCE_STATUS, 0, ~1);
0347
0348     if (r) {
0349         DRM_ERROR("VCE not responding, giving up!!!\n");
0350         return r;
0351     }
0352
0353     return 0;
0354 }
0355
0356 int vce_v1_0_init(struct radeon_device *rdev)
0357 {
0358     struct radeon_ring *ring;
0359     int r;
0360
0361     r = vce_v1_0_start(rdev);
0362     if (r)
0363         return r;
0364
0365     ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
0366     ring->ready = true;
0367     r = radeon_ring_test(rdev, TN_RING_TYPE_VCE1_INDEX, ring);
0368     if (r) {
0369         ring->ready = false;
0370         return r;
0371     }
0372
0373     ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
0374     ring->ready = true;
0375     r = radeon_ring_test(rdev, TN_RING_TYPE_VCE2_INDEX, ring);
0376     if (r) {
0377         ring->ready = false;
0378         return r;
0379     }
0380
0381     DRM_INFO("VCE initialized successfully.\n");
0382
0383     return 0;
0384 }