drm/radeon/uvd_v4_2.c

0001 /*
0002  * Copyright 2013 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Christian König <christian.koenig@amd.com>
0023  */
0024
0025 #include <linux/firmware.h>
0026
0027 #include "radeon.h"
0028 #include "radeon_asic.h"
0029 #include "cikd.h"
0030
0031 /**
0032  * uvd_v4_2_resume - memory controller programming
0033  *
0034  * @rdev: radeon_device pointer
0035  *
0036  * Let the UVD memory controller know it's offsets
0037  */
0038 int uvd_v4_2_resume(struct radeon_device *rdev)
0039 {
0040     uint64_t addr;
0041     uint32_t size;
0042
0043     /* program the VCPU memory controller bits 0-27 */
0044
0045     /* skip over the header of the new firmware format */
0046     if (rdev->uvd.fw_header_present)
0047         addr = (rdev->uvd.gpu_addr + 0x200) >> 3;
0048     else
0049         addr = rdev->uvd.gpu_addr >> 3;
0050
0051     size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;
0052     WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
0053     WREG32(UVD_VCPU_CACHE_SIZE0, size);
0054
0055     addr += size;
0056     size = RADEON_UVD_HEAP_SIZE >> 3;
0057     WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
0058     WREG32(UVD_VCPU_CACHE_SIZE1, size);
0059
0060     addr += size;
0061     size = (RADEON_UVD_STACK_SIZE +
0062            (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3;
0063     WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
0064     WREG32(UVD_VCPU_CACHE_SIZE2, size);
0065
0066     /* bits 28-31 */
0067     addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
0068     WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
0069
0070     /* bits 32-39 */
0071     addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
0072     WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
0073
0074     if (rdev->uvd.fw_header_present)
0075         WREG32(UVD_GP_SCRATCH4, rdev->uvd.max_handles);
0076
0077     return 0;
0078 }