drm/radeon/uvd_v2_2.c

0001 /*
0002  * Copyright 2013 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Christian König <christian.koenig@amd.com>
0023  */
0024
0025 #include <linux/firmware.h>
0026
0027 #include "radeon.h"
0028 #include "radeon_asic.h"
0029 #include "rv770d.h"
0030
0031 /**
0032  * uvd_v2_2_fence_emit - emit an fence & trap command
0033  *
0034  * @rdev: radeon_device pointer
0035  * @fence: fence to emit
0036  *
0037  * Write a fence and a trap command to the ring.
0038  */
0039 void uvd_v2_2_fence_emit(struct radeon_device *rdev,
0040              struct radeon_fence *fence)
0041 {
0042     struct radeon_ring *ring = &rdev->ring[fence->ring];
0043     uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
0044
0045     radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
0046     radeon_ring_write(ring, fence->seq);
0047     radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
0048     radeon_ring_write(ring, lower_32_bits(addr));
0049     radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
0050     radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
0051     radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
0052     radeon_ring_write(ring, 0);
0053
0054     radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
0055     radeon_ring_write(ring, 0);
0056     radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
0057     radeon_ring_write(ring, 0);
0058     radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
0059     radeon_ring_write(ring, 2);
0060 }
0061
0062 /**
0063  * uvd_v2_2_semaphore_emit - emit semaphore command
0064  *
0065  * @rdev: radeon_device pointer
0066  * @ring: radeon_ring pointer
0067  * @semaphore: semaphore to emit commands for
0068  * @emit_wait: true if we should emit a wait command
0069  *
0070  * Emit a semaphore command (either wait or signal) to the UVD ring.
0071  */
0072 bool uvd_v2_2_semaphore_emit(struct radeon_device *rdev,
0073                  struct radeon_ring *ring,
0074                  struct radeon_semaphore *semaphore,
0075                  bool emit_wait)
0076 {
0077     uint64_t addr = semaphore->gpu_addr;
0078
0079     radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
0080     radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
0081
0082     radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
0083     radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
0084
0085     radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
0086     radeon_ring_write(ring, emit_wait ? 1 : 0);
0087
0088     return true;
0089 }
0090
0091 /**
0092  * uvd_v2_2_resume - memory controller programming
0093  *
0094  * @rdev: radeon_device pointer
0095  *
0096  * Let the UVD memory controller know it's offsets
0097  */
0098 int uvd_v2_2_resume(struct radeon_device *rdev)
0099 {
0100     uint64_t addr;
0101     uint32_t chip_id, size;
0102     int r;
0103
0104     /* RV770 uses V1.0 MC */
0105     if (rdev->family == CHIP_RV770)
0106         return uvd_v1_0_resume(rdev);
0107
0108     r = radeon_uvd_resume(rdev);
0109     if (r)
0110         return r;
0111
0112     /* program the VCPU memory controller bits 0-27 */
0113     addr = rdev->uvd.gpu_addr >> 3;
0114     size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;
0115     WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
0116     WREG32(UVD_VCPU_CACHE_SIZE0, size);
0117
0118     addr += size;
0119     size = RADEON_UVD_HEAP_SIZE >> 3;
0120     WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
0121     WREG32(UVD_VCPU_CACHE_SIZE1, size);
0122
0123     addr += size;
0124     size = (RADEON_UVD_STACK_SIZE +
0125            (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3;
0126     WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
0127     WREG32(UVD_VCPU_CACHE_SIZE2, size);
0128
0129     /* bits 28-31 */
0130     addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
0131     WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
0132
0133     /* bits 32-39 */
0134     addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
0135     WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
0136
0137     /* tell firmware which hardware it is running on */
0138     switch (rdev->family) {
0139     default:
0140         return -EINVAL;
0141     case CHIP_RV710:
0142         chip_id = 0x01000005;
0143         break;
0144     case CHIP_RV730:
0145         chip_id = 0x01000006;
0146         break;
0147     case CHIP_RV740:
0148         chip_id = 0x01000007;
0149         break;
0150     case CHIP_CYPRESS:
0151     case CHIP_HEMLOCK:
0152         chip_id = 0x01000008;
0153         break;
0154     case CHIP_JUNIPER:
0155         chip_id = 0x01000009;
0156         break;
0157     case CHIP_REDWOOD:
0158         chip_id = 0x0100000a;
0159         break;
0160     case CHIP_CEDAR:
0161         chip_id = 0x0100000b;
0162         break;
0163     case CHIP_SUMO:
0164     case CHIP_SUMO2:
0165         chip_id = 0x0100000c;
0166         break;
0167     case CHIP_PALM:
0168         chip_id = 0x0100000e;
0169         break;
0170     case CHIP_CAYMAN:
0171         chip_id = 0x0100000f;
0172         break;
0173     case CHIP_BARTS:
0174         chip_id = 0x01000010;
0175         break;
0176     case CHIP_TURKS:
0177         chip_id = 0x01000011;
0178         break;
0179     case CHIP_CAICOS:
0180         chip_id = 0x01000012;
0181         break;
0182     case CHIP_TAHITI:
0183         chip_id = 0x01000014;
0184         break;
0185     case CHIP_VERDE:
0186         chip_id = 0x01000015;
0187         break;
0188     case CHIP_PITCAIRN:
0189     case CHIP_OLAND:
0190         chip_id = 0x01000016;
0191         break;
0192     case CHIP_ARUBA:
0193         chip_id = 0x01000017;
0194         break;
0195     }
0196     WREG32(UVD_VCPU_CHIP_ID, chip_id);
0197
0198     return 0;
0199 }