drm/radeon/trinity_dpm.h

0001 /*
0002  * Copyright 2012 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __TRINITY_DPM_H__
0024 #define __TRINITY_DPM_H__
0025
0026 #include "sumo_dpm.h"
0027
0028 #define TRINITY_SIZEOF_DPM_STATE_TABLE (SMU_SCLK_DPM_STATE_1_CNTL_0 - SMU_SCLK_DPM_STATE_0_CNTL_0)
0029
0030 struct trinity_pl {
0031     u32 sclk;
0032     u8 vddc_index;
0033     u8 ds_divider_index;
0034     u8 ss_divider_index;
0035     u8 allow_gnb_slow;
0036     u8 force_nbp_state;
0037     u8 display_wm;
0038     u8 vce_wm;
0039 };
0040
0041 #define TRINITY_POWERSTATE_FLAGS_NBPS_FORCEHIGH  (1 << 0)
0042 #define TRINITY_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH (1 << 1)
0043 #define TRINITY_POWERSTATE_FLAGS_NBPS_LOCKTOLOW  (1 << 2)
0044
0045 #define TRINITY_POWERSTATE_FLAGS_BAPM_DISABLE    (1 << 0)
0046
0047 struct trinity_ps {
0048     u32 num_levels;
0049     struct trinity_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
0050
0051     u32 nbps_flags;
0052     u32 bapm_flags;
0053
0054     u8 Dpm0PgNbPsLo;
0055     u8 Dpm0PgNbPsHi;
0056     u8 DpmXNbPsLo;
0057     u8 DpmXNbPsHi;
0058
0059     u32 vclk_low_divider;
0060     u32 vclk_high_divider;
0061     u32 dclk_low_divider;
0062     u32 dclk_high_divider;
0063 };
0064
0065 #define TRINITY_NUM_NBPSTATES   4
0066
0067 struct trinity_uvd_clock_table_entry
0068 {
0069     u32 vclk;
0070     u32 dclk;
0071     u8 vclk_did;
0072     u8 dclk_did;
0073     u8 rsv[2];
0074 };
0075
0076 struct trinity_sys_info {
0077     u32 bootup_uma_clk;
0078     u32 bootup_sclk;
0079     u32 min_sclk;
0080     u32 dentist_vco_freq;
0081     u32 nb_dpm_enable;
0082     u32 nbp_mclk[TRINITY_NUM_NBPSTATES];
0083     u32 nbp_nclk[TRINITY_NUM_NBPSTATES];
0084     u16 nbp_voltage_index[TRINITY_NUM_NBPSTATES];
0085     u16 bootup_nb_voltage_index;
0086     u8 htc_tmp_lmt;
0087     u8 htc_hyst_lmt;
0088     struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;
0089     struct sumo_vid_mapping_table vid_mapping_table;
0090     u32 uma_channel_number;
0091     struct trinity_uvd_clock_table_entry uvd_clock_table_entries[4];
0092 };
0093
0094 struct trinity_power_info {
0095     u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];
0096     u32 dpm_interval;
0097     u32 thermal_auto_throttling;
0098     struct trinity_sys_info sys_info;
0099     struct trinity_pl boot_pl;
0100     u32 min_sclk_did;
0101     bool enable_nbps_policy;
0102     bool voltage_drop_in_dce;
0103     bool override_dynamic_mgpg;
0104     bool enable_gfx_clock_gating;
0105     bool enable_gfx_power_gating;
0106     bool enable_mg_clock_gating;
0107     bool enable_gfx_dynamic_mgpg;
0108     bool enable_auto_thermal_throttling;
0109     bool enable_dpm;
0110     bool enable_sclk_ds;
0111     bool enable_bapm;
0112     bool uvd_dpm;
0113     struct radeon_ps current_rps;
0114     struct trinity_ps current_ps;
0115     struct radeon_ps requested_rps;
0116     struct trinity_ps requested_ps;
0117 };
0118
0119 #define TRINITY_AT_DFLT            30
0120
0121 /* trinity_smc.c */
0122 int trinity_dpm_bapm_enable(struct radeon_device *rdev, bool enable);
0123 int trinity_dpm_config(struct radeon_device *rdev, bool enable);
0124 int trinity_uvd_dpm_config(struct radeon_device *rdev);
0125 int trinity_dpm_force_state(struct radeon_device *rdev, u32 n);
0126 int trinity_dpm_n_levels_disabled(struct radeon_device *rdev, u32 n);
0127 int trinity_dpm_no_forced_level(struct radeon_device *rdev);
0128 int trinity_dce_enable_voltage_adjustment(struct radeon_device *rdev,
0129                       bool enable);
0130 int trinity_gfx_dynamic_mgpg_config(struct radeon_device *rdev);
0131 void trinity_acquire_mutex(struct radeon_device *rdev);
0132 void trinity_release_mutex(struct radeon_device *rdev);
0133
0134 #endif