drm/radeon/sumo_dpm.h

0001 /*
0002  * Copyright 2012 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __SUMO_DPM_H__
0024 #define __SUMO_DPM_H__
0025
0026 #include "atom.h"
0027 #include "radeon.h"
0028
0029 #define SUMO_MAX_HARDWARE_POWERLEVELS 5
0030 #define SUMO_PM_NUMBER_OF_TC 15
0031
0032 struct sumo_pl {
0033     u32 sclk;
0034     u32 vddc_index;
0035     u32 ds_divider_index;
0036     u32 ss_divider_index;
0037     u32 allow_gnb_slow;
0038     u32 sclk_dpm_tdp_limit;
0039 };
0040
0041 /* used for the flags field */
0042 #define SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE (1 << 0)
0043 #define SUMO_POWERSTATE_FLAGS_BOOST_STATE       (1 << 1)
0044
0045 struct sumo_ps {
0046     struct sumo_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
0047     u32 num_levels;
0048     /* flags */
0049     u32 flags;
0050 };
0051
0052 #define NUMBER_OF_M3ARB_PARAM_SETS 10
0053 #define SUMO_MAX_NUMBER_VOLTAGES    4
0054
0055 struct sumo_disp_clock_voltage_mapping_table {
0056     u32 num_max_voltage_levels;
0057     u32 display_clock_frequency[SUMO_MAX_NUMBER_VOLTAGES];
0058 };
0059
0060 struct sumo_vid_mapping_entry {
0061     u16 vid_2bit;
0062     u16 vid_7bit;
0063 };
0064
0065 struct sumo_vid_mapping_table {
0066     u32 num_entries;
0067     struct sumo_vid_mapping_entry entries[SUMO_MAX_NUMBER_VOLTAGES];
0068 };
0069
0070 struct sumo_sclk_voltage_mapping_entry {
0071     u32 sclk_frequency;
0072     u16 vid_2bit;
0073     u16 rsv;
0074 };
0075
0076 struct sumo_sclk_voltage_mapping_table {
0077     u32 num_max_dpm_entries;
0078     struct sumo_sclk_voltage_mapping_entry entries[SUMO_MAX_HARDWARE_POWERLEVELS];
0079 };
0080
0081 struct sumo_sys_info {
0082     u32 bootup_sclk;
0083     u32 min_sclk;
0084     u32 bootup_uma_clk;
0085     u16 bootup_nb_voltage_index;
0086     u8 htc_tmp_lmt;
0087     u8 htc_hyst_lmt;
0088     struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;
0089     struct sumo_disp_clock_voltage_mapping_table disp_clk_voltage_mapping_table;
0090     struct sumo_vid_mapping_table vid_mapping_table;
0091     u32 csr_m3_arb_cntl_default[NUMBER_OF_M3ARB_PARAM_SETS];
0092     u32 csr_m3_arb_cntl_uvd[NUMBER_OF_M3ARB_PARAM_SETS];
0093     u32 csr_m3_arb_cntl_fs3d[NUMBER_OF_M3ARB_PARAM_SETS];
0094     u32 sclk_dpm_boost_margin;
0095     u32 sclk_dpm_throttle_margin;
0096     u32 sclk_dpm_tdp_limit_pg;
0097     u32 gnb_tdp_limit;
0098     u32 sclk_dpm_tdp_limit_boost;
0099     u32 boost_sclk;
0100     u32 boost_vid_2bit;
0101     bool enable_boost;
0102 };
0103
0104 struct sumo_power_info {
0105     u32 asi;
0106     u32 pasi;
0107     u32 bsp;
0108     u32 bsu;
0109     u32 pbsp;
0110     u32 pbsu;
0111     u32 dsp;
0112     u32 psp;
0113     u32 thermal_auto_throttling;
0114     u32 uvd_m3_arbiter;
0115     u32 fw_version;
0116     struct sumo_sys_info sys_info;
0117     struct sumo_pl acpi_pl;
0118     struct sumo_pl boot_pl;
0119     struct sumo_pl boost_pl;
0120     bool disable_gfx_power_gating_in_uvd;
0121     bool driver_nbps_policy_disable;
0122     bool enable_alt_vddnb;
0123     bool enable_dynamic_m3_arbiter;
0124     bool enable_gfx_clock_gating;
0125     bool enable_gfx_power_gating;
0126     bool enable_mg_clock_gating;
0127     bool enable_sclk_ds;
0128     bool enable_auto_thermal_throttling;
0129     bool enable_dynamic_patch_ps;
0130     bool enable_dpm;
0131     bool enable_boost;
0132     struct radeon_ps current_rps;
0133     struct sumo_ps current_ps;
0134     struct radeon_ps requested_rps;
0135     struct sumo_ps requested_ps;
0136 };
0137
0138 #define SUMO_UTC_DFLT_00                     0x48
0139 #define SUMO_UTC_DFLT_01                     0x44
0140 #define SUMO_UTC_DFLT_02                     0x44
0141 #define SUMO_UTC_DFLT_03                     0x44
0142 #define SUMO_UTC_DFLT_04                     0x44
0143 #define SUMO_UTC_DFLT_05                     0x44
0144 #define SUMO_UTC_DFLT_06                     0x44
0145 #define SUMO_UTC_DFLT_07                     0x44
0146 #define SUMO_UTC_DFLT_08                     0x44
0147 #define SUMO_UTC_DFLT_09                     0x44
0148 #define SUMO_UTC_DFLT_10                     0x44
0149 #define SUMO_UTC_DFLT_11                     0x44
0150 #define SUMO_UTC_DFLT_12                     0x44
0151 #define SUMO_UTC_DFLT_13                     0x44
0152 #define SUMO_UTC_DFLT_14                     0x44
0153
0154 #define SUMO_DTC_DFLT_00                     0x48
0155 #define SUMO_DTC_DFLT_01                     0x44
0156 #define SUMO_DTC_DFLT_02                     0x44
0157 #define SUMO_DTC_DFLT_03                     0x44
0158 #define SUMO_DTC_DFLT_04                     0x44
0159 #define SUMO_DTC_DFLT_05                     0x44
0160 #define SUMO_DTC_DFLT_06                     0x44
0161 #define SUMO_DTC_DFLT_07                     0x44
0162 #define SUMO_DTC_DFLT_08                     0x44
0163 #define SUMO_DTC_DFLT_09                     0x44
0164 #define SUMO_DTC_DFLT_10                     0x44
0165 #define SUMO_DTC_DFLT_11                     0x44
0166 #define SUMO_DTC_DFLT_12                     0x44
0167 #define SUMO_DTC_DFLT_13                     0x44
0168 #define SUMO_DTC_DFLT_14                     0x44
0169
0170 #define SUMO_AH_DFLT               5
0171
0172 #define SUMO_R_DFLT0               70
0173 #define SUMO_R_DFLT1               70
0174 #define SUMO_R_DFLT2               70
0175 #define SUMO_R_DFLT3               70
0176 #define SUMO_R_DFLT4               100
0177
0178 #define SUMO_L_DFLT0               0
0179 #define SUMO_L_DFLT1               20
0180 #define SUMO_L_DFLT2               20
0181 #define SUMO_L_DFLT3               20
0182 #define SUMO_L_DFLT4               20
0183 #define SUMO_VRC_DFLT              0x30033
0184 #define SUMO_MGCGTTLOCAL0_DFLT     0
0185 #define SUMO_MGCGTTLOCAL1_DFLT     0
0186 #define SUMO_GICST_DFLT            19
0187 #define SUMO_SST_DFLT              8
0188 #define SUMO_VOLTAGEDROPT_DFLT     1
0189 #define SUMO_GFXPOWERGATINGT_DFLT  100
0190
0191 /* sumo_dpm.c */
0192 void sumo_gfx_clockgating_initialize(struct radeon_device *rdev);
0193 void sumo_program_vc(struct radeon_device *rdev, u32 vrc);
0194 void sumo_clear_vc(struct radeon_device *rdev);
0195 void sumo_program_sstp(struct radeon_device *rdev);
0196 void sumo_take_smu_control(struct radeon_device *rdev, bool enable);
0197 void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev,
0198                            struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
0199                            ATOM_AVAILABLE_SCLK_LIST *table);
0200 void sumo_construct_vid_mapping_table(struct radeon_device *rdev,
0201                       struct sumo_vid_mapping_table *vid_mapping_table,
0202                       ATOM_AVAILABLE_SCLK_LIST *table);
0203 u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,
0204                   struct sumo_vid_mapping_table *vid_mapping_table,
0205                   u32 vid_2bit);
0206 u32 sumo_get_sleep_divider_from_id(u32 id);
0207 u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
0208                      u32 sclk,
0209                      u32 min_sclk_in_sr);
0210 struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev);
0211
0212 /* sumo_smc.c */
0213 void sumo_initialize_m3_arb(struct radeon_device *rdev);
0214 void sumo_smu_pg_init(struct radeon_device *rdev);
0215 void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit);
0216 void sumo_smu_notify_alt_vddnb_change(struct radeon_device *rdev,
0217                       bool powersaving, bool force_nbps1);
0218 void sumo_boost_state_enable(struct radeon_device *rdev, bool enable);
0219 void sumo_enable_boost_timer(struct radeon_device *rdev);
0220 u32 sumo_get_running_fw_version(struct radeon_device *rdev);
0221
0222 #endif