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0001 /*
0002  * Copyright 2012 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #include "radeon.h"
0025 #include "radeon_asic.h"
0026 #include "sumod.h"
0027 #include "r600_dpm.h"
0028 #include "cypress_dpm.h"
0029 #include "sumo_dpm.h"
0030 #include <linux/seq_file.h>
0031 
0032 #define SUMO_MAX_DEEPSLEEP_DIVIDER_ID 5
0033 #define SUMO_MINIMUM_ENGINE_CLOCK 800
0034 #define BOOST_DPM_LEVEL 7
0035 
0036 static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] =
0037 {
0038     SUMO_UTC_DFLT_00,
0039     SUMO_UTC_DFLT_01,
0040     SUMO_UTC_DFLT_02,
0041     SUMO_UTC_DFLT_03,
0042     SUMO_UTC_DFLT_04,
0043     SUMO_UTC_DFLT_05,
0044     SUMO_UTC_DFLT_06,
0045     SUMO_UTC_DFLT_07,
0046     SUMO_UTC_DFLT_08,
0047     SUMO_UTC_DFLT_09,
0048     SUMO_UTC_DFLT_10,
0049     SUMO_UTC_DFLT_11,
0050     SUMO_UTC_DFLT_12,
0051     SUMO_UTC_DFLT_13,
0052     SUMO_UTC_DFLT_14,
0053 };
0054 
0055 static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] =
0056 {
0057     SUMO_DTC_DFLT_00,
0058     SUMO_DTC_DFLT_01,
0059     SUMO_DTC_DFLT_02,
0060     SUMO_DTC_DFLT_03,
0061     SUMO_DTC_DFLT_04,
0062     SUMO_DTC_DFLT_05,
0063     SUMO_DTC_DFLT_06,
0064     SUMO_DTC_DFLT_07,
0065     SUMO_DTC_DFLT_08,
0066     SUMO_DTC_DFLT_09,
0067     SUMO_DTC_DFLT_10,
0068     SUMO_DTC_DFLT_11,
0069     SUMO_DTC_DFLT_12,
0070     SUMO_DTC_DFLT_13,
0071     SUMO_DTC_DFLT_14,
0072 };
0073 
0074 static struct sumo_ps *sumo_get_ps(struct radeon_ps *rps)
0075 {
0076     struct sumo_ps *ps = rps->ps_priv;
0077 
0078     return ps;
0079 }
0080 
0081 struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev)
0082 {
0083     struct sumo_power_info *pi = rdev->pm.dpm.priv;
0084 
0085     return pi;
0086 }
0087 
0088 static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
0089 {
0090     if (enable)
0091         WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
0092     else {
0093         WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
0094         WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
0095         WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
0096         RREG32(GB_ADDR_CONFIG);
0097     }
0098 }
0099 
0100 #define CGCG_CGTT_LOCAL0_MASK 0xE5BFFFFF
0101 #define CGCG_CGTT_LOCAL1_MASK 0xEFFF07FF
0102 
0103 static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable)
0104 {
0105     u32 local0;
0106     u32 local1;
0107 
0108     local0 = RREG32(CG_CGTT_LOCAL_0);
0109     local1 = RREG32(CG_CGTT_LOCAL_1);
0110 
0111     if (enable) {
0112         WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
0113         WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
0114     } else {
0115         WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
0116         WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
0117     }
0118 }
0119 
0120 static void sumo_program_git(struct radeon_device *rdev)
0121 {
0122     u32 p, u;
0123     u32 xclk = radeon_get_xclk(rdev);
0124 
0125     r600_calculate_u_and_p(SUMO_GICST_DFLT,
0126                    xclk, 16, &p, &u);
0127 
0128     WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK);
0129 }
0130 
0131 static void sumo_program_grsd(struct radeon_device *rdev)
0132 {
0133     u32 p, u;
0134     u32 xclk = radeon_get_xclk(rdev);
0135     u32 grs = 256 * 25 / 100;
0136 
0137     r600_calculate_u_and_p(1, xclk, 14, &p, &u);
0138 
0139     WREG32(CG_GCOOR, PHC(grs) | SDC(p) | SU(u));
0140 }
0141 
0142 void sumo_gfx_clockgating_initialize(struct radeon_device *rdev)
0143 {
0144     sumo_program_git(rdev);
0145     sumo_program_grsd(rdev);
0146 }
0147 
0148 static void sumo_gfx_powergating_initialize(struct radeon_device *rdev)
0149 {
0150     u32 rcu_pwr_gating_cntl;
0151     u32 p, u;
0152     u32 p_c, p_p, d_p;
0153     u32 r_t, i_t;
0154     u32 xclk = radeon_get_xclk(rdev);
0155 
0156     if (rdev->family == CHIP_PALM) {
0157         p_c = 4;
0158         d_p = 10;
0159         r_t = 10;
0160         i_t = 4;
0161         p_p = 50 + 1000/200 + 6 * 32;
0162     } else {
0163         p_c = 16;
0164         d_p = 50;
0165         r_t = 50;
0166         i_t  = 50;
0167         p_p = 113;
0168     }
0169 
0170     WREG32(CG_SCRATCH2, 0x01B60A17);
0171 
0172     r600_calculate_u_and_p(SUMO_GFXPOWERGATINGT_DFLT,
0173                    xclk, 16, &p, &u);
0174 
0175     WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u),
0176          ~(PGP_MASK | PGU_MASK));
0177 
0178     r600_calculate_u_and_p(SUMO_VOLTAGEDROPT_DFLT,
0179                    xclk, 16, &p, &u);
0180 
0181     WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u),
0182          ~(PGP_MASK | PGU_MASK));
0183 
0184     if (rdev->family == CHIP_PALM) {
0185         WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x10103210);
0186         WREG32_RCU(RCU_PWR_GATING_SEQ1, 0x10101010);
0187     } else {
0188         WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x76543210);
0189         WREG32_RCU(RCU_PWR_GATING_SEQ1, 0xFEDCBA98);
0190     }
0191 
0192     rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
0193     rcu_pwr_gating_cntl &=
0194         ~(RSVD_MASK | PCV_MASK | PGS_MASK);
0195     rcu_pwr_gating_cntl |= PCV(p_c) | PGS(1) | PWR_GATING_EN;
0196     if (rdev->family == CHIP_PALM) {
0197         rcu_pwr_gating_cntl &= ~PCP_MASK;
0198         rcu_pwr_gating_cntl |= PCP(0x77);
0199     }
0200     WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
0201 
0202     rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
0203     rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
0204     rcu_pwr_gating_cntl |= MPPU(p_p) | MPPD(50);
0205     WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
0206 
0207     rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
0208     rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
0209     rcu_pwr_gating_cntl |= DPPU(d_p) | DPPD(50);
0210     WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
0211 
0212     rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_4);
0213     rcu_pwr_gating_cntl &= ~(RT_MASK | IT_MASK);
0214     rcu_pwr_gating_cntl |= RT(r_t) | IT(i_t);
0215     WREG32_RCU(RCU_PWR_GATING_CNTL_4, rcu_pwr_gating_cntl);
0216 
0217     if (rdev->family == CHIP_PALM)
0218         WREG32_RCU(RCU_PWR_GATING_CNTL_5, 0xA02);
0219 
0220     sumo_smu_pg_init(rdev);
0221 
0222     rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
0223     rcu_pwr_gating_cntl &=
0224         ~(RSVD_MASK | PCV_MASK | PGS_MASK);
0225     rcu_pwr_gating_cntl |= PCV(p_c) | PGS(4) | PWR_GATING_EN;
0226     if (rdev->family == CHIP_PALM) {
0227         rcu_pwr_gating_cntl &= ~PCP_MASK;
0228         rcu_pwr_gating_cntl |= PCP(0x77);
0229     }
0230     WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
0231 
0232     if (rdev->family == CHIP_PALM) {
0233         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
0234         rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
0235         rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50);
0236         WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
0237 
0238         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
0239         rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
0240         rcu_pwr_gating_cntl |= DPPU(16) | DPPD(50);
0241         WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
0242     }
0243 
0244     sumo_smu_pg_init(rdev);
0245 
0246     rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
0247     rcu_pwr_gating_cntl &=
0248         ~(RSVD_MASK | PCV_MASK | PGS_MASK);
0249     rcu_pwr_gating_cntl |= PGS(5) | PWR_GATING_EN;
0250 
0251     if (rdev->family == CHIP_PALM) {
0252         rcu_pwr_gating_cntl |= PCV(4);
0253         rcu_pwr_gating_cntl &= ~PCP_MASK;
0254         rcu_pwr_gating_cntl |= PCP(0x77);
0255     } else
0256         rcu_pwr_gating_cntl |= PCV(11);
0257     WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
0258 
0259     if (rdev->family == CHIP_PALM) {
0260         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
0261         rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
0262         rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50);
0263         WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
0264 
0265         rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
0266         rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
0267         rcu_pwr_gating_cntl |= DPPU(22) | DPPD(50);
0268         WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
0269     }
0270 
0271     sumo_smu_pg_init(rdev);
0272 }
0273 
0274 static void sumo_gfx_powergating_enable(struct radeon_device *rdev, bool enable)
0275 {
0276     if (enable)
0277         WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN);
0278     else {
0279         WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN);
0280         RREG32(GB_ADDR_CONFIG);
0281     }
0282 }
0283 
0284 static int sumo_enable_clock_power_gating(struct radeon_device *rdev)
0285 {
0286     struct sumo_power_info *pi = sumo_get_pi(rdev);
0287 
0288     if (pi->enable_gfx_clock_gating)
0289         sumo_gfx_clockgating_initialize(rdev);
0290     if (pi->enable_gfx_power_gating)
0291         sumo_gfx_powergating_initialize(rdev);
0292     if (pi->enable_mg_clock_gating)
0293         sumo_mg_clockgating_enable(rdev, true);
0294     if (pi->enable_gfx_clock_gating)
0295         sumo_gfx_clockgating_enable(rdev, true);
0296     if (pi->enable_gfx_power_gating)
0297         sumo_gfx_powergating_enable(rdev, true);
0298 
0299     return 0;
0300 }
0301 
0302 static void sumo_disable_clock_power_gating(struct radeon_device *rdev)
0303 {
0304     struct sumo_power_info *pi = sumo_get_pi(rdev);
0305 
0306     if (pi->enable_gfx_clock_gating)
0307         sumo_gfx_clockgating_enable(rdev, false);
0308     if (pi->enable_gfx_power_gating)
0309         sumo_gfx_powergating_enable(rdev, false);
0310     if (pi->enable_mg_clock_gating)
0311         sumo_mg_clockgating_enable(rdev, false);
0312 }
0313 
0314 static void sumo_calculate_bsp(struct radeon_device *rdev,
0315                    u32 high_clk)
0316 {
0317     struct sumo_power_info *pi = sumo_get_pi(rdev);
0318     u32 xclk = radeon_get_xclk(rdev);
0319 
0320     pi->pasi = 65535 * 100 / high_clk;
0321     pi->asi = 65535 * 100 / high_clk;
0322 
0323     r600_calculate_u_and_p(pi->asi,
0324                    xclk, 16, &pi->bsp, &pi->bsu);
0325 
0326     r600_calculate_u_and_p(pi->pasi,
0327                    xclk, 16, &pi->pbsp, &pi->pbsu);
0328 
0329     pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
0330     pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
0331 }
0332 
0333 static void sumo_init_bsp(struct radeon_device *rdev)
0334 {
0335     struct sumo_power_info *pi = sumo_get_pi(rdev);
0336 
0337     WREG32(CG_BSP_0, pi->psp);
0338 }
0339 
0340 
0341 static void sumo_program_bsp(struct radeon_device *rdev,
0342                  struct radeon_ps *rps)
0343 {
0344     struct sumo_power_info *pi = sumo_get_pi(rdev);
0345     struct sumo_ps *ps = sumo_get_ps(rps);
0346     u32 i;
0347     u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk;
0348 
0349     if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
0350         highest_engine_clock = pi->boost_pl.sclk;
0351 
0352     sumo_calculate_bsp(rdev, highest_engine_clock);
0353 
0354     for (i = 0; i < ps->num_levels - 1; i++)
0355         WREG32(CG_BSP_0 + (i * 4), pi->dsp);
0356 
0357     WREG32(CG_BSP_0 + (i * 4), pi->psp);
0358 
0359     if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
0360         WREG32(CG_BSP_0 + (BOOST_DPM_LEVEL * 4), pi->psp);
0361 }
0362 
0363 static void sumo_write_at(struct radeon_device *rdev,
0364               u32 index, u32 value)
0365 {
0366     if (index == 0)
0367         WREG32(CG_AT_0, value);
0368     else if (index == 1)
0369         WREG32(CG_AT_1, value);
0370     else if (index == 2)
0371         WREG32(CG_AT_2, value);
0372     else if (index == 3)
0373         WREG32(CG_AT_3, value);
0374     else if (index == 4)
0375         WREG32(CG_AT_4, value);
0376     else if (index == 5)
0377         WREG32(CG_AT_5, value);
0378     else if (index == 6)
0379         WREG32(CG_AT_6, value);
0380     else if (index == 7)
0381         WREG32(CG_AT_7, value);
0382 }
0383 
0384 static void sumo_program_at(struct radeon_device *rdev,
0385                 struct radeon_ps *rps)
0386 {
0387     struct sumo_power_info *pi = sumo_get_pi(rdev);
0388     struct sumo_ps *ps = sumo_get_ps(rps);
0389     u32 asi;
0390     u32 i;
0391     u32 m_a;
0392     u32 a_t;
0393     u32 r[SUMO_MAX_HARDWARE_POWERLEVELS];
0394     u32 l[SUMO_MAX_HARDWARE_POWERLEVELS];
0395 
0396     r[0] = SUMO_R_DFLT0;
0397     r[1] = SUMO_R_DFLT1;
0398     r[2] = SUMO_R_DFLT2;
0399     r[3] = SUMO_R_DFLT3;
0400     r[4] = SUMO_R_DFLT4;
0401 
0402     l[0] = SUMO_L_DFLT0;
0403     l[1] = SUMO_L_DFLT1;
0404     l[2] = SUMO_L_DFLT2;
0405     l[3] = SUMO_L_DFLT3;
0406     l[4] = SUMO_L_DFLT4;
0407 
0408     for (i = 0; i < ps->num_levels; i++) {
0409         asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi;
0410 
0411         m_a = asi * ps->levels[i].sclk / 100;
0412 
0413         a_t = CG_R(m_a * r[i] / 100) | CG_L(m_a * l[i] / 100);
0414 
0415         sumo_write_at(rdev, i, a_t);
0416     }
0417 
0418     if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) {
0419         asi = pi->pasi;
0420 
0421         m_a = asi * pi->boost_pl.sclk / 100;
0422 
0423         a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) |
0424             CG_L(m_a * l[ps->num_levels - 1] / 100);
0425 
0426         sumo_write_at(rdev, BOOST_DPM_LEVEL, a_t);
0427     }
0428 }
0429 
0430 static void sumo_program_tp(struct radeon_device *rdev)
0431 {
0432     int i;
0433     enum r600_td td = R600_TD_DFLT;
0434 
0435     for (i = 0; i < SUMO_PM_NUMBER_OF_TC; i++) {
0436         WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK);
0437         WREG32_P(CG_FFCT_0 + (i * 4), DTC_0(sumo_dtc[i]), ~DTC_0_MASK);
0438     }
0439 
0440     if (td == R600_TD_AUTO)
0441         WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
0442     else
0443         WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
0444 
0445     if (td == R600_TD_UP)
0446         WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
0447 
0448     if (td == R600_TD_DOWN)
0449         WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
0450 }
0451 
0452 void sumo_program_vc(struct radeon_device *rdev, u32 vrc)
0453 {
0454     WREG32(CG_FTV, vrc);
0455 }
0456 
0457 void sumo_clear_vc(struct radeon_device *rdev)
0458 {
0459     WREG32(CG_FTV, 0);
0460 }
0461 
0462 void sumo_program_sstp(struct radeon_device *rdev)
0463 {
0464     u32 p, u;
0465     u32 xclk = radeon_get_xclk(rdev);
0466 
0467     r600_calculate_u_and_p(SUMO_SST_DFLT,
0468                    xclk, 16, &p, &u);
0469 
0470     WREG32(CG_SSP, SSTU(u) | SST(p));
0471 }
0472 
0473 static void sumo_set_divider_value(struct radeon_device *rdev,
0474                    u32 index, u32 divider)
0475 {
0476     u32 reg_index = index / 4;
0477     u32 field_index = index % 4;
0478 
0479     if (field_index == 0)
0480         WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
0481              SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK);
0482     else if (field_index == 1)
0483         WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
0484              SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK);
0485     else if (field_index == 2)
0486         WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
0487              SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK);
0488     else if (field_index == 3)
0489         WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
0490              SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK);
0491 }
0492 
0493 static void sumo_set_ds_dividers(struct radeon_device *rdev,
0494                  u32 index, u32 divider)
0495 {
0496     struct sumo_power_info *pi = sumo_get_pi(rdev);
0497 
0498     if (pi->enable_sclk_ds) {
0499         u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6);
0500 
0501         dpm_ctrl &= ~(0x7 << (index * 3));
0502         dpm_ctrl |= (divider << (index * 3));
0503         WREG32(CG_SCLK_DPM_CTRL_6, dpm_ctrl);
0504     }
0505 }
0506 
0507 static void sumo_set_ss_dividers(struct radeon_device *rdev,
0508                  u32 index, u32 divider)
0509 {
0510     struct sumo_power_info *pi = sumo_get_pi(rdev);
0511 
0512     if (pi->enable_sclk_ds) {
0513         u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11);
0514 
0515         dpm_ctrl &= ~(0x7 << (index * 3));
0516         dpm_ctrl |= (divider << (index * 3));
0517         WREG32(CG_SCLK_DPM_CTRL_11, dpm_ctrl);
0518     }
0519 }
0520 
0521 static void sumo_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
0522 {
0523     u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL);
0524 
0525     voltage_cntl &= ~(DPM_STATE0_LEVEL_MASK << (index * 2));
0526     voltage_cntl |= (vid << (DPM_STATE0_LEVEL_SHIFT + index * 2));
0527     WREG32(CG_DPM_VOLTAGE_CNTL, voltage_cntl);
0528 }
0529 
0530 static void sumo_set_allos_gnb_slow(struct radeon_device *rdev, u32 index, u32 gnb_slow)
0531 {
0532     struct sumo_power_info *pi = sumo_get_pi(rdev);
0533     u32 temp = gnb_slow;
0534     u32 cg_sclk_dpm_ctrl_3;
0535 
0536     if (pi->driver_nbps_policy_disable)
0537         temp = 1;
0538 
0539     cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
0540     cg_sclk_dpm_ctrl_3 &= ~(GNB_SLOW_FSTATE_0_MASK << index);
0541     cg_sclk_dpm_ctrl_3 |= (temp << (GNB_SLOW_FSTATE_0_SHIFT + index));
0542 
0543     WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
0544 }
0545 
0546 static void sumo_program_power_level(struct radeon_device *rdev,
0547                      struct sumo_pl *pl, u32 index)
0548 {
0549     struct sumo_power_info *pi = sumo_get_pi(rdev);
0550     int ret;
0551     struct atom_clock_dividers dividers;
0552     u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS;
0553 
0554     ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
0555                          pl->sclk, false, &dividers);
0556     if (ret)
0557         return;
0558 
0559     sumo_set_divider_value(rdev, index, dividers.post_div);
0560 
0561     sumo_set_vid(rdev, index, pl->vddc_index);
0562 
0563     if (pl->ss_divider_index == 0 || pl->ds_divider_index == 0) {
0564         if (ds_en)
0565             WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
0566     } else {
0567         sumo_set_ss_dividers(rdev, index, pl->ss_divider_index);
0568         sumo_set_ds_dividers(rdev, index, pl->ds_divider_index);
0569 
0570         if (!ds_en)
0571             WREG32_P(DEEP_SLEEP_CNTL, ENABLE_DS, ~ENABLE_DS);
0572     }
0573 
0574     sumo_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow);
0575 
0576     if (pi->enable_boost)
0577         sumo_set_tdp_limit(rdev, index, pl->sclk_dpm_tdp_limit);
0578 }
0579 
0580 static void sumo_power_level_enable(struct radeon_device *rdev, u32 index, bool enable)
0581 {
0582     u32 reg_index = index / 4;
0583     u32 field_index = index % 4;
0584 
0585     if (field_index == 0)
0586         WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
0587              enable ? SCLK_FSTATE_0_VLD : 0, ~SCLK_FSTATE_0_VLD);
0588     else if (field_index == 1)
0589         WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
0590              enable ? SCLK_FSTATE_1_VLD : 0, ~SCLK_FSTATE_1_VLD);
0591     else if (field_index == 2)
0592         WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
0593              enable ? SCLK_FSTATE_2_VLD : 0, ~SCLK_FSTATE_2_VLD);
0594     else if (field_index == 3)
0595         WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
0596              enable ? SCLK_FSTATE_3_VLD : 0, ~SCLK_FSTATE_3_VLD);
0597 }
0598 
0599 static bool sumo_dpm_enabled(struct radeon_device *rdev)
0600 {
0601     if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE)
0602         return true;
0603     else
0604         return false;
0605 }
0606 
0607 static void sumo_start_dpm(struct radeon_device *rdev)
0608 {
0609     WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE);
0610 }
0611 
0612 static void sumo_stop_dpm(struct radeon_device *rdev)
0613 {
0614     WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE);
0615 }
0616 
0617 static void sumo_set_forced_mode(struct radeon_device *rdev, bool enable)
0618 {
0619     if (enable)
0620         WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE_EN, ~FORCE_SCLK_STATE_EN);
0621     else
0622         WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_SCLK_STATE_EN);
0623 }
0624 
0625 static void sumo_set_forced_mode_enabled(struct radeon_device *rdev)
0626 {
0627     int i;
0628 
0629     sumo_set_forced_mode(rdev, true);
0630     for (i = 0; i < rdev->usec_timeout; i++) {
0631         if (RREG32(CG_SCLK_STATUS) & SCLK_OVERCLK_DETECT)
0632             break;
0633         udelay(1);
0634     }
0635 }
0636 
0637 static void sumo_wait_for_level_0(struct radeon_device *rdev)
0638 {
0639     int i;
0640 
0641     for (i = 0; i < rdev->usec_timeout; i++) {
0642         if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) == 0)
0643             break;
0644         udelay(1);
0645     }
0646     for (i = 0; i < rdev->usec_timeout; i++) {
0647         if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) == 0)
0648             break;
0649         udelay(1);
0650     }
0651 }
0652 
0653 static void sumo_set_forced_mode_disabled(struct radeon_device *rdev)
0654 {
0655     sumo_set_forced_mode(rdev, false);
0656 }
0657 
0658 static void sumo_enable_power_level_0(struct radeon_device *rdev)
0659 {
0660     sumo_power_level_enable(rdev, 0, true);
0661 }
0662 
0663 static void sumo_patch_boost_state(struct radeon_device *rdev,
0664                    struct radeon_ps *rps)
0665 {
0666     struct sumo_power_info *pi = sumo_get_pi(rdev);
0667     struct sumo_ps *new_ps = sumo_get_ps(rps);
0668 
0669     if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) {
0670         pi->boost_pl = new_ps->levels[new_ps->num_levels - 1];
0671         pi->boost_pl.sclk = pi->sys_info.boost_sclk;
0672         pi->boost_pl.vddc_index = pi->sys_info.boost_vid_2bit;
0673         pi->boost_pl.sclk_dpm_tdp_limit = pi->sys_info.sclk_dpm_tdp_limit_boost;
0674     }
0675 }
0676 
0677 static void sumo_pre_notify_alt_vddnb_change(struct radeon_device *rdev,
0678                          struct radeon_ps *new_rps,
0679                          struct radeon_ps *old_rps)
0680 {
0681     struct sumo_ps *new_ps = sumo_get_ps(new_rps);
0682     struct sumo_ps *old_ps = sumo_get_ps(old_rps);
0683     u32 nbps1_old = 0;
0684     u32 nbps1_new = 0;
0685 
0686     if (old_ps != NULL)
0687         nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
0688 
0689     nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
0690 
0691     if (nbps1_old == 1 && nbps1_new == 0)
0692         sumo_smu_notify_alt_vddnb_change(rdev, 0, 0);
0693 }
0694 
0695 static void sumo_post_notify_alt_vddnb_change(struct radeon_device *rdev,
0696                           struct radeon_ps *new_rps,
0697                           struct radeon_ps *old_rps)
0698 {
0699     struct sumo_ps *new_ps = sumo_get_ps(new_rps);
0700     struct sumo_ps *old_ps = sumo_get_ps(old_rps);
0701     u32 nbps1_old = 0;
0702     u32 nbps1_new = 0;
0703 
0704     if (old_ps != NULL)
0705         nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
0706 
0707     nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
0708 
0709     if (nbps1_old == 0 && nbps1_new == 1)
0710         sumo_smu_notify_alt_vddnb_change(rdev, 1, 1);
0711 }
0712 
0713 static void sumo_enable_boost(struct radeon_device *rdev,
0714                   struct radeon_ps *rps,
0715                   bool enable)
0716 {
0717     struct sumo_ps *new_ps = sumo_get_ps(rps);
0718 
0719     if (enable) {
0720         if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
0721             sumo_boost_state_enable(rdev, true);
0722     } else
0723         sumo_boost_state_enable(rdev, false);
0724 }
0725 
0726 static void sumo_set_forced_level(struct radeon_device *rdev, u32 index)
0727 {
0728     WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE(index), ~FORCE_SCLK_STATE_MASK);
0729 }
0730 
0731 static void sumo_set_forced_level_0(struct radeon_device *rdev)
0732 {
0733     sumo_set_forced_level(rdev, 0);
0734 }
0735 
0736 static void sumo_program_wl(struct radeon_device *rdev,
0737                 struct radeon_ps *rps)
0738 {
0739     struct sumo_ps *new_ps = sumo_get_ps(rps);
0740     u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
0741 
0742     dpm_ctrl4 &= 0xFFFFFF00;
0743     dpm_ctrl4 |= (1 << (new_ps->num_levels - 1));
0744 
0745     if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
0746         dpm_ctrl4 |= (1 << BOOST_DPM_LEVEL);
0747 
0748     WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
0749 }
0750 
0751 static void sumo_program_power_levels_0_to_n(struct radeon_device *rdev,
0752                          struct radeon_ps *new_rps,
0753                          struct radeon_ps *old_rps)
0754 {
0755     struct sumo_power_info *pi = sumo_get_pi(rdev);
0756     struct sumo_ps *new_ps = sumo_get_ps(new_rps);
0757     struct sumo_ps *old_ps = sumo_get_ps(old_rps);
0758     u32 i;
0759     u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels;
0760 
0761     for (i = 0; i < new_ps->num_levels; i++) {
0762         sumo_program_power_level(rdev, &new_ps->levels[i], i);
0763         sumo_power_level_enable(rdev, i, true);
0764     }
0765 
0766     for (i = new_ps->num_levels; i < n_current_state_levels; i++)
0767         sumo_power_level_enable(rdev, i, false);
0768 
0769     if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
0770         sumo_program_power_level(rdev, &pi->boost_pl, BOOST_DPM_LEVEL);
0771 }
0772 
0773 static void sumo_enable_acpi_pm(struct radeon_device *rdev)
0774 {
0775     WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
0776 }
0777 
0778 static void sumo_program_power_level_enter_state(struct radeon_device *rdev)
0779 {
0780     WREG32_P(CG_SCLK_DPM_CTRL_5, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK);
0781 }
0782 
0783 static void sumo_program_acpi_power_level(struct radeon_device *rdev)
0784 {
0785     struct sumo_power_info *pi = sumo_get_pi(rdev);
0786     struct atom_clock_dividers dividers;
0787     int ret;
0788 
0789     ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
0790                          pi->acpi_pl.sclk,
0791                          false, &dividers);
0792     if (ret)
0793         return;
0794 
0795     WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK);
0796     WREG32_P(CG_ACPI_VOLTAGE_CNTL, 0, ~ACPI_VOLTAGE_EN);
0797 }
0798 
0799 static void sumo_program_bootup_state(struct radeon_device *rdev)
0800 {
0801     struct sumo_power_info *pi = sumo_get_pi(rdev);
0802     u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
0803     u32 i;
0804 
0805     sumo_program_power_level(rdev, &pi->boot_pl, 0);
0806 
0807     dpm_ctrl4 &= 0xFFFFFF00;
0808     WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
0809 
0810     for (i = 1; i < 8; i++)
0811         sumo_power_level_enable(rdev, i, false);
0812 }
0813 
0814 static void sumo_setup_uvd_clocks(struct radeon_device *rdev,
0815                   struct radeon_ps *new_rps,
0816                   struct radeon_ps *old_rps)
0817 {
0818     struct sumo_power_info *pi = sumo_get_pi(rdev);
0819 
0820     if (pi->enable_gfx_power_gating) {
0821         sumo_gfx_powergating_enable(rdev, false);
0822     }
0823 
0824     radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
0825 
0826     if (pi->enable_gfx_power_gating) {
0827         if (!pi->disable_gfx_power_gating_in_uvd ||
0828             !r600_is_uvd_state(new_rps->class, new_rps->class2))
0829             sumo_gfx_powergating_enable(rdev, true);
0830     }
0831 }
0832 
0833 static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
0834                             struct radeon_ps *new_rps,
0835                             struct radeon_ps *old_rps)
0836 {
0837     struct sumo_ps *new_ps = sumo_get_ps(new_rps);
0838     struct sumo_ps *current_ps = sumo_get_ps(old_rps);
0839 
0840     if ((new_rps->vclk == old_rps->vclk) &&
0841         (new_rps->dclk == old_rps->dclk))
0842         return;
0843 
0844     if (new_ps->levels[new_ps->num_levels - 1].sclk >=
0845         current_ps->levels[current_ps->num_levels - 1].sclk)
0846         return;
0847 
0848     sumo_setup_uvd_clocks(rdev, new_rps, old_rps);
0849 }
0850 
0851 static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
0852                            struct radeon_ps *new_rps,
0853                            struct radeon_ps *old_rps)
0854 {
0855     struct sumo_ps *new_ps = sumo_get_ps(new_rps);
0856     struct sumo_ps *current_ps = sumo_get_ps(old_rps);
0857 
0858     if ((new_rps->vclk == old_rps->vclk) &&
0859         (new_rps->dclk == old_rps->dclk))
0860         return;
0861 
0862     if (new_ps->levels[new_ps->num_levels - 1].sclk <
0863         current_ps->levels[current_ps->num_levels - 1].sclk)
0864         return;
0865 
0866     sumo_setup_uvd_clocks(rdev, new_rps, old_rps);
0867 }
0868 
0869 void sumo_take_smu_control(struct radeon_device *rdev, bool enable)
0870 {
0871 /* This bit selects who handles display phy powergating.
0872  * Clear the bit to let atom handle it.
0873  * Set it to let the driver handle it.
0874  * For now we just let atom handle it.
0875  */
0876 #if 0
0877     u32 v = RREG32(DOUT_SCRATCH3);
0878 
0879     if (enable)
0880         v |= 0x4;
0881     else
0882         v &= 0xFFFFFFFB;
0883 
0884     WREG32(DOUT_SCRATCH3, v);
0885 #endif
0886 }
0887 
0888 static void sumo_enable_sclk_ds(struct radeon_device *rdev, bool enable)
0889 {
0890     if (enable) {
0891         u32 deep_sleep_cntl = RREG32(DEEP_SLEEP_CNTL);
0892         u32 deep_sleep_cntl2 = RREG32(DEEP_SLEEP_CNTL2);
0893         u32 t = 1;
0894 
0895         deep_sleep_cntl &= ~R_DIS;
0896         deep_sleep_cntl &= ~HS_MASK;
0897         deep_sleep_cntl |= HS(t > 4095 ? 4095 : t);
0898 
0899         deep_sleep_cntl2 |= LB_UFP_EN;
0900         deep_sleep_cntl2 &= INOUT_C_MASK;
0901         deep_sleep_cntl2 |= INOUT_C(0xf);
0902 
0903         WREG32(DEEP_SLEEP_CNTL2, deep_sleep_cntl2);
0904         WREG32(DEEP_SLEEP_CNTL, deep_sleep_cntl);
0905     } else
0906         WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
0907 }
0908 
0909 static void sumo_program_bootup_at(struct radeon_device *rdev)
0910 {
0911     WREG32_P(CG_AT_0, CG_R(0xffff), ~CG_R_MASK);
0912     WREG32_P(CG_AT_0, CG_L(0), ~CG_L_MASK);
0913 }
0914 
0915 static void sumo_reset_am(struct radeon_device *rdev)
0916 {
0917     WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET);
0918 }
0919 
0920 static void sumo_start_am(struct radeon_device *rdev)
0921 {
0922     WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_RESET);
0923 }
0924 
0925 static void sumo_program_ttp(struct radeon_device *rdev)
0926 {
0927     u32 xclk = radeon_get_xclk(rdev);
0928     u32 p, u;
0929     u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5);
0930 
0931     r600_calculate_u_and_p(1000,
0932                    xclk, 16, &p, &u);
0933 
0934     cg_sclk_dpm_ctrl_5 &= ~(TT_TP_MASK | TT_TU_MASK);
0935     cg_sclk_dpm_ctrl_5 |= TT_TP(p) | TT_TU(u);
0936 
0937     WREG32(CG_SCLK_DPM_CTRL_5, cg_sclk_dpm_ctrl_5);
0938 }
0939 
0940 static void sumo_program_ttt(struct radeon_device *rdev)
0941 {
0942     u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
0943     struct sumo_power_info *pi = sumo_get_pi(rdev);
0944 
0945     cg_sclk_dpm_ctrl_3 &= ~(GNB_TT_MASK | GNB_THERMTHRO_MASK);
0946     cg_sclk_dpm_ctrl_3 |= GNB_TT(pi->thermal_auto_throttling + 49);
0947 
0948     WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
0949 }
0950 
0951 
0952 static void sumo_enable_voltage_scaling(struct radeon_device *rdev, bool enable)
0953 {
0954     if (enable) {
0955         WREG32_P(CG_DPM_VOLTAGE_CNTL, DPM_VOLTAGE_EN, ~DPM_VOLTAGE_EN);
0956         WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~CG_VOLTAGE_EN);
0957     } else {
0958         WREG32_P(CG_CG_VOLTAGE_CNTL, CG_VOLTAGE_EN, ~CG_VOLTAGE_EN);
0959         WREG32_P(CG_DPM_VOLTAGE_CNTL, 0, ~DPM_VOLTAGE_EN);
0960     }
0961 }
0962 
0963 static void sumo_override_cnb_thermal_events(struct radeon_device *rdev)
0964 {
0965     WREG32_P(CG_SCLK_DPM_CTRL_3, CNB_THERMTHRO_MASK_SCLK,
0966          ~CNB_THERMTHRO_MASK_SCLK);
0967 }
0968 
0969 static void sumo_program_dc_hto(struct radeon_device *rdev)
0970 {
0971     u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4);
0972     u32 p, u;
0973     u32 xclk = radeon_get_xclk(rdev);
0974 
0975     r600_calculate_u_and_p(100000,
0976                    xclk, 14, &p, &u);
0977 
0978     cg_sclk_dpm_ctrl_4 &= ~(DC_HDC_MASK | DC_HU_MASK);
0979     cg_sclk_dpm_ctrl_4 |= DC_HDC(p) | DC_HU(u);
0980 
0981     WREG32(CG_SCLK_DPM_CTRL_4, cg_sclk_dpm_ctrl_4);
0982 }
0983 
0984 static void sumo_force_nbp_state(struct radeon_device *rdev,
0985                  struct radeon_ps *rps)
0986 {
0987     struct sumo_power_info *pi = sumo_get_pi(rdev);
0988     struct sumo_ps *new_ps = sumo_get_ps(rps);
0989 
0990     if (!pi->driver_nbps_policy_disable) {
0991         if (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)
0992             WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_NB_PSTATE_1, ~FORCE_NB_PSTATE_1);
0993         else
0994             WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_NB_PSTATE_1);
0995     }
0996 }
0997 
0998 u32 sumo_get_sleep_divider_from_id(u32 id)
0999 {
1000     return 1 << id;
1001 }
1002 
1003 u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
1004                      u32 sclk,
1005                      u32 min_sclk_in_sr)
1006 {
1007     struct sumo_power_info *pi = sumo_get_pi(rdev);
1008     u32 i;
1009     u32 temp;
1010     u32 min = (min_sclk_in_sr > SUMO_MINIMUM_ENGINE_CLOCK) ?
1011         min_sclk_in_sr : SUMO_MINIMUM_ENGINE_CLOCK;
1012 
1013     if (sclk < min)
1014         return 0;
1015 
1016     if (!pi->enable_sclk_ds)
1017         return 0;
1018 
1019     for (i = SUMO_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
1020         temp = sclk / sumo_get_sleep_divider_from_id(i);
1021 
1022         if (temp >= min || i == 0)
1023             break;
1024     }
1025     return i;
1026 }
1027 
1028 static u32 sumo_get_valid_engine_clock(struct radeon_device *rdev,
1029                        u32 lower_limit)
1030 {
1031     struct sumo_power_info *pi = sumo_get_pi(rdev);
1032     u32 i;
1033 
1034     for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) {
1035         if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit)
1036             return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency;
1037     }
1038 
1039     return pi->sys_info.sclk_voltage_mapping_table.entries[pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1].sclk_frequency;
1040 }
1041 
1042 static void sumo_patch_thermal_state(struct radeon_device *rdev,
1043                      struct sumo_ps *ps,
1044                      struct sumo_ps *current_ps)
1045 {
1046     struct sumo_power_info *pi = sumo_get_pi(rdev);
1047     u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1048     u32 current_vddc;
1049     u32 current_sclk;
1050     u32 current_index = 0;
1051 
1052     if (current_ps) {
1053         current_vddc = current_ps->levels[current_index].vddc_index;
1054         current_sclk = current_ps->levels[current_index].sclk;
1055     } else {
1056         current_vddc = pi->boot_pl.vddc_index;
1057         current_sclk = pi->boot_pl.sclk;
1058     }
1059 
1060     ps->levels[0].vddc_index = current_vddc;
1061 
1062     if (ps->levels[0].sclk > current_sclk)
1063         ps->levels[0].sclk = current_sclk;
1064 
1065     ps->levels[0].ss_divider_index =
1066         sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr);
1067 
1068     ps->levels[0].ds_divider_index =
1069         sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1070 
1071     if (ps->levels[0].ds_divider_index > ps->levels[0].ss_divider_index + 1)
1072         ps->levels[0].ds_divider_index = ps->levels[0].ss_divider_index + 1;
1073 
1074     if (ps->levels[0].ss_divider_index == ps->levels[0].ds_divider_index) {
1075         if (ps->levels[0].ss_divider_index > 1)
1076             ps->levels[0].ss_divider_index = ps->levels[0].ss_divider_index - 1;
1077     }
1078 
1079     if (ps->levels[0].ss_divider_index == 0)
1080         ps->levels[0].ds_divider_index = 0;
1081 
1082     if (ps->levels[0].ds_divider_index == 0)
1083         ps->levels[0].ss_divider_index = 0;
1084 }
1085 
1086 static void sumo_apply_state_adjust_rules(struct radeon_device *rdev,
1087                       struct radeon_ps *new_rps,
1088                       struct radeon_ps *old_rps)
1089 {
1090     struct sumo_ps *ps = sumo_get_ps(new_rps);
1091     struct sumo_ps *current_ps = sumo_get_ps(old_rps);
1092     struct sumo_power_info *pi = sumo_get_pi(rdev);
1093     u32 min_voltage = 0; /* ??? */
1094     u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */
1095     u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1096     u32 i;
1097 
1098     if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1099         return sumo_patch_thermal_state(rdev, ps, current_ps);
1100 
1101     if (pi->enable_boost) {
1102         if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE)
1103             ps->flags |= SUMO_POWERSTATE_FLAGS_BOOST_STATE;
1104     }
1105 
1106     if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) ||
1107         (new_rps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) ||
1108         (new_rps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE))
1109         ps->flags |= SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE;
1110 
1111     for (i = 0; i < ps->num_levels; i++) {
1112         if (ps->levels[i].vddc_index < min_voltage)
1113             ps->levels[i].vddc_index = min_voltage;
1114 
1115         if (ps->levels[i].sclk < min_sclk)
1116             ps->levels[i].sclk =
1117                 sumo_get_valid_engine_clock(rdev, min_sclk);
1118 
1119         ps->levels[i].ss_divider_index =
1120             sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr);
1121 
1122         ps->levels[i].ds_divider_index =
1123             sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1124 
1125         if (ps->levels[i].ds_divider_index > ps->levels[i].ss_divider_index + 1)
1126             ps->levels[i].ds_divider_index = ps->levels[i].ss_divider_index + 1;
1127 
1128         if (ps->levels[i].ss_divider_index == ps->levels[i].ds_divider_index) {
1129             if (ps->levels[i].ss_divider_index > 1)
1130                 ps->levels[i].ss_divider_index = ps->levels[i].ss_divider_index - 1;
1131         }
1132 
1133         if (ps->levels[i].ss_divider_index == 0)
1134             ps->levels[i].ds_divider_index = 0;
1135 
1136         if (ps->levels[i].ds_divider_index == 0)
1137             ps->levels[i].ss_divider_index = 0;
1138 
1139         if (ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)
1140             ps->levels[i].allow_gnb_slow = 1;
1141         else if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) ||
1142              (new_rps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC))
1143             ps->levels[i].allow_gnb_slow = 0;
1144         else if (i == ps->num_levels - 1)
1145             ps->levels[i].allow_gnb_slow = 0;
1146         else
1147             ps->levels[i].allow_gnb_slow = 1;
1148     }
1149 }
1150 
1151 static void sumo_cleanup_asic(struct radeon_device *rdev)
1152 {
1153     sumo_take_smu_control(rdev, false);
1154 }
1155 
1156 static int sumo_set_thermal_temperature_range(struct radeon_device *rdev,
1157                           int min_temp, int max_temp)
1158 {
1159     int low_temp = 0 * 1000;
1160     int high_temp = 255 * 1000;
1161 
1162     if (low_temp < min_temp)
1163         low_temp = min_temp;
1164     if (high_temp > max_temp)
1165         high_temp = max_temp;
1166     if (high_temp < low_temp) {
1167         DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
1168         return -EINVAL;
1169     }
1170 
1171     WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK);
1172     WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK);
1173 
1174     rdev->pm.dpm.thermal.min_temp = low_temp;
1175     rdev->pm.dpm.thermal.max_temp = high_temp;
1176 
1177     return 0;
1178 }
1179 
1180 static void sumo_update_current_ps(struct radeon_device *rdev,
1181                    struct radeon_ps *rps)
1182 {
1183     struct sumo_ps *new_ps = sumo_get_ps(rps);
1184     struct sumo_power_info *pi = sumo_get_pi(rdev);
1185 
1186     pi->current_rps = *rps;
1187     pi->current_ps = *new_ps;
1188     pi->current_rps.ps_priv = &pi->current_ps;
1189 }
1190 
1191 static void sumo_update_requested_ps(struct radeon_device *rdev,
1192                      struct radeon_ps *rps)
1193 {
1194     struct sumo_ps *new_ps = sumo_get_ps(rps);
1195     struct sumo_power_info *pi = sumo_get_pi(rdev);
1196 
1197     pi->requested_rps = *rps;
1198     pi->requested_ps = *new_ps;
1199     pi->requested_rps.ps_priv = &pi->requested_ps;
1200 }
1201 
1202 int sumo_dpm_enable(struct radeon_device *rdev)
1203 {
1204     struct sumo_power_info *pi = sumo_get_pi(rdev);
1205 
1206     if (sumo_dpm_enabled(rdev))
1207         return -EINVAL;
1208 
1209     sumo_program_bootup_state(rdev);
1210     sumo_init_bsp(rdev);
1211     sumo_reset_am(rdev);
1212     sumo_program_tp(rdev);
1213     sumo_program_bootup_at(rdev);
1214     sumo_start_am(rdev);
1215     if (pi->enable_auto_thermal_throttling) {
1216         sumo_program_ttp(rdev);
1217         sumo_program_ttt(rdev);
1218     }
1219     sumo_program_dc_hto(rdev);
1220     sumo_program_power_level_enter_state(rdev);
1221     sumo_enable_voltage_scaling(rdev, true);
1222     sumo_program_sstp(rdev);
1223     sumo_program_vc(rdev, SUMO_VRC_DFLT);
1224     sumo_override_cnb_thermal_events(rdev);
1225     sumo_start_dpm(rdev);
1226     sumo_wait_for_level_0(rdev);
1227     if (pi->enable_sclk_ds)
1228         sumo_enable_sclk_ds(rdev, true);
1229     if (pi->enable_boost)
1230         sumo_enable_boost_timer(rdev);
1231 
1232     sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1233 
1234     return 0;
1235 }
1236 
1237 int sumo_dpm_late_enable(struct radeon_device *rdev)
1238 {
1239     int ret;
1240 
1241     ret = sumo_enable_clock_power_gating(rdev);
1242     if (ret)
1243         return ret;
1244 
1245     if (rdev->irq.installed &&
1246         r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1247         ret = sumo_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1248         if (ret)
1249             return ret;
1250         rdev->irq.dpm_thermal = true;
1251         radeon_irq_set(rdev);
1252     }
1253 
1254     return 0;
1255 }
1256 
1257 void sumo_dpm_disable(struct radeon_device *rdev)
1258 {
1259     struct sumo_power_info *pi = sumo_get_pi(rdev);
1260 
1261     if (!sumo_dpm_enabled(rdev))
1262         return;
1263     sumo_disable_clock_power_gating(rdev);
1264     if (pi->enable_sclk_ds)
1265         sumo_enable_sclk_ds(rdev, false);
1266     sumo_clear_vc(rdev);
1267     sumo_wait_for_level_0(rdev);
1268     sumo_stop_dpm(rdev);
1269     sumo_enable_voltage_scaling(rdev, false);
1270 
1271     if (rdev->irq.installed &&
1272         r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1273         rdev->irq.dpm_thermal = false;
1274         radeon_irq_set(rdev);
1275     }
1276 
1277     sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1278 }
1279 
1280 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev)
1281 {
1282     struct sumo_power_info *pi = sumo_get_pi(rdev);
1283     struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1284     struct radeon_ps *new_ps = &requested_ps;
1285 
1286     sumo_update_requested_ps(rdev, new_ps);
1287 
1288     if (pi->enable_dynamic_patch_ps)
1289         sumo_apply_state_adjust_rules(rdev,
1290                           &pi->requested_rps,
1291                           &pi->current_rps);
1292 
1293     return 0;
1294 }
1295 
1296 int sumo_dpm_set_power_state(struct radeon_device *rdev)
1297 {
1298     struct sumo_power_info *pi = sumo_get_pi(rdev);
1299     struct radeon_ps *new_ps = &pi->requested_rps;
1300     struct radeon_ps *old_ps = &pi->current_rps;
1301 
1302     if (pi->enable_dpm)
1303         sumo_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
1304     if (pi->enable_boost) {
1305         sumo_enable_boost(rdev, new_ps, false);
1306         sumo_patch_boost_state(rdev, new_ps);
1307     }
1308     if (pi->enable_dpm) {
1309         sumo_pre_notify_alt_vddnb_change(rdev, new_ps, old_ps);
1310         sumo_enable_power_level_0(rdev);
1311         sumo_set_forced_level_0(rdev);
1312         sumo_set_forced_mode_enabled(rdev);
1313         sumo_wait_for_level_0(rdev);
1314         sumo_program_power_levels_0_to_n(rdev, new_ps, old_ps);
1315         sumo_program_wl(rdev, new_ps);
1316         sumo_program_bsp(rdev, new_ps);
1317         sumo_program_at(rdev, new_ps);
1318         sumo_force_nbp_state(rdev, new_ps);
1319         sumo_set_forced_mode_disabled(rdev);
1320         sumo_set_forced_mode_enabled(rdev);
1321         sumo_set_forced_mode_disabled(rdev);
1322         sumo_post_notify_alt_vddnb_change(rdev, new_ps, old_ps);
1323     }
1324     if (pi->enable_boost)
1325         sumo_enable_boost(rdev, new_ps, true);
1326     if (pi->enable_dpm)
1327         sumo_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
1328 
1329     return 0;
1330 }
1331 
1332 void sumo_dpm_post_set_power_state(struct radeon_device *rdev)
1333 {
1334     struct sumo_power_info *pi = sumo_get_pi(rdev);
1335     struct radeon_ps *new_ps = &pi->requested_rps;
1336 
1337     sumo_update_current_ps(rdev, new_ps);
1338 }
1339 
1340 #if 0
1341 void sumo_dpm_reset_asic(struct radeon_device *rdev)
1342 {
1343     sumo_program_bootup_state(rdev);
1344     sumo_enable_power_level_0(rdev);
1345     sumo_set_forced_level_0(rdev);
1346     sumo_set_forced_mode_enabled(rdev);
1347     sumo_wait_for_level_0(rdev);
1348     sumo_set_forced_mode_disabled(rdev);
1349     sumo_set_forced_mode_enabled(rdev);
1350     sumo_set_forced_mode_disabled(rdev);
1351 }
1352 #endif
1353 
1354 void sumo_dpm_setup_asic(struct radeon_device *rdev)
1355 {
1356     struct sumo_power_info *pi = sumo_get_pi(rdev);
1357 
1358     sumo_initialize_m3_arb(rdev);
1359     pi->fw_version = sumo_get_running_fw_version(rdev);
1360     DRM_INFO("Found smc ucode version: 0x%08x\n", pi->fw_version);
1361     sumo_program_acpi_power_level(rdev);
1362     sumo_enable_acpi_pm(rdev);
1363     sumo_take_smu_control(rdev, true);
1364 }
1365 
1366 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev)
1367 {
1368 
1369 }
1370 
1371 union power_info {
1372     struct _ATOM_POWERPLAY_INFO info;
1373     struct _ATOM_POWERPLAY_INFO_V2 info_2;
1374     struct _ATOM_POWERPLAY_INFO_V3 info_3;
1375     struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1376     struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1377     struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1378 };
1379 
1380 union pplib_clock_info {
1381     struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1382     struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1383     struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1384     struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1385 };
1386 
1387 union pplib_power_state {
1388     struct _ATOM_PPLIB_STATE v1;
1389     struct _ATOM_PPLIB_STATE_V2 v2;
1390 };
1391 
1392 static void sumo_patch_boot_state(struct radeon_device *rdev,
1393                   struct sumo_ps *ps)
1394 {
1395     struct sumo_power_info *pi = sumo_get_pi(rdev);
1396 
1397     ps->num_levels = 1;
1398     ps->flags = 0;
1399     ps->levels[0] = pi->boot_pl;
1400 }
1401 
1402 static void sumo_parse_pplib_non_clock_info(struct radeon_device *rdev,
1403                         struct radeon_ps *rps,
1404                         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
1405                         u8 table_rev)
1406 {
1407     struct sumo_ps *ps = sumo_get_ps(rps);
1408 
1409     rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1410     rps->class = le16_to_cpu(non_clock_info->usClassification);
1411     rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
1412 
1413     if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
1414         rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
1415         rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
1416     } else {
1417         rps->vclk = 0;
1418         rps->dclk = 0;
1419     }
1420 
1421     if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1422         rdev->pm.dpm.boot_ps = rps;
1423         sumo_patch_boot_state(rdev, ps);
1424     }
1425     if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
1426         rdev->pm.dpm.uvd_ps = rps;
1427 }
1428 
1429 static void sumo_parse_pplib_clock_info(struct radeon_device *rdev,
1430                     struct radeon_ps *rps, int index,
1431                     union pplib_clock_info *clock_info)
1432 {
1433     struct sumo_power_info *pi = sumo_get_pi(rdev);
1434     struct sumo_ps *ps = sumo_get_ps(rps);
1435     struct sumo_pl *pl = &ps->levels[index];
1436     u32 sclk;
1437 
1438     sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
1439     sclk |= clock_info->sumo.ucEngineClockHigh << 16;
1440     pl->sclk = sclk;
1441     pl->vddc_index = clock_info->sumo.vddcIndex;
1442     pl->sclk_dpm_tdp_limit = clock_info->sumo.tdpLimit;
1443 
1444     ps->num_levels = index + 1;
1445 
1446     if (pi->enable_sclk_ds) {
1447         pl->ds_divider_index = 5;
1448         pl->ss_divider_index = 4;
1449     }
1450 }
1451 
1452 static int sumo_parse_power_table(struct radeon_device *rdev)
1453 {
1454     struct radeon_mode_info *mode_info = &rdev->mode_info;
1455     struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1456     union pplib_power_state *power_state;
1457     int i, j, k, non_clock_array_index, clock_array_index;
1458     union pplib_clock_info *clock_info;
1459     struct _StateArray *state_array;
1460     struct _ClockInfoArray *clock_info_array;
1461     struct _NonClockInfoArray *non_clock_info_array;
1462     union power_info *power_info;
1463     int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1464     u16 data_offset;
1465     u8 frev, crev;
1466     u8 *power_state_offset;
1467     struct sumo_ps *ps;
1468 
1469     if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1470                    &frev, &crev, &data_offset))
1471         return -EINVAL;
1472     power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1473 
1474     state_array = (struct _StateArray *)
1475         (mode_info->atom_context->bios + data_offset +
1476          le16_to_cpu(power_info->pplib.usStateArrayOffset));
1477     clock_info_array = (struct _ClockInfoArray *)
1478         (mode_info->atom_context->bios + data_offset +
1479          le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
1480     non_clock_info_array = (struct _NonClockInfoArray *)
1481         (mode_info->atom_context->bios + data_offset +
1482          le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
1483 
1484     rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
1485                   sizeof(struct radeon_ps),
1486                   GFP_KERNEL);
1487     if (!rdev->pm.dpm.ps)
1488         return -ENOMEM;
1489     power_state_offset = (u8 *)state_array->states;
1490     for (i = 0; i < state_array->ucNumEntries; i++) {
1491         u8 *idx;
1492         power_state = (union pplib_power_state *)power_state_offset;
1493         non_clock_array_index = power_state->v2.nonClockInfoIndex;
1494         non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1495             &non_clock_info_array->nonClockInfo[non_clock_array_index];
1496         if (!rdev->pm.power_state[i].clock_info)
1497             return -EINVAL;
1498         ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL);
1499         if (ps == NULL) {
1500             kfree(rdev->pm.dpm.ps);
1501             return -ENOMEM;
1502         }
1503         rdev->pm.dpm.ps[i].ps_priv = ps;
1504         k = 0;
1505         idx = (u8 *)&power_state->v2.clockInfoIndex[0];
1506         for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
1507             clock_array_index = idx[j];
1508             if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
1509                 break;
1510 
1511             clock_info = (union pplib_clock_info *)
1512                 ((u8 *)&clock_info_array->clockInfo[0] +
1513                  (clock_array_index * clock_info_array->ucEntrySize));
1514             sumo_parse_pplib_clock_info(rdev,
1515                             &rdev->pm.dpm.ps[i], k,
1516                             clock_info);
1517             k++;
1518         }
1519         sumo_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
1520                         non_clock_info,
1521                         non_clock_info_array->ucEntrySize);
1522         power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
1523     }
1524     rdev->pm.dpm.num_ps = state_array->ucNumEntries;
1525     return 0;
1526 }
1527 
1528 u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,
1529                   struct sumo_vid_mapping_table *vid_mapping_table,
1530                   u32 vid_2bit)
1531 {
1532     u32 i;
1533 
1534     for (i = 0; i < vid_mapping_table->num_entries; i++) {
1535         if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
1536             return vid_mapping_table->entries[i].vid_7bit;
1537     }
1538 
1539     return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
1540 }
1541 
1542 #if 0
1543 u32 sumo_convert_vid7_to_vid2(struct radeon_device *rdev,
1544                   struct sumo_vid_mapping_table *vid_mapping_table,
1545                   u32 vid_7bit)
1546 {
1547     u32 i;
1548 
1549     for (i = 0; i < vid_mapping_table->num_entries; i++) {
1550         if (vid_mapping_table->entries[i].vid_7bit == vid_7bit)
1551             return vid_mapping_table->entries[i].vid_2bit;
1552     }
1553 
1554     return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit;
1555 }
1556 #endif
1557 
1558 static u16 sumo_convert_voltage_index_to_value(struct radeon_device *rdev,
1559                            u32 vid_2bit)
1560 {
1561     struct sumo_power_info *pi = sumo_get_pi(rdev);
1562     u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit);
1563 
1564     if (vid_7bit > 0x7C)
1565         return 0;
1566 
1567     return (15500 - vid_7bit * 125 + 5) / 10;
1568 }
1569 
1570 static void sumo_construct_display_voltage_mapping_table(struct radeon_device *rdev,
1571                              struct sumo_disp_clock_voltage_mapping_table *disp_clk_voltage_mapping_table,
1572                              ATOM_CLK_VOLT_CAPABILITY *table)
1573 {
1574     u32 i;
1575 
1576     for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
1577         if (table[i].ulMaximumSupportedCLK == 0)
1578             break;
1579 
1580         disp_clk_voltage_mapping_table->display_clock_frequency[i] =
1581             table[i].ulMaximumSupportedCLK;
1582     }
1583 
1584     disp_clk_voltage_mapping_table->num_max_voltage_levels = i;
1585 
1586     if (disp_clk_voltage_mapping_table->num_max_voltage_levels == 0) {
1587         disp_clk_voltage_mapping_table->display_clock_frequency[0] = 80000;
1588         disp_clk_voltage_mapping_table->num_max_voltage_levels = 1;
1589     }
1590 }
1591 
1592 void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev,
1593                            struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
1594                            ATOM_AVAILABLE_SCLK_LIST *table)
1595 {
1596     u32 i;
1597     u32 n = 0;
1598     u32 prev_sclk = 0;
1599 
1600     for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
1601         if (table[i].ulSupportedSCLK > prev_sclk) {
1602             sclk_voltage_mapping_table->entries[n].sclk_frequency =
1603                 table[i].ulSupportedSCLK;
1604             sclk_voltage_mapping_table->entries[n].vid_2bit =
1605                 table[i].usVoltageIndex;
1606             prev_sclk = table[i].ulSupportedSCLK;
1607             n++;
1608         }
1609     }
1610 
1611     sclk_voltage_mapping_table->num_max_dpm_entries = n;
1612 }
1613 
1614 void sumo_construct_vid_mapping_table(struct radeon_device *rdev,
1615                       struct sumo_vid_mapping_table *vid_mapping_table,
1616                       ATOM_AVAILABLE_SCLK_LIST *table)
1617 {
1618     u32 i, j;
1619 
1620     for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
1621         if (table[i].ulSupportedSCLK != 0) {
1622             vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
1623                 table[i].usVoltageID;
1624             vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
1625                 table[i].usVoltageIndex;
1626         }
1627     }
1628 
1629     for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
1630         if (vid_mapping_table->entries[i].vid_7bit == 0) {
1631             for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) {
1632                 if (vid_mapping_table->entries[j].vid_7bit != 0) {
1633                     vid_mapping_table->entries[i] =
1634                         vid_mapping_table->entries[j];
1635                     vid_mapping_table->entries[j].vid_7bit = 0;
1636                     break;
1637                 }
1638             }
1639 
1640             if (j == SUMO_MAX_NUMBER_VOLTAGES)
1641                 break;
1642         }
1643     }
1644 
1645     vid_mapping_table->num_entries = i;
1646 }
1647 
1648 union igp_info {
1649     struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1650     struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1651     struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
1652     struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1653 };
1654 
1655 static int sumo_parse_sys_info_table(struct radeon_device *rdev)
1656 {
1657     struct sumo_power_info *pi = sumo_get_pi(rdev);
1658     struct radeon_mode_info *mode_info = &rdev->mode_info;
1659     int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1660     union igp_info *igp_info;
1661     u8 frev, crev;
1662     u16 data_offset;
1663     int i;
1664 
1665     if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1666                    &frev, &crev, &data_offset)) {
1667         igp_info = (union igp_info *)(mode_info->atom_context->bios +
1668                           data_offset);
1669 
1670         if (crev != 6) {
1671             DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1672             return -EINVAL;
1673         }
1674         pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_6.ulBootUpEngineClock);
1675         pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_6.ulMinEngineClock);
1676         pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_6.ulBootUpUMAClock);
1677         pi->sys_info.bootup_nb_voltage_index =
1678             le16_to_cpu(igp_info->info_6.usBootUpNBVoltage);
1679         if (igp_info->info_6.ucHtcTmpLmt == 0)
1680             pi->sys_info.htc_tmp_lmt = 203;
1681         else
1682             pi->sys_info.htc_tmp_lmt = igp_info->info_6.ucHtcTmpLmt;
1683         if (igp_info->info_6.ucHtcHystLmt == 0)
1684             pi->sys_info.htc_hyst_lmt = 5;
1685         else
1686             pi->sys_info.htc_hyst_lmt = igp_info->info_6.ucHtcHystLmt;
1687         if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
1688             DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
1689         }
1690         for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++) {
1691             pi->sys_info.csr_m3_arb_cntl_default[i] =
1692                 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_DEFAULT[i]);
1693             pi->sys_info.csr_m3_arb_cntl_uvd[i] =
1694                 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_UVD[i]);
1695             pi->sys_info.csr_m3_arb_cntl_fs3d[i] =
1696                 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_FS3D[i]);
1697         }
1698         pi->sys_info.sclk_dpm_boost_margin =
1699             le32_to_cpu(igp_info->info_6.SclkDpmBoostMargin);
1700         pi->sys_info.sclk_dpm_throttle_margin =
1701             le32_to_cpu(igp_info->info_6.SclkDpmThrottleMargin);
1702         pi->sys_info.sclk_dpm_tdp_limit_pg =
1703             le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitPG);
1704         pi->sys_info.gnb_tdp_limit = le16_to_cpu(igp_info->info_6.GnbTdpLimit);
1705         pi->sys_info.sclk_dpm_tdp_limit_boost =
1706             le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitBoost);
1707         pi->sys_info.boost_sclk = le32_to_cpu(igp_info->info_6.ulBoostEngineCLock);
1708         pi->sys_info.boost_vid_2bit = igp_info->info_6.ulBoostVid_2bit;
1709         if (igp_info->info_6.EnableBoost)
1710             pi->sys_info.enable_boost = true;
1711         else
1712             pi->sys_info.enable_boost = false;
1713         sumo_construct_display_voltage_mapping_table(rdev,
1714                                  &pi->sys_info.disp_clk_voltage_mapping_table,
1715                                  igp_info->info_6.sDISPCLK_Voltage);
1716         sumo_construct_sclk_voltage_mapping_table(rdev,
1717                               &pi->sys_info.sclk_voltage_mapping_table,
1718                               igp_info->info_6.sAvail_SCLK);
1719         sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table,
1720                          igp_info->info_6.sAvail_SCLK);
1721 
1722     }
1723     return 0;
1724 }
1725 
1726 static void sumo_construct_boot_and_acpi_state(struct radeon_device *rdev)
1727 {
1728     struct sumo_power_info *pi = sumo_get_pi(rdev);
1729 
1730     pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
1731     pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
1732     pi->boot_pl.ds_divider_index = 0;
1733     pi->boot_pl.ss_divider_index = 0;
1734     pi->boot_pl.allow_gnb_slow = 1;
1735     pi->acpi_pl = pi->boot_pl;
1736     pi->current_ps.num_levels = 1;
1737     pi->current_ps.levels[0] = pi->boot_pl;
1738 }
1739 
1740 int sumo_dpm_init(struct radeon_device *rdev)
1741 {
1742     struct sumo_power_info *pi;
1743     u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;
1744     int ret;
1745 
1746     pi = kzalloc(sizeof(struct sumo_power_info), GFP_KERNEL);
1747     if (pi == NULL)
1748         return -ENOMEM;
1749     rdev->pm.dpm.priv = pi;
1750 
1751     pi->driver_nbps_policy_disable = false;
1752     if ((rdev->family == CHIP_PALM) && (hw_rev < 3))
1753         pi->disable_gfx_power_gating_in_uvd = true;
1754     else
1755         pi->disable_gfx_power_gating_in_uvd = false;
1756     pi->enable_alt_vddnb = true;
1757     pi->enable_sclk_ds = true;
1758     pi->enable_dynamic_m3_arbiter = false;
1759     pi->enable_dynamic_patch_ps = true;
1760     /* Some PALM chips don't seem to properly ungate gfx when UVD is in use;
1761      * for now just disable gfx PG.
1762      */
1763     if (rdev->family == CHIP_PALM)
1764         pi->enable_gfx_power_gating = false;
1765     else
1766         pi->enable_gfx_power_gating = true;
1767     pi->enable_gfx_clock_gating = true;
1768     pi->enable_mg_clock_gating = true;
1769     pi->enable_auto_thermal_throttling = true;
1770 
1771     ret = sumo_parse_sys_info_table(rdev);
1772     if (ret)
1773         return ret;
1774 
1775     sumo_construct_boot_and_acpi_state(rdev);
1776 
1777     ret = r600_get_platform_caps(rdev);
1778     if (ret)
1779         return ret;
1780 
1781     ret = sumo_parse_power_table(rdev);
1782     if (ret)
1783         return ret;
1784 
1785     pi->pasi = CYPRESS_HASI_DFLT;
1786     pi->asi = RV770_ASI_DFLT;
1787     pi->thermal_auto_throttling = pi->sys_info.htc_tmp_lmt;
1788     pi->enable_boost = pi->sys_info.enable_boost;
1789     pi->enable_dpm = true;
1790 
1791     return 0;
1792 }
1793 
1794 void sumo_dpm_print_power_state(struct radeon_device *rdev,
1795                 struct radeon_ps *rps)
1796 {
1797     int i;
1798     struct sumo_ps *ps = sumo_get_ps(rps);
1799 
1800     r600_dpm_print_class_info(rps->class, rps->class2);
1801     r600_dpm_print_cap_info(rps->caps);
1802     printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1803     for (i = 0; i < ps->num_levels; i++) {
1804         struct sumo_pl *pl = &ps->levels[i];
1805         printk("\t\tpower level %d    sclk: %u vddc: %u\n",
1806                i, pl->sclk,
1807                sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1808     }
1809     r600_dpm_print_ps_status(rdev, rps);
1810 }
1811 
1812 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
1813                               struct seq_file *m)
1814 {
1815     struct sumo_power_info *pi = sumo_get_pi(rdev);
1816     struct radeon_ps *rps = &pi->current_rps;
1817     struct sumo_ps *ps = sumo_get_ps(rps);
1818     struct sumo_pl *pl;
1819     u32 current_index =
1820         (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>
1821         CURR_INDEX_SHIFT;
1822 
1823     if (current_index == BOOST_DPM_LEVEL) {
1824         pl = &pi->boost_pl;
1825         seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1826         seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
1827                current_index, pl->sclk,
1828                sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1829     } else if (current_index >= ps->num_levels) {
1830         seq_printf(m, "invalid dpm profile %d\n", current_index);
1831     } else {
1832         pl = &ps->levels[current_index];
1833         seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1834         seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
1835                current_index, pl->sclk,
1836                sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1837     }
1838 }
1839 
1840 u32 sumo_dpm_get_current_sclk(struct radeon_device *rdev)
1841 {
1842     struct sumo_power_info *pi = sumo_get_pi(rdev);
1843     struct radeon_ps *rps = &pi->current_rps;
1844     struct sumo_ps *ps = sumo_get_ps(rps);
1845     struct sumo_pl *pl;
1846     u32 current_index =
1847         (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>
1848         CURR_INDEX_SHIFT;
1849 
1850     if (current_index == BOOST_DPM_LEVEL) {
1851         pl = &pi->boost_pl;
1852         return pl->sclk;
1853     } else if (current_index >= ps->num_levels) {
1854         return 0;
1855     } else {
1856         pl = &ps->levels[current_index];
1857         return pl->sclk;
1858     }
1859 }
1860 
1861 u32 sumo_dpm_get_current_mclk(struct radeon_device *rdev)
1862 {
1863     struct sumo_power_info *pi = sumo_get_pi(rdev);
1864 
1865     return pi->sys_info.bootup_uma_clk;
1866 }
1867 
1868 u16 sumo_dpm_get_current_vddc(struct radeon_device *rdev)
1869 {
1870     struct sumo_power_info *pi = sumo_get_pi(rdev);
1871     struct radeon_ps *rps = &pi->current_rps;
1872     struct sumo_ps *ps = sumo_get_ps(rps);
1873     struct sumo_pl *pl;
1874     u32 current_index =
1875         (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>
1876         CURR_INDEX_SHIFT;
1877 
1878     if (current_index == BOOST_DPM_LEVEL) {
1879         pl = &pi->boost_pl;
1880     } else if (current_index >= ps->num_levels) {
1881         return 0;
1882     } else {
1883         pl = &ps->levels[current_index];
1884     }
1885     return sumo_convert_voltage_index_to_value(rdev, pl->vddc_index);
1886 }
1887 
1888 void sumo_dpm_fini(struct radeon_device *rdev)
1889 {
1890     int i;
1891 
1892     sumo_cleanup_asic(rdev); /* ??? */
1893 
1894     for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1895         kfree(rdev->pm.dpm.ps[i].ps_priv);
1896     }
1897     kfree(rdev->pm.dpm.ps);
1898     kfree(rdev->pm.dpm.priv);
1899 }
1900 
1901 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low)
1902 {
1903     struct sumo_power_info *pi = sumo_get_pi(rdev);
1904     struct sumo_ps *requested_state = sumo_get_ps(&pi->requested_rps);
1905 
1906     if (low)
1907         return requested_state->levels[0].sclk;
1908     else
1909         return requested_state->levels[requested_state->num_levels - 1].sclk;
1910 }
1911 
1912 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low)
1913 {
1914     struct sumo_power_info *pi = sumo_get_pi(rdev);
1915 
1916     return pi->sys_info.bootup_uma_clk;
1917 }
1918 
1919 int sumo_dpm_force_performance_level(struct radeon_device *rdev,
1920                      enum radeon_dpm_forced_level level)
1921 {
1922     struct sumo_power_info *pi = sumo_get_pi(rdev);
1923     struct radeon_ps *rps = &pi->current_rps;
1924     struct sumo_ps *ps = sumo_get_ps(rps);
1925     int i;
1926 
1927     if (ps->num_levels <= 1)
1928         return 0;
1929 
1930     if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1931         if (pi->enable_boost)
1932             sumo_enable_boost(rdev, rps, false);
1933         sumo_power_level_enable(rdev, ps->num_levels - 1, true);
1934         sumo_set_forced_level(rdev, ps->num_levels - 1);
1935         sumo_set_forced_mode_enabled(rdev);
1936         for (i = 0; i < ps->num_levels - 1; i++) {
1937             sumo_power_level_enable(rdev, i, false);
1938         }
1939         sumo_set_forced_mode(rdev, false);
1940         sumo_set_forced_mode_enabled(rdev);
1941         sumo_set_forced_mode(rdev, false);
1942     } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1943         if (pi->enable_boost)
1944             sumo_enable_boost(rdev, rps, false);
1945         sumo_power_level_enable(rdev, 0, true);
1946         sumo_set_forced_level(rdev, 0);
1947         sumo_set_forced_mode_enabled(rdev);
1948         for (i = 1; i < ps->num_levels; i++) {
1949             sumo_power_level_enable(rdev, i, false);
1950         }
1951         sumo_set_forced_mode(rdev, false);
1952         sumo_set_forced_mode_enabled(rdev);
1953         sumo_set_forced_mode(rdev, false);
1954     } else {
1955         for (i = 0; i < ps->num_levels; i++) {
1956             sumo_power_level_enable(rdev, i, true);
1957         }
1958         if (pi->enable_boost)
1959             sumo_enable_boost(rdev, rps, true);
1960     }
1961 
1962     rdev->pm.dpm.forced_level = level;
1963 
1964     return 0;
1965 }
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