drm/radeon/smu7_discrete.h

0001 /*
0002  * Copyright 2013 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef SMU7_DISCRETE_H
0025 #define SMU7_DISCRETE_H
0026
0027 #include "smu7.h"
0028
0029 #pragma pack(push, 1)
0030
0031 #define SMU7_DTE_ITERATIONS 5
0032 #define SMU7_DTE_SOURCES 3
0033 #define SMU7_DTE_SINKS 1
0034 #define SMU7_NUM_CPU_TES 0
0035 #define SMU7_NUM_GPU_TES 1
0036 #define SMU7_NUM_NON_TES 2
0037
0038 struct SMU7_SoftRegisters
0039 {
0040     uint32_t        RefClockFrequency;
0041     uint32_t        PmTimerP;
0042     uint32_t        FeatureEnables;
0043     uint32_t        PreVBlankGap;
0044     uint32_t        VBlankTimeout;
0045     uint32_t        TrainTimeGap;
0046
0047     uint32_t        MvddSwitchTime;
0048     uint32_t        LongestAcpiTrainTime;
0049     uint32_t        AcpiDelay;
0050     uint32_t        G5TrainTime;
0051     uint32_t        DelayMpllPwron;
0052     uint32_t        VoltageChangeTimeout;
0053     uint32_t        HandshakeDisables;
0054
0055     uint8_t         DisplayPhy1Config;
0056     uint8_t         DisplayPhy2Config;
0057     uint8_t         DisplayPhy3Config;
0058     uint8_t         DisplayPhy4Config;
0059
0060     uint8_t         DisplayPhy5Config;
0061     uint8_t         DisplayPhy6Config;
0062     uint8_t         DisplayPhy7Config;
0063     uint8_t         DisplayPhy8Config;
0064
0065     uint32_t        AverageGraphicsA;
0066     uint32_t        AverageMemoryA;
0067     uint32_t        AverageGioA;
0068
0069     uint8_t         SClkDpmEnabledLevels;
0070     uint8_t         MClkDpmEnabledLevels;
0071     uint8_t         LClkDpmEnabledLevels;
0072     uint8_t         PCIeDpmEnabledLevels;
0073
0074     uint8_t         UVDDpmEnabledLevels;
0075     uint8_t         SAMUDpmEnabledLevels;
0076     uint8_t         ACPDpmEnabledLevels;
0077     uint8_t         VCEDpmEnabledLevels;
0078
0079     uint32_t        DRAM_LOG_ADDR_H;
0080     uint32_t        DRAM_LOG_ADDR_L;
0081     uint32_t        DRAM_LOG_PHY_ADDR_H;
0082     uint32_t        DRAM_LOG_PHY_ADDR_L;
0083     uint32_t        DRAM_LOG_BUFF_SIZE;
0084     uint32_t        UlvEnterC;
0085     uint32_t        UlvTime;
0086     uint32_t        Reserved[3];
0087
0088 };
0089
0090 typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;
0091
0092 struct SMU7_Discrete_VoltageLevel
0093 {
0094     uint16_t    Voltage;
0095     uint16_t    StdVoltageHiSidd;
0096     uint16_t    StdVoltageLoSidd;
0097     uint8_t     Smio;
0098     uint8_t     padding;
0099 };
0100
0101 typedef struct SMU7_Discrete_VoltageLevel SMU7_Discrete_VoltageLevel;
0102
0103 struct SMU7_Discrete_GraphicsLevel
0104 {
0105     uint32_t    Flags;
0106     uint32_t    MinVddc;
0107     uint32_t    MinVddcPhases;
0108
0109     uint32_t    SclkFrequency;
0110
0111     uint8_t     padding1[2];
0112     uint16_t    ActivityLevel;
0113
0114     uint32_t    CgSpllFuncCntl3;
0115     uint32_t    CgSpllFuncCntl4;
0116     uint32_t    SpllSpreadSpectrum;
0117     uint32_t    SpllSpreadSpectrum2;
0118     uint32_t    CcPwrDynRm;
0119     uint32_t    CcPwrDynRm1;
0120     uint8_t     SclkDid;
0121     uint8_t     DisplayWatermark;
0122     uint8_t     EnabledForActivity;
0123     uint8_t     EnabledForThrottle;
0124     uint8_t     UpH;
0125     uint8_t     DownH;
0126     uint8_t     VoltageDownH;
0127     uint8_t     PowerThrottle;
0128     uint8_t     DeepSleepDivId;
0129     uint8_t     padding[3];
0130 };
0131
0132 typedef struct SMU7_Discrete_GraphicsLevel SMU7_Discrete_GraphicsLevel;
0133
0134 struct SMU7_Discrete_ACPILevel
0135 {
0136     uint32_t    Flags;
0137     uint32_t    MinVddc;
0138     uint32_t    MinVddcPhases;
0139     uint32_t    SclkFrequency;
0140     uint8_t     SclkDid;
0141     uint8_t     DisplayWatermark;
0142     uint8_t     DeepSleepDivId;
0143     uint8_t     padding;
0144     uint32_t    CgSpllFuncCntl;
0145     uint32_t    CgSpllFuncCntl2;
0146     uint32_t    CgSpllFuncCntl3;
0147     uint32_t    CgSpllFuncCntl4;
0148     uint32_t    SpllSpreadSpectrum;
0149     uint32_t    SpllSpreadSpectrum2;
0150     uint32_t    CcPwrDynRm;
0151     uint32_t    CcPwrDynRm1;
0152 };
0153
0154 typedef struct SMU7_Discrete_ACPILevel SMU7_Discrete_ACPILevel;
0155
0156 struct SMU7_Discrete_Ulv
0157 {
0158     uint32_t    CcPwrDynRm;
0159     uint32_t    CcPwrDynRm1;
0160     uint16_t    VddcOffset;
0161     uint8_t     VddcOffsetVid;
0162     uint8_t     VddcPhase;
0163     uint32_t    Reserved;
0164 };
0165
0166 typedef struct SMU7_Discrete_Ulv SMU7_Discrete_Ulv;
0167
0168 struct SMU7_Discrete_MemoryLevel
0169 {
0170     uint32_t    MinVddc;
0171     uint32_t    MinVddcPhases;
0172     uint32_t    MinVddci;
0173     uint32_t    MinMvdd;
0174
0175     uint32_t    MclkFrequency;
0176
0177     uint8_t     EdcReadEnable;
0178     uint8_t     EdcWriteEnable;
0179     uint8_t     RttEnable;
0180     uint8_t     StutterEnable;
0181
0182     uint8_t     StrobeEnable;
0183     uint8_t     StrobeRatio;
0184     uint8_t     EnabledForThrottle;
0185     uint8_t     EnabledForActivity;
0186
0187     uint8_t     UpH;
0188     uint8_t     DownH;
0189     uint8_t     VoltageDownH;
0190     uint8_t     padding;
0191
0192     uint16_t    ActivityLevel;
0193     uint8_t     DisplayWatermark;
0194     uint8_t     padding1;
0195
0196     uint32_t    MpllFuncCntl;
0197     uint32_t    MpllFuncCntl_1;
0198     uint32_t    MpllFuncCntl_2;
0199     uint32_t    MpllAdFuncCntl;
0200     uint32_t    MpllDqFuncCntl;
0201     uint32_t    MclkPwrmgtCntl;
0202     uint32_t    DllCntl;
0203     uint32_t    MpllSs1;
0204     uint32_t    MpllSs2;
0205 };
0206
0207 typedef struct SMU7_Discrete_MemoryLevel SMU7_Discrete_MemoryLevel;
0208
0209 struct SMU7_Discrete_LinkLevel
0210 {
0211     uint8_t     PcieGenSpeed;
0212     uint8_t     PcieLaneCount;
0213     uint8_t     EnabledForActivity;
0214     uint8_t     Padding;
0215     uint32_t    DownT;
0216     uint32_t    UpT;
0217     uint32_t    Reserved;
0218 };
0219
0220 typedef struct SMU7_Discrete_LinkLevel SMU7_Discrete_LinkLevel;
0221
0222
0223 struct SMU7_Discrete_MCArbDramTimingTableEntry
0224 {
0225     uint32_t McArbDramTiming;
0226     uint32_t McArbDramTiming2;
0227     uint8_t  McArbBurstTime;
0228     uint8_t  padding[3];
0229 };
0230
0231 typedef struct SMU7_Discrete_MCArbDramTimingTableEntry SMU7_Discrete_MCArbDramTimingTableEntry;
0232
0233 struct SMU7_Discrete_MCArbDramTimingTable
0234 {
0235     SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
0236 };
0237
0238 typedef struct SMU7_Discrete_MCArbDramTimingTable SMU7_Discrete_MCArbDramTimingTable;
0239
0240 struct SMU7_Discrete_UvdLevel
0241 {
0242     uint32_t VclkFrequency;
0243     uint32_t DclkFrequency;
0244     uint16_t MinVddc;
0245     uint8_t  MinVddcPhases;
0246     uint8_t  VclkDivider;
0247     uint8_t  DclkDivider;
0248     uint8_t  padding[3];
0249 };
0250
0251 typedef struct SMU7_Discrete_UvdLevel SMU7_Discrete_UvdLevel;
0252
0253 struct SMU7_Discrete_ExtClkLevel
0254 {
0255     uint32_t Frequency;
0256     uint16_t MinVoltage;
0257     uint8_t  MinPhases;
0258     uint8_t  Divider;
0259 };
0260
0261 typedef struct SMU7_Discrete_ExtClkLevel SMU7_Discrete_ExtClkLevel;
0262
0263 struct SMU7_Discrete_StateInfo
0264 {
0265     uint32_t SclkFrequency;
0266     uint32_t MclkFrequency;
0267     uint32_t VclkFrequency;
0268     uint32_t DclkFrequency;
0269     uint32_t SamclkFrequency;
0270     uint32_t AclkFrequency;
0271     uint32_t EclkFrequency;
0272     uint16_t MvddVoltage;
0273     uint16_t padding16;
0274     uint8_t  DisplayWatermark;
0275     uint8_t  McArbIndex;
0276     uint8_t  McRegIndex;
0277     uint8_t  SeqIndex;
0278     uint8_t  SclkDid;
0279     int8_t   SclkIndex;
0280     int8_t   MclkIndex;
0281     uint8_t  PCIeGen;
0282
0283 };
0284
0285 typedef struct SMU7_Discrete_StateInfo SMU7_Discrete_StateInfo;
0286
0287
0288 struct SMU7_Discrete_DpmTable
0289 {
0290     SMU7_PIDController                  GraphicsPIDController;
0291     SMU7_PIDController                  MemoryPIDController;
0292     SMU7_PIDController                  LinkPIDController;
0293
0294     uint32_t                            SystemFlags;
0295
0296
0297     uint32_t                            SmioMaskVddcVid;
0298     uint32_t                            SmioMaskVddcPhase;
0299     uint32_t                            SmioMaskVddciVid;
0300     uint32_t                            SmioMaskMvddVid;
0301
0302     uint32_t                            VddcLevelCount;
0303     uint32_t                            VddciLevelCount;
0304     uint32_t                            MvddLevelCount;
0305
0306     SMU7_Discrete_VoltageLevel          VddcLevel               [SMU7_MAX_LEVELS_VDDC];
0307 //    SMU7_Discrete_VoltageLevel          VddcStandardReference   [SMU7_MAX_LEVELS_VDDC];
0308     SMU7_Discrete_VoltageLevel          VddciLevel              [SMU7_MAX_LEVELS_VDDCI];
0309     SMU7_Discrete_VoltageLevel          MvddLevel               [SMU7_MAX_LEVELS_MVDD];
0310
0311     uint8_t                             GraphicsDpmLevelCount;
0312     uint8_t                             MemoryDpmLevelCount;
0313     uint8_t                             LinkLevelCount;
0314     uint8_t                             UvdLevelCount;
0315     uint8_t                             VceLevelCount;
0316     uint8_t                             AcpLevelCount;
0317     uint8_t                             SamuLevelCount;
0318     uint8_t                             MasterDeepSleepControl;
0319     uint32_t                            Reserved[5];
0320 //    uint32_t                            SamuDefaultLevel;
0321
0322     SMU7_Discrete_GraphicsLevel         GraphicsLevel           [SMU7_MAX_LEVELS_GRAPHICS];
0323     SMU7_Discrete_MemoryLevel           MemoryACPILevel;
0324     SMU7_Discrete_MemoryLevel           MemoryLevel             [SMU7_MAX_LEVELS_MEMORY];
0325     SMU7_Discrete_LinkLevel             LinkLevel               [SMU7_MAX_LEVELS_LINK];
0326     SMU7_Discrete_ACPILevel             ACPILevel;
0327     SMU7_Discrete_UvdLevel              UvdLevel                [SMU7_MAX_LEVELS_UVD];
0328     SMU7_Discrete_ExtClkLevel           VceLevel                [SMU7_MAX_LEVELS_VCE];
0329     SMU7_Discrete_ExtClkLevel           AcpLevel                [SMU7_MAX_LEVELS_ACP];
0330     SMU7_Discrete_ExtClkLevel           SamuLevel               [SMU7_MAX_LEVELS_SAMU];
0331     SMU7_Discrete_Ulv                   Ulv;
0332
0333     uint32_t                            SclkStepSize;
0334     uint32_t                            Smio                    [SMU7_MAX_ENTRIES_SMIO];
0335
0336     uint8_t                             UvdBootLevel;
0337     uint8_t                             VceBootLevel;
0338     uint8_t                             AcpBootLevel;
0339     uint8_t                             SamuBootLevel;
0340
0341     uint8_t                             UVDInterval;
0342     uint8_t                             VCEInterval;
0343     uint8_t                             ACPInterval;
0344     uint8_t                             SAMUInterval;
0345
0346     uint8_t                             GraphicsBootLevel;
0347     uint8_t                             GraphicsVoltageChangeEnable;
0348     uint8_t                             GraphicsThermThrottleEnable;
0349     uint8_t                             GraphicsInterval;
0350
0351     uint8_t                             VoltageInterval;
0352     uint8_t                             ThermalInterval;
0353     uint16_t                            TemperatureLimitHigh;
0354
0355     uint16_t                            TemperatureLimitLow;
0356     uint8_t                             MemoryBootLevel;
0357     uint8_t                             MemoryVoltageChangeEnable;
0358
0359     uint8_t                             MemoryInterval;
0360     uint8_t                             MemoryThermThrottleEnable;
0361     uint16_t                            VddcVddciDelta;
0362
0363     uint16_t                            VoltageResponseTime;
0364     uint16_t                            PhaseResponseTime;
0365
0366     uint8_t                             PCIeBootLinkLevel;
0367     uint8_t                             PCIeGenInterval;
0368     uint8_t                             DTEInterval;
0369     uint8_t                             DTEMode;
0370
0371     uint8_t                             SVI2Enable;
0372     uint8_t                             VRHotGpio;
0373     uint8_t                             AcDcGpio;
0374     uint8_t                             ThermGpio;
0375
0376     uint16_t                            PPM_PkgPwrLimit;
0377     uint16_t                            PPM_TemperatureLimit;
0378
0379     uint16_t                            DefaultTdp;
0380     uint16_t                            TargetTdp;
0381
0382     uint16_t                            FpsHighT;
0383     uint16_t                            FpsLowT;
0384
0385     uint16_t                            BAPMTI_R  [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS];
0386     uint16_t                            BAPMTI_RC [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS];
0387
0388     uint8_t                             DTEAmbientTempBase;
0389     uint8_t                             DTETjOffset;
0390     uint8_t                             GpuTjMax;
0391     uint8_t                             GpuTjHyst;
0392
0393     uint16_t                            BootVddc;
0394     uint16_t                            BootVddci;
0395
0396     uint16_t                            BootMVdd;
0397     uint16_t                            padding;
0398
0399     uint32_t                            BAPM_TEMP_GRADIENT;
0400
0401     uint32_t                            LowSclkInterruptT;
0402 };
0403
0404 typedef struct SMU7_Discrete_DpmTable SMU7_Discrete_DpmTable;
0405
0406 #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
0407 #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU7_MAX_LEVELS_MEMORY
0408
0409 struct SMU7_Discrete_MCRegisterAddress
0410 {
0411     uint16_t s0;
0412     uint16_t s1;
0413 };
0414
0415 typedef struct SMU7_Discrete_MCRegisterAddress SMU7_Discrete_MCRegisterAddress;
0416
0417 struct SMU7_Discrete_MCRegisterSet
0418 {
0419     uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
0420 };
0421
0422 typedef struct SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisterSet;
0423
0424 struct SMU7_Discrete_MCRegisters
0425 {
0426     uint8_t                             last;
0427     uint8_t                             reserved[3];
0428     SMU7_Discrete_MCRegisterAddress     address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
0429     SMU7_Discrete_MCRegisterSet         data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
0430 };
0431
0432 typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters;
0433
0434 struct SMU7_Discrete_FanTable
0435 {
0436     uint16_t FdoMode;
0437     int16_t  TempMin;
0438     int16_t  TempMed;
0439     int16_t  TempMax;
0440     int16_t  Slope1;
0441     int16_t  Slope2;
0442     int16_t  FdoMin;
0443     int16_t  HystUp;
0444     int16_t  HystDown;
0445     int16_t  HystSlope;
0446     int16_t  TempRespLim;
0447     int16_t  TempCurr;
0448     int16_t  SlopeCurr;
0449     int16_t  PwmCurr;
0450     uint32_t RefreshPeriod;
0451     int16_t  FdoMax;
0452     uint8_t  TempSrc;
0453     int8_t   Padding;
0454 };
0455
0456 typedef struct SMU7_Discrete_FanTable SMU7_Discrete_FanTable;
0457
0458
0459 struct SMU7_Discrete_PmFuses {
0460   // dw0-dw1
0461   uint8_t BapmVddCVidHiSidd[8];
0462
0463   // dw2-dw3
0464   uint8_t BapmVddCVidLoSidd[8];
0465
0466   // dw4-dw5
0467   uint8_t VddCVid[8];
0468
0469   // dw6
0470   uint8_t SviLoadLineEn;
0471   uint8_t SviLoadLineVddC;
0472   uint8_t SviLoadLineTrimVddC;
0473   uint8_t SviLoadLineOffsetVddC;
0474
0475   // dw7
0476   uint16_t TDC_VDDC_PkgLimit;
0477   uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
0478   uint8_t TDC_MAWt;
0479
0480   // dw8
0481   uint8_t TdcWaterfallCtl;
0482   uint8_t LPMLTemperatureMin;
0483   uint8_t LPMLTemperatureMax;
0484   uint8_t Reserved;
0485
0486   // dw9-dw10
0487   uint8_t BapmVddCVidHiSidd2[8];
0488
0489   // dw11-dw12
0490   int16_t FuzzyFan_ErrorSetDelta;
0491   int16_t FuzzyFan_ErrorRateSetDelta;
0492   int16_t FuzzyFan_PwmSetDelta;
0493   uint16_t CalcMeasPowerBlend;
0494
0495   // dw13-dw16
0496   uint8_t GnbLPML[16];
0497
0498   // dw17
0499   uint8_t GnbLPMLMaxVid;
0500   uint8_t GnbLPMLMinVid;
0501   uint8_t Reserved1[2];
0502
0503   // dw18
0504   uint16_t BapmVddCBaseLeakageHiSidd;
0505   uint16_t BapmVddCBaseLeakageLoSidd;
0506 };
0507
0508 typedef struct SMU7_Discrete_PmFuses SMU7_Discrete_PmFuses;
0509
0510
0511 #pragma pack(pop)
0512
0513 #endif
0514