drm/radeon/si_dpm.h

0001 /*
0002  * Copyright 2012 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __SI_DPM_H__
0024 #define __SI_DPM_H__
0025
0026 #include "ni_dpm.h"
0027 #include "sislands_smc.h"
0028
0029 enum si_cac_config_reg_type
0030 {
0031     SISLANDS_CACCONFIG_MMR = 0,
0032     SISLANDS_CACCONFIG_CGIND,
0033     SISLANDS_CACCONFIG_MAX
0034 };
0035
0036 struct si_cac_config_reg
0037 {
0038     u32 offset;
0039     u32 mask;
0040     u32 shift;
0041     u32 value;
0042     enum si_cac_config_reg_type type;
0043 };
0044
0045 struct si_powertune_data
0046 {
0047     u32 cac_window;
0048     u32 l2_lta_window_size_default;
0049     u8 lts_truncate_default;
0050     u8 shift_n_default;
0051     u8 operating_temp;
0052     struct ni_leakage_coeffients leakage_coefficients;
0053     u32 fixed_kt;
0054     u32 lkge_lut_v0_percent;
0055     u8 dc_cac[NISLANDS_DCCAC_MAX_LEVELS];
0056     bool enable_powertune_by_default;
0057 };
0058
0059 struct si_dyn_powertune_data
0060 {
0061     u32 cac_leakage;
0062     s32 leakage_minimum_temperature;
0063     u32 wintime;
0064     u32 l2_lta_window_size;
0065     u8 lts_truncate;
0066     u8 shift_n;
0067     u8 dc_pwr_value;
0068     bool disable_uvd_powertune;
0069 };
0070
0071 struct si_dte_data
0072 {
0073     u32 tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
0074     u32 r[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
0075     u32 k;
0076     u32 t0;
0077     u32 max_t;
0078     u8 window_size;
0079     u8 temp_select;
0080     u8 dte_mode;
0081     u8 tdep_count;
0082     u8 t_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
0083     u32 tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
0084     u32 tdep_r[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
0085     u32 t_threshold;
0086     bool enable_dte_by_default;
0087 };
0088
0089 struct si_clock_registers {
0090     u32 cg_spll_func_cntl;
0091     u32 cg_spll_func_cntl_2;
0092     u32 cg_spll_func_cntl_3;
0093     u32 cg_spll_func_cntl_4;
0094     u32 cg_spll_spread_spectrum;
0095     u32 cg_spll_spread_spectrum_2;
0096     u32 dll_cntl;
0097     u32 mclk_pwrmgt_cntl;
0098     u32 mpll_ad_func_cntl;
0099     u32 mpll_dq_func_cntl;
0100     u32 mpll_func_cntl;
0101     u32 mpll_func_cntl_1;
0102     u32 mpll_func_cntl_2;
0103     u32 mpll_ss1;
0104     u32 mpll_ss2;
0105 };
0106
0107 struct si_mc_reg_entry {
0108     u32 mclk_max;
0109     u32 mc_data[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
0110 };
0111
0112 struct si_mc_reg_table {
0113     u8 last;
0114     u8 num_entries;
0115     u16 valid_flag;
0116     struct si_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
0117     SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
0118 };
0119
0120 #define SISLANDS_MCREGISTERTABLE_INITIAL_SLOT               0
0121 #define SISLANDS_MCREGISTERTABLE_ACPI_SLOT                  1
0122 #define SISLANDS_MCREGISTERTABLE_ULV_SLOT                   2
0123 #define SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT     3
0124
0125 struct si_leakage_voltage_entry
0126 {
0127     u16 voltage;
0128     u16 leakage_index;
0129 };
0130
0131 #define SISLANDS_LEAKAGE_INDEX0     0xff01
0132 #define SISLANDS_MAX_LEAKAGE_COUNT  4
0133
0134 struct si_leakage_voltage
0135 {
0136     u16 count;
0137     struct si_leakage_voltage_entry entries[SISLANDS_MAX_LEAKAGE_COUNT];
0138 };
0139
0140 #define SISLANDS_MAX_HARDWARE_POWERLEVELS 5
0141
0142 struct si_ulv_param {
0143     bool supported;
0144     u32 cg_ulv_control;
0145     u32 cg_ulv_parameter;
0146     u32 volt_change_delay;
0147     struct rv7xx_pl pl;
0148     bool one_pcie_lane_in_ulv;
0149 };
0150
0151 struct si_power_info {
0152     /* must be first! */
0153     struct ni_power_info ni;
0154     struct si_clock_registers clock_registers;
0155     struct si_mc_reg_table mc_reg_table;
0156     struct atom_voltage_table mvdd_voltage_table;
0157     struct atom_voltage_table vddc_phase_shed_table;
0158     struct si_leakage_voltage leakage_voltage;
0159     u16 mvdd_bootup_value;
0160     struct si_ulv_param ulv;
0161     u32 max_cu;
0162     /* pcie gen */
0163     enum radeon_pcie_gen force_pcie_gen;
0164     enum radeon_pcie_gen boot_pcie_gen;
0165     enum radeon_pcie_gen acpi_pcie_gen;
0166     u32 sys_pcie_mask;
0167     /* flags */
0168     bool enable_dte;
0169     bool enable_ppm;
0170     bool vddc_phase_shed_control;
0171     bool pspp_notify_required;
0172     bool sclk_deep_sleep_above_low;
0173     bool voltage_control_svi2;
0174     bool vddci_control_svi2;
0175     /* smc offsets */
0176     u32 sram_end;
0177     u32 state_table_start;
0178     u32 soft_regs_start;
0179     u32 mc_reg_table_start;
0180     u32 arb_table_start;
0181     u32 cac_table_start;
0182     u32 dte_table_start;
0183     u32 spll_table_start;
0184     u32 papm_cfg_table_start;
0185     u32 fan_table_start;
0186     /* CAC stuff */
0187     const struct si_cac_config_reg *cac_weights;
0188     const struct si_cac_config_reg *lcac_config;
0189     const struct si_cac_config_reg *cac_override;
0190     const struct si_powertune_data *powertune_data;
0191     struct si_dyn_powertune_data dyn_powertune_data;
0192     /* DTE stuff */
0193     struct si_dte_data dte_data;
0194     /* scratch structs */
0195     SMC_SIslands_MCRegisters smc_mc_reg_table;
0196     SISLANDS_SMC_STATETABLE smc_statetable;
0197     PP_SIslands_PAPMParameters papm_parm;
0198     /* SVI2 */
0199     u8 svd_gpio_id;
0200     u8 svc_gpio_id;
0201     /* fan control */
0202     bool fan_ctrl_is_in_default_mode;
0203     u32 t_min;
0204     u32 fan_ctrl_default_mode;
0205     bool fan_is_controlled_by_smc;
0206 };
0207
0208 #define SISLANDS_INITIAL_STATE_ARB_INDEX    0
0209 #define SISLANDS_ACPI_STATE_ARB_INDEX       1
0210 #define SISLANDS_ULV_STATE_ARB_INDEX        2
0211 #define SISLANDS_DRIVER_STATE_ARB_INDEX     3
0212
0213 #define SISLANDS_DPM2_MAX_PULSE_SKIP        256
0214
0215 #define SISLANDS_DPM2_NEAR_TDP_DEC          10
0216 #define SISLANDS_DPM2_ABOVE_SAFE_INC        5
0217 #define SISLANDS_DPM2_BELOW_SAFE_INC        20
0218
0219 #define SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT            80
0220
0221 #define SISLANDS_DPM2_MAXPS_PERCENT_H                   99
0222 #define SISLANDS_DPM2_MAXPS_PERCENT_M                   99
0223
0224 #define SISLANDS_DPM2_SQ_RAMP_MAX_POWER                 0x3FFF
0225 #define SISLANDS_DPM2_SQ_RAMP_MIN_POWER                 0x12
0226 #define SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA           0x15
0227 #define SISLANDS_DPM2_SQ_RAMP_STI_SIZE                  0x1E
0228 #define SISLANDS_DPM2_SQ_RAMP_LTI_RATIO                 0xF
0229
0230 #define SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN         10
0231
0232 #define SISLANDS_VRC_DFLT                               0xC000B3
0233 #define SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT             1687
0234 #define SISLANDS_CGULVPARAMETER_DFLT                    0x00040035
0235 #define SISLANDS_CGULVCONTROL_DFLT                      0x1f007550
0236
0237 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
0238 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
0239 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
0240                           u32 max_voltage_steps,
0241                           struct atom_voltage_table *voltage_table);
0242
0243 #endif