drm/radeon/rv770_smc.h

0001 /*
0002  * Copyright 2011 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __RV770_SMC_H__
0024 #define __RV770_SMC_H__
0025
0026 #include "ppsmc.h"
0027
0028 #pragma pack(push, 1)
0029
0030 #define RV770_SMC_TABLE_ADDRESS 0xB000
0031
0032 #define RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE    3
0033
0034 struct RV770_SMC_SCLK_VALUE
0035 {
0036     uint32_t        vCG_SPLL_FUNC_CNTL;
0037     uint32_t        vCG_SPLL_FUNC_CNTL_2;
0038     uint32_t        vCG_SPLL_FUNC_CNTL_3;
0039     uint32_t        vCG_SPLL_SPREAD_SPECTRUM;
0040     uint32_t        vCG_SPLL_SPREAD_SPECTRUM_2;
0041     uint32_t        sclk_value;
0042 };
0043
0044 typedef struct RV770_SMC_SCLK_VALUE RV770_SMC_SCLK_VALUE;
0045
0046 struct RV770_SMC_MCLK_VALUE
0047 {
0048     uint32_t        vMPLL_AD_FUNC_CNTL;
0049     uint32_t        vMPLL_AD_FUNC_CNTL_2;
0050     uint32_t        vMPLL_DQ_FUNC_CNTL;
0051     uint32_t        vMPLL_DQ_FUNC_CNTL_2;
0052     uint32_t        vMCLK_PWRMGT_CNTL;
0053     uint32_t        vDLL_CNTL;
0054     uint32_t        vMPLL_SS;
0055     uint32_t        vMPLL_SS2;
0056     uint32_t        mclk_value;
0057 };
0058
0059 typedef struct RV770_SMC_MCLK_VALUE RV770_SMC_MCLK_VALUE;
0060
0061
0062 struct RV730_SMC_MCLK_VALUE
0063 {
0064     uint32_t        vMCLK_PWRMGT_CNTL;
0065     uint32_t        vDLL_CNTL;
0066     uint32_t        vMPLL_FUNC_CNTL;
0067     uint32_t        vMPLL_FUNC_CNTL2;
0068     uint32_t        vMPLL_FUNC_CNTL3;
0069     uint32_t        vMPLL_SS;
0070     uint32_t        vMPLL_SS2;
0071     uint32_t        mclk_value;
0072 };
0073
0074 typedef struct RV730_SMC_MCLK_VALUE RV730_SMC_MCLK_VALUE;
0075
0076 struct RV770_SMC_VOLTAGE_VALUE
0077 {
0078     uint16_t             value;
0079     uint8_t              index;
0080     uint8_t              padding;
0081 };
0082
0083 typedef struct RV770_SMC_VOLTAGE_VALUE RV770_SMC_VOLTAGE_VALUE;
0084
0085 union RV7XX_SMC_MCLK_VALUE
0086 {
0087     RV770_SMC_MCLK_VALUE    mclk770;
0088     RV730_SMC_MCLK_VALUE    mclk730;
0089 };
0090
0091 typedef union RV7XX_SMC_MCLK_VALUE RV7XX_SMC_MCLK_VALUE, *LPRV7XX_SMC_MCLK_VALUE;
0092
0093 struct RV770_SMC_HW_PERFORMANCE_LEVEL
0094 {
0095     uint8_t                 arbValue;
0096     union{
0097         uint8_t             seqValue;
0098         uint8_t             ACIndex;
0099     };
0100     uint8_t                 displayWatermark;
0101     uint8_t                 gen2PCIE;
0102     uint8_t                 gen2XSP;
0103     uint8_t                 backbias;
0104     uint8_t                 strobeMode;
0105     uint8_t                 mcFlags;
0106     uint32_t                aT;
0107     uint32_t                bSP;
0108     RV770_SMC_SCLK_VALUE    sclk;
0109     RV7XX_SMC_MCLK_VALUE    mclk;
0110     RV770_SMC_VOLTAGE_VALUE vddc;
0111     RV770_SMC_VOLTAGE_VALUE mvdd;
0112     RV770_SMC_VOLTAGE_VALUE vddci;
0113     uint8_t                 reserved1;
0114     uint8_t                 reserved2;
0115     uint8_t                 stateFlags;
0116     uint8_t                 padding;
0117 };
0118
0119 #define SMC_STROBE_RATIO    0x0F
0120 #define SMC_STROBE_ENABLE   0x10
0121
0122 #define SMC_MC_EDC_RD_FLAG  0x01
0123 #define SMC_MC_EDC_WR_FLAG  0x02
0124 #define SMC_MC_RTT_ENABLE   0x04
0125 #define SMC_MC_STUTTER_EN   0x08
0126
0127 typedef struct RV770_SMC_HW_PERFORMANCE_LEVEL RV770_SMC_HW_PERFORMANCE_LEVEL;
0128
0129 struct RV770_SMC_SWSTATE
0130 {
0131     uint8_t           flags;
0132     uint8_t           padding1;
0133     uint8_t           padding2;
0134     uint8_t           padding3;
0135     RV770_SMC_HW_PERFORMANCE_LEVEL levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
0136 };
0137
0138 typedef struct RV770_SMC_SWSTATE RV770_SMC_SWSTATE;
0139
0140 #define RV770_SMC_VOLTAGEMASK_VDDC 0
0141 #define RV770_SMC_VOLTAGEMASK_MVDD 1
0142 #define RV770_SMC_VOLTAGEMASK_VDDCI 2
0143 #define RV770_SMC_VOLTAGEMASK_MAX  4
0144
0145 struct RV770_SMC_VOLTAGEMASKTABLE
0146 {
0147     uint8_t  highMask[RV770_SMC_VOLTAGEMASK_MAX];
0148     uint32_t lowMask[RV770_SMC_VOLTAGEMASK_MAX];
0149 };
0150
0151 typedef struct RV770_SMC_VOLTAGEMASKTABLE RV770_SMC_VOLTAGEMASKTABLE;
0152
0153 #define MAX_NO_VREG_STEPS 32
0154
0155 struct RV770_SMC_STATETABLE
0156 {
0157     uint8_t             thermalProtectType;
0158     uint8_t             systemFlags;
0159     uint8_t             maxVDDCIndexInPPTable;
0160     uint8_t             extraFlags;
0161     uint8_t             highSMIO[MAX_NO_VREG_STEPS];
0162     uint32_t            lowSMIO[MAX_NO_VREG_STEPS];
0163     RV770_SMC_VOLTAGEMASKTABLE voltageMaskTable;
0164     RV770_SMC_SWSTATE   initialState;
0165     RV770_SMC_SWSTATE   ACPIState;
0166     RV770_SMC_SWSTATE   driverState;
0167     RV770_SMC_SWSTATE   ULVState;
0168 };
0169
0170 typedef struct RV770_SMC_STATETABLE RV770_SMC_STATETABLE;
0171
0172 #define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01
0173
0174 #pragma pack(pop)
0175
0176 #define RV770_SMC_SOFT_REGISTERS_START        0x104
0177
0178 #define RV770_SMC_SOFT_REGISTER_mclk_chg_timeout        0x0
0179 #define RV770_SMC_SOFT_REGISTER_baby_step_timer         0x8
0180 #define RV770_SMC_SOFT_REGISTER_delay_bbias             0xC
0181 #define RV770_SMC_SOFT_REGISTER_delay_vreg              0x10
0182 #define RV770_SMC_SOFT_REGISTER_delay_acpi              0x2C
0183 #define RV770_SMC_SOFT_REGISTER_seq_index               0x64
0184 #define RV770_SMC_SOFT_REGISTER_mvdd_chg_time           0x68
0185 #define RV770_SMC_SOFT_REGISTER_mclk_switch_lim         0x78
0186 #define RV770_SMC_SOFT_REGISTER_mc_block_delay          0x90
0187 #define RV770_SMC_SOFT_REGISTER_uvd_enabled             0x9C
0188 #define RV770_SMC_SOFT_REGISTER_is_asic_lombok          0xA0
0189
0190 int rv770_copy_bytes_to_smc(struct radeon_device *rdev,
0191                 u16 smc_start_address, const u8 *src,
0192                 u16 byte_count, u16 limit);
0193 void rv770_start_smc(struct radeon_device *rdev);
0194 void rv770_reset_smc(struct radeon_device *rdev);
0195 void rv770_stop_smc_clock(struct radeon_device *rdev);
0196 void rv770_start_smc_clock(struct radeon_device *rdev);
0197 bool rv770_is_smc_running(struct radeon_device *rdev);
0198 PPSMC_Result rv770_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg);
0199 PPSMC_Result rv770_wait_for_smc_inactive(struct radeon_device *rdev);
0200 int rv770_read_smc_sram_dword(struct radeon_device *rdev,
0201                   u16 smc_address, u32 *value, u16 limit);
0202 int rv770_write_smc_sram_dword(struct radeon_device *rdev,
0203                    u16 smc_address, u32 value, u16 limit);
0204 int rv770_load_smc_ucode(struct radeon_device *rdev,
0205              u16 limit);
0206
0207 #endif