drm/radeon/rv770_dpm.h

0001 /*
0002  * Copyright 2011 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __RV770_DPM_H__
0024 #define __RV770_DPM_H__
0025
0026 #include "radeon.h"
0027 #include "rv770_smc.h"
0028
0029 struct rv770_clock_registers {
0030     u32 cg_spll_func_cntl;
0031     u32 cg_spll_func_cntl_2;
0032     u32 cg_spll_func_cntl_3;
0033     u32 cg_spll_spread_spectrum;
0034     u32 cg_spll_spread_spectrum_2;
0035     u32 mpll_ad_func_cntl;
0036     u32 mpll_ad_func_cntl_2;
0037     u32 mpll_dq_func_cntl;
0038     u32 mpll_dq_func_cntl_2;
0039     u32 mclk_pwrmgt_cntl;
0040     u32 dll_cntl;
0041     u32 mpll_ss1;
0042     u32 mpll_ss2;
0043 };
0044
0045 struct rv730_clock_registers {
0046     u32 cg_spll_func_cntl;
0047     u32 cg_spll_func_cntl_2;
0048     u32 cg_spll_func_cntl_3;
0049     u32 cg_spll_spread_spectrum;
0050     u32 cg_spll_spread_spectrum_2;
0051     u32 mclk_pwrmgt_cntl;
0052     u32 dll_cntl;
0053     u32 mpll_func_cntl;
0054     u32 mpll_func_cntl2;
0055     u32 mpll_func_cntl3;
0056     u32 mpll_ss;
0057     u32 mpll_ss2;
0058 };
0059
0060 union r7xx_clock_registers {
0061     struct rv770_clock_registers rv770;
0062     struct rv730_clock_registers rv730;
0063 };
0064
0065 struct vddc_table_entry {
0066     u16 vddc;
0067     u8 vddc_index;
0068     u8 high_smio;
0069     u32 low_smio;
0070 };
0071
0072 #define MAX_NO_OF_MVDD_VALUES 2
0073 #define MAX_NO_VREG_STEPS 32
0074
0075 struct rv7xx_power_info {
0076     /* flags */
0077     bool mem_gddr5;
0078     bool pcie_gen2;
0079     bool dynamic_pcie_gen2;
0080     bool acpi_pcie_gen2;
0081     bool boot_in_gen2;
0082     bool voltage_control; /* vddc */
0083     bool mvdd_control;
0084     bool sclk_ss;
0085     bool mclk_ss;
0086     bool dynamic_ss;
0087     bool gfx_clock_gating;
0088     bool mg_clock_gating;
0089     bool mgcgtssm;
0090     bool power_gating;
0091     bool thermal_protection;
0092     bool display_gap;
0093     bool dcodt;
0094     bool ulps;
0095     /* registers */
0096     union r7xx_clock_registers clk_regs;
0097     u32 s0_vid_lower_smio_cntl;
0098     /* voltage */
0099     u32 vddc_mask_low;
0100     u32 mvdd_mask_low;
0101     u32 mvdd_split_frequency;
0102     u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES];
0103     u16 max_vddc;
0104     u16 max_vddc_in_table;
0105     u16 min_vddc_in_table;
0106     struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS];
0107     u8 valid_vddc_entries;
0108     /* dc odt */
0109     u32 mclk_odt_threshold;
0110     u8 odt_value_0[2];
0111     u8 odt_value_1[2];
0112     /* stored values */
0113     u32 boot_sclk;
0114     u16 acpi_vddc;
0115     u32 ref_div;
0116     u32 active_auto_throttle_sources;
0117     u32 mclk_stutter_mode_threshold;
0118     u32 mclk_strobe_mode_threshold;
0119     u32 mclk_edc_enable_threshold;
0120     u32 bsp;
0121     u32 bsu;
0122     u32 pbsp;
0123     u32 pbsu;
0124     u32 dsp;
0125     u32 psp;
0126     u32 asi;
0127     u32 pasi;
0128     u32 vrc;
0129     u32 restricted_levels;
0130     u32 rlp;
0131     u32 rmp;
0132     u32 lhp;
0133     u32 lmp;
0134     /* smc offsets */
0135     u16 state_table_start;
0136     u16 soft_regs_start;
0137     u16 sram_end;
0138     /* scratch structs */
0139     RV770_SMC_STATETABLE smc_statetable;
0140 };
0141
0142 struct rv7xx_pl {
0143     u32 sclk;
0144     u32 mclk;
0145     u16 vddc;
0146     u16 vddci; /* eg+ only */
0147     u32 flags;
0148     enum radeon_pcie_gen pcie_gen; /* si+ only */
0149 };
0150
0151 struct rv7xx_ps {
0152     struct rv7xx_pl high;
0153     struct rv7xx_pl medium;
0154     struct rv7xx_pl low;
0155     bool dc_compatible;
0156 };
0157
0158 #define RV770_RLP_DFLT                                10
0159 #define RV770_RMP_DFLT                                25
0160 #define RV770_LHP_DFLT                                25
0161 #define RV770_LMP_DFLT                                10
0162 #define RV770_VRC_DFLT                                0x003f
0163 #define RV770_ASI_DFLT                                1000
0164 #define RV770_HASI_DFLT                               200000
0165 #define RV770_MGCGTTLOCAL0_DFLT                       0x00100000
0166 #define RV7XX_MGCGTTLOCAL0_DFLT                       0
0167 #define RV770_MGCGTTLOCAL1_DFLT                       0xFFFF0000
0168 #define RV770_MGCGCGTSSMCTRL_DFLT                     0x55940000
0169
0170 #define MVDD_LOW_INDEX  0
0171 #define MVDD_HIGH_INDEX 1
0172
0173 #define MVDD_LOW_VALUE  0
0174 #define MVDD_HIGH_VALUE 0xffff
0175
0176 #define RV770_DEFAULT_VCLK_FREQ  53300 /* 10 khz */
0177 #define RV770_DEFAULT_DCLK_FREQ  40000 /* 10 khz */
0178
0179 /* rv730/rv710 */
0180 int rv730_populate_sclk_value(struct radeon_device *rdev,
0181                   u32 engine_clock,
0182                   RV770_SMC_SCLK_VALUE *sclk);
0183 int rv730_populate_mclk_value(struct radeon_device *rdev,
0184                   u32 engine_clock, u32 memory_clock,
0185                   LPRV7XX_SMC_MCLK_VALUE mclk);
0186 void rv730_read_clock_registers(struct radeon_device *rdev);
0187 int rv730_populate_smc_acpi_state(struct radeon_device *rdev,
0188                   RV770_SMC_STATETABLE *table);
0189 int rv730_populate_smc_initial_state(struct radeon_device *rdev,
0190                      struct radeon_ps *radeon_initial_state,
0191                      RV770_SMC_STATETABLE *table);
0192 void rv730_program_memory_timing_parameters(struct radeon_device *rdev,
0193                         struct radeon_ps *radeon_state);
0194 void rv730_power_gating_enable(struct radeon_device *rdev,
0195                    bool enable);
0196 void rv730_start_dpm(struct radeon_device *rdev);
0197 void rv730_stop_dpm(struct radeon_device *rdev);
0198 void rv730_program_dcodt(struct radeon_device *rdev, bool use_dcodt);
0199 void rv730_get_odt_values(struct radeon_device *rdev);
0200
0201 /* rv740 */
0202 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
0203                   RV770_SMC_SCLK_VALUE *sclk);
0204 int rv740_populate_mclk_value(struct radeon_device *rdev,
0205                   u32 engine_clock, u32 memory_clock,
0206                   RV7XX_SMC_MCLK_VALUE *mclk);
0207 void rv740_read_clock_registers(struct radeon_device *rdev);
0208 int rv740_populate_smc_acpi_state(struct radeon_device *rdev,
0209                   RV770_SMC_STATETABLE *table);
0210 void rv740_enable_mclk_spread_spectrum(struct radeon_device *rdev,
0211                        bool enable);
0212 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock);
0213 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock);
0214 u32 rv740_get_decoded_reference_divider(u32 encoded_ref);
0215
0216 /* rv770 */
0217 u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf);
0218 int rv770_populate_vddc_value(struct radeon_device *rdev, u16 vddc,
0219                   RV770_SMC_VOLTAGE_VALUE *voltage);
0220 int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
0221                   RV770_SMC_VOLTAGE_VALUE *voltage);
0222 u8 rv770_get_seq_value(struct radeon_device *rdev,
0223                struct rv7xx_pl *pl);
0224 int rv770_populate_initial_mvdd_value(struct radeon_device *rdev,
0225                       RV770_SMC_VOLTAGE_VALUE *voltage);
0226 u32 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev,
0227                     u32 engine_clock);
0228 void rv770_program_response_times(struct radeon_device *rdev);
0229 int rv770_populate_smc_sp(struct radeon_device *rdev,
0230               struct radeon_ps *radeon_state,
0231               RV770_SMC_SWSTATE *smc_state);
0232 int rv770_populate_smc_t(struct radeon_device *rdev,
0233              struct radeon_ps *radeon_state,
0234              RV770_SMC_SWSTATE *smc_state);
0235 void rv770_read_voltage_smio_registers(struct radeon_device *rdev);
0236 void rv770_get_memory_type(struct radeon_device *rdev);
0237 void r7xx_start_smc(struct radeon_device *rdev);
0238 u8 rv770_get_memory_module_index(struct radeon_device *rdev);
0239 void rv770_get_max_vddc(struct radeon_device *rdev);
0240 void rv770_get_pcie_gen2_status(struct radeon_device *rdev);
0241 void rv770_enable_acpi_pm(struct radeon_device *rdev);
0242 void rv770_restore_cgcg(struct radeon_device *rdev);
0243 bool rv770_dpm_enabled(struct radeon_device *rdev);
0244 void rv770_enable_voltage_control(struct radeon_device *rdev,
0245                   bool enable);
0246 void rv770_enable_backbias(struct radeon_device *rdev,
0247                bool enable);
0248 void rv770_enable_thermal_protection(struct radeon_device *rdev,
0249                      bool enable);
0250 void rv770_enable_auto_throttle_source(struct radeon_device *rdev,
0251                        enum radeon_dpm_auto_throttle_src source,
0252                        bool enable);
0253 void rv770_setup_bsp(struct radeon_device *rdev);
0254 void rv770_program_git(struct radeon_device *rdev);
0255 void rv770_program_tp(struct radeon_device *rdev);
0256 void rv770_program_tpp(struct radeon_device *rdev);
0257 void rv770_program_sstp(struct radeon_device *rdev);
0258 void rv770_program_engine_speed_parameters(struct radeon_device *rdev);
0259 void rv770_program_vc(struct radeon_device *rdev);
0260 void rv770_clear_vc(struct radeon_device *rdev);
0261 int rv770_upload_firmware(struct radeon_device *rdev);
0262 void rv770_stop_dpm(struct radeon_device *rdev);
0263 void r7xx_stop_smc(struct radeon_device *rdev);
0264 void rv770_reset_smio_status(struct radeon_device *rdev);
0265 int rv770_restrict_performance_levels_before_switch(struct radeon_device *rdev);
0266 int rv770_dpm_force_performance_level(struct radeon_device *rdev,
0267                       enum radeon_dpm_forced_level level);
0268 int rv770_halt_smc(struct radeon_device *rdev);
0269 int rv770_resume_smc(struct radeon_device *rdev);
0270 int rv770_set_sw_state(struct radeon_device *rdev);
0271 int rv770_set_boot_state(struct radeon_device *rdev);
0272 int rv7xx_parse_power_table(struct radeon_device *rdev);
0273 void rv770_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
0274                           struct radeon_ps *new_ps,
0275                           struct radeon_ps *old_ps);
0276 void rv770_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
0277                          struct radeon_ps *new_ps,
0278                          struct radeon_ps *old_ps);
0279 void rv770_get_engine_memory_ss(struct radeon_device *rdev);
0280
0281 /* smc */
0282 int rv770_write_smc_soft_register(struct radeon_device *rdev,
0283                   u16 reg_offset, u32 value);
0284
0285 #endif