drm/radeon/rv770_dma.c

0001 /*
0002  * Copyright 2013 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Alex Deucher
0023  */
0024
0025 #include "radeon.h"
0026 #include "radeon_asic.h"
0027 #include "rv770d.h"
0028
0029 /**
0030  * rv770_copy_dma - copy pages using the DMA engine
0031  *
0032  * @rdev: radeon_device pointer
0033  * @src_offset: src GPU address
0034  * @dst_offset: dst GPU address
0035  * @num_gpu_pages: number of GPU pages to xfer
0036  * @resv: reservation object to sync to
0037  *
0038  * Copy GPU paging using the DMA engine (r7xx).
0039  * Used by the radeon ttm implementation to move pages if
0040  * registered as the asic copy callback.
0041  */
0042 struct radeon_fence *rv770_copy_dma(struct radeon_device *rdev,
0043                     uint64_t src_offset, uint64_t dst_offset,
0044                     unsigned num_gpu_pages,
0045                     struct dma_resv *resv)
0046 {
0047     struct radeon_fence *fence;
0048     struct radeon_sync sync;
0049     int ring_index = rdev->asic->copy.dma_ring_index;
0050     struct radeon_ring *ring = &rdev->ring[ring_index];
0051     u32 size_in_dw, cur_size_in_dw;
0052     int i, num_loops;
0053     int r = 0;
0054
0055     radeon_sync_create(&sync);
0056
0057     size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
0058     num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFF);
0059     r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8);
0060     if (r) {
0061         DRM_ERROR("radeon: moving bo (%d).\n", r);
0062         radeon_sync_free(rdev, &sync, NULL);
0063         return ERR_PTR(r);
0064     }
0065
0066     radeon_sync_resv(rdev, &sync, resv, false);
0067     radeon_sync_rings(rdev, &sync, ring->idx);
0068
0069     for (i = 0; i < num_loops; i++) {
0070         cur_size_in_dw = size_in_dw;
0071         if (cur_size_in_dw > 0xFFFF)
0072             cur_size_in_dw = 0xFFFF;
0073         size_in_dw -= cur_size_in_dw;
0074         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
0075         radeon_ring_write(ring, dst_offset & 0xfffffffc);
0076         radeon_ring_write(ring, src_offset & 0xfffffffc);
0077         radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
0078         radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
0079         src_offset += cur_size_in_dw * 4;
0080         dst_offset += cur_size_in_dw * 4;
0081     }
0082
0083     r = radeon_fence_emit(rdev, &fence, ring->idx);
0084     if (r) {
0085         radeon_ring_unlock_undo(rdev, ring);
0086         radeon_sync_free(rdev, &sync, NULL);
0087         return ERR_PTR(r);
0088     }
0089
0090     radeon_ring_unlock_commit(rdev, ring, false);
0091     radeon_sync_free(rdev, &sync, fence);
0092
0093     return fence;
0094 }