drm/radeon/rv740d.h

0001 /*
0002  * Copyright 2011 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef RV740_H
0024 #define RV740_H
0025
0026 #define CG_SPLL_FUNC_CNTL               0x600
0027 #define     SPLL_RESET              (1 << 0)
0028 #define     SPLL_SLEEP              (1 << 1)
0029 #define     SPLL_BYPASS_EN              (1 << 3)
0030 #define     SPLL_REF_DIV(x)             ((x) << 4)
0031 #define     SPLL_REF_DIV_MASK           (0x3f << 4)
0032 #define     SPLL_PDIV_A(x)              ((x) << 20)
0033 #define     SPLL_PDIV_A_MASK            (0x7f << 20)
0034 #define CG_SPLL_FUNC_CNTL_2             0x604
0035 #define     SCLK_MUX_SEL(x)             ((x) << 0)
0036 #define     SCLK_MUX_SEL_MASK           (0x1ff << 0)
0037 #define CG_SPLL_FUNC_CNTL_3             0x608
0038 #define     SPLL_FB_DIV(x)              ((x) << 0)
0039 #define     SPLL_FB_DIV_MASK            (0x3ffffff << 0)
0040 #define     SPLL_DITHEN             (1 << 28)
0041
0042 #define MPLL_CNTL_MODE                  0x61c
0043 #define     SS_SSEN                 (1 << 24)
0044
0045 #define MPLL_AD_FUNC_CNTL               0x624
0046 #define     CLKF(x)                 ((x) << 0)
0047 #define     CLKF_MASK               (0x7f << 0)
0048 #define     CLKR(x)                 ((x) << 7)
0049 #define     CLKR_MASK               (0x1f << 7)
0050 #define     CLKFRAC(x)              ((x) << 12)
0051 #define     CLKFRAC_MASK                (0x1f << 12)
0052 #define     YCLK_POST_DIV(x)            ((x) << 17)
0053 #define     YCLK_POST_DIV_MASK          (3 << 17)
0054 #define     IBIAS(x)                ((x) << 20)
0055 #define     IBIAS_MASK              (0x3ff << 20)
0056 #define     RESET                   (1 << 30)
0057 #define     PDNB                    (1 << 31)
0058 #define MPLL_AD_FUNC_CNTL_2             0x628
0059 #define     BYPASS                  (1 << 19)
0060 #define     BIAS_GEN_PDNB               (1 << 24)
0061 #define     RESET_EN                (1 << 25)
0062 #define     VCO_MODE                (1 << 29)
0063 #define MPLL_DQ_FUNC_CNTL               0x62c
0064 #define MPLL_DQ_FUNC_CNTL_2             0x630
0065
0066 #define MCLK_PWRMGT_CNTL                0x648
0067 #define     DLL_SPEED(x)                ((x) << 0)
0068 #define     DLL_SPEED_MASK              (0x1f << 0)
0069 #       define MPLL_PWRMGT_OFF                          (1 << 5)
0070 #       define DLL_READY                                (1 << 6)
0071 #       define MC_INT_CNTL                              (1 << 7)
0072 #       define MRDCKA0_SLEEP                            (1 << 8)
0073 #       define MRDCKA1_SLEEP                            (1 << 9)
0074 #       define MRDCKB0_SLEEP                            (1 << 10)
0075 #       define MRDCKB1_SLEEP                            (1 << 11)
0076 #       define MRDCKC0_SLEEP                            (1 << 12)
0077 #       define MRDCKC1_SLEEP                            (1 << 13)
0078 #       define MRDCKD0_SLEEP                            (1 << 14)
0079 #       define MRDCKD1_SLEEP                            (1 << 15)
0080 #       define MRDCKA0_RESET                            (1 << 16)
0081 #       define MRDCKA1_RESET                            (1 << 17)
0082 #       define MRDCKB0_RESET                            (1 << 18)
0083 #       define MRDCKB1_RESET                            (1 << 19)
0084 #       define MRDCKC0_RESET                            (1 << 20)
0085 #       define MRDCKC1_RESET                            (1 << 21)
0086 #       define MRDCKD0_RESET                            (1 << 22)
0087 #       define MRDCKD1_RESET                            (1 << 23)
0088 #       define DLL_READY_READ                           (1 << 24)
0089 #       define USE_DISPLAY_GAP                          (1 << 25)
0090 #       define USE_DISPLAY_URGENT_NORMAL                (1 << 26)
0091 #       define MPLL_TURNOFF_D2                          (1 << 28)
0092 #define DLL_CNTL                    0x64c
0093 #       define MRDCKA0_BYPASS                           (1 << 24)
0094 #       define MRDCKA1_BYPASS                           (1 << 25)
0095 #       define MRDCKB0_BYPASS                           (1 << 26)
0096 #       define MRDCKB1_BYPASS                           (1 << 27)
0097 #       define MRDCKC0_BYPASS                           (1 << 28)
0098 #       define MRDCKC1_BYPASS                           (1 << 29)
0099 #       define MRDCKD0_BYPASS                           (1 << 30)
0100 #       define MRDCKD1_BYPASS                           (1 << 31)
0101
0102 #define CG_SPLL_SPREAD_SPECTRUM             0x790
0103 #define     SSEN                    (1 << 0)
0104 #define     CLK_S(x)                ((x) << 4)
0105 #define     CLK_S_MASK              (0xfff << 4)
0106 #define CG_SPLL_SPREAD_SPECTRUM_2           0x794
0107 #define     CLK_V(x)                ((x) << 0)
0108 #define     CLK_V_MASK              (0x3ffffff << 0)
0109
0110 #define MPLL_SS1                    0x85c
0111 #define     CLKV(x)                 ((x) << 0)
0112 #define     CLKV_MASK               (0x3ffffff << 0)
0113 #define MPLL_SS2                    0x860
0114 #define     CLKS(x)                 ((x) << 0)
0115 #define     CLKS_MASK               (0xfff << 0)
0116
0117 #endif