drm/radeon/rv730d.h

0001 /*
0002  * Copyright 2011 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef RV730_H
0024 #define RV730_H
0025
0026 #define CG_SPLL_FUNC_CNTL               0x600
0027 #define     SPLL_RESET              (1 << 0)
0028 #define     SPLL_SLEEP              (1 << 1)
0029 #define     SPLL_DIVEN              (1 << 2)
0030 #define     SPLL_BYPASS_EN              (1 << 3)
0031 #define     SPLL_REF_DIV(x)             ((x) << 4)
0032 #define     SPLL_REF_DIV_MASK           (0x3f << 4)
0033 #define     SPLL_HILEN(x)               ((x) << 12)
0034 #define     SPLL_HILEN_MASK             (0xf << 12)
0035 #define     SPLL_LOLEN(x)               ((x) << 16)
0036 #define     SPLL_LOLEN_MASK             (0xf << 16)
0037 #define CG_SPLL_FUNC_CNTL_2             0x604
0038 #define     SCLK_MUX_SEL(x)             ((x) << 0)
0039 #define     SCLK_MUX_SEL_MASK           (0x1ff << 0)
0040 #define CG_SPLL_FUNC_CNTL_3             0x608
0041 #define     SPLL_FB_DIV(x)              ((x) << 0)
0042 #define     SPLL_FB_DIV_MASK            (0x3ffffff << 0)
0043 #define     SPLL_DITHEN             (1 << 28)
0044
0045 #define CG_MPLL_FUNC_CNTL               0x624
0046 #define     MPLL_RESET              (1 << 0)
0047 #define     MPLL_SLEEP              (1 << 1)
0048 #define     MPLL_DIVEN              (1 << 2)
0049 #define     MPLL_BYPASS_EN              (1 << 3)
0050 #define     MPLL_REF_DIV(x)             ((x) << 4)
0051 #define     MPLL_REF_DIV_MASK           (0x3f << 4)
0052 #define     MPLL_HILEN(x)               ((x) << 12)
0053 #define     MPLL_HILEN_MASK             (0xf << 12)
0054 #define     MPLL_LOLEN(x)               ((x) << 16)
0055 #define     MPLL_LOLEN_MASK             (0xf << 16)
0056 #define CG_MPLL_FUNC_CNTL_2             0x628
0057 #define     MCLK_MUX_SEL(x)             ((x) << 0)
0058 #define     MCLK_MUX_SEL_MASK           (0x1ff << 0)
0059 #define CG_MPLL_FUNC_CNTL_3             0x62c
0060 #define     MPLL_FB_DIV(x)              ((x) << 0)
0061 #define     MPLL_FB_DIV_MASK            (0x3ffffff << 0)
0062 #define     MPLL_DITHEN             (1 << 28)
0063
0064 #define CG_TCI_MPLL_SPREAD_SPECTRUM         0x634
0065 #define CG_TCI_MPLL_SPREAD_SPECTRUM_2           0x638
0066 #define GENERAL_PWRMGT                                  0x63c
0067 #       define GLOBAL_PWRMGT_EN                         (1 << 0)
0068 #       define STATIC_PM_EN                             (1 << 1)
0069 #       define THERMAL_PROTECTION_DIS                   (1 << 2)
0070 #       define THERMAL_PROTECTION_TYPE                  (1 << 3)
0071 #       define ENABLE_GEN2PCIE                          (1 << 4)
0072 #       define ENABLE_GEN2XSP                           (1 << 5)
0073 #       define SW_SMIO_INDEX(x)                         ((x) << 6)
0074 #       define SW_SMIO_INDEX_MASK                       (3 << 6)
0075 #       define LOW_VOLT_D2_ACPI                         (1 << 8)
0076 #       define LOW_VOLT_D3_ACPI                         (1 << 9)
0077 #       define VOLT_PWRMGT_EN                           (1 << 10)
0078 #       define BACKBIAS_PAD_EN                          (1 << 18)
0079 #       define BACKBIAS_VALUE                           (1 << 19)
0080 #       define DYN_SPREAD_SPECTRUM_EN                   (1 << 23)
0081 #       define AC_DC_SW                                 (1 << 24)
0082
0083 #define SCLK_PWRMGT_CNTL                                  0x644
0084 #       define SCLK_PWRMGT_OFF                            (1 << 0)
0085 #       define SCLK_LOW_D1                                (1 << 1)
0086 #       define FIR_RESET                                  (1 << 4)
0087 #       define FIR_FORCE_TREND_SEL                        (1 << 5)
0088 #       define FIR_TREND_MODE                             (1 << 6)
0089 #       define DYN_GFX_CLK_OFF_EN                         (1 << 7)
0090 #       define GFX_CLK_FORCE_ON                           (1 << 8)
0091 #       define GFX_CLK_REQUEST_OFF                        (1 << 9)
0092 #       define GFX_CLK_FORCE_OFF                          (1 << 10)
0093 #       define GFX_CLK_OFF_ACPI_D1                        (1 << 11)
0094 #       define GFX_CLK_OFF_ACPI_D2                        (1 << 12)
0095 #       define GFX_CLK_OFF_ACPI_D3                        (1 << 13)
0096
0097 #define TCI_MCLK_PWRMGT_CNTL                0x648
0098 #       define MPLL_PWRMGT_OFF                          (1 << 5)
0099 #       define DLL_READY                                (1 << 6)
0100 #       define MC_INT_CNTL                              (1 << 7)
0101 #       define MRDCKA_SLEEP                             (1 << 8)
0102 #       define MRDCKB_SLEEP                             (1 << 9)
0103 #       define MRDCKC_SLEEP                             (1 << 10)
0104 #       define MRDCKD_SLEEP                             (1 << 11)
0105 #       define MRDCKE_SLEEP                             (1 << 12)
0106 #       define MRDCKF_SLEEP                             (1 << 13)
0107 #       define MRDCKG_SLEEP                             (1 << 14)
0108 #       define MRDCKH_SLEEP                             (1 << 15)
0109 #       define MRDCKA_RESET                             (1 << 16)
0110 #       define MRDCKB_RESET                             (1 << 17)
0111 #       define MRDCKC_RESET                             (1 << 18)
0112 #       define MRDCKD_RESET                             (1 << 19)
0113 #       define MRDCKE_RESET                             (1 << 20)
0114 #       define MRDCKF_RESET                             (1 << 21)
0115 #       define MRDCKG_RESET                             (1 << 22)
0116 #       define MRDCKH_RESET                             (1 << 23)
0117 #       define DLL_READY_READ                           (1 << 24)
0118 #       define USE_DISPLAY_GAP                          (1 << 25)
0119 #       define USE_DISPLAY_URGENT_NORMAL                (1 << 26)
0120 #       define MPLL_TURNOFF_D2                          (1 << 28)
0121 #define TCI_DLL_CNTL                    0x64c
0122
0123 #define CG_PG_CNTL                  0x858
0124 #       define PWRGATE_ENABLE                           (1 << 0)
0125
0126 #define CG_AT                               0x6d4
0127 #define     CG_R(x)                 ((x) << 0)
0128 #define     CG_R_MASK               (0xffff << 0)
0129 #define     CG_L(x)                 ((x) << 16)
0130 #define     CG_L_MASK               (0xffff << 16)
0131
0132 #define CG_SPLL_SPREAD_SPECTRUM             0x790
0133 #define     SSEN                    (1 << 0)
0134 #define     CLK_S(x)                ((x) << 4)
0135 #define     CLK_S_MASK              (0xfff << 4)
0136 #define CG_SPLL_SPREAD_SPECTRUM_2           0x794
0137 #define     CLK_V(x)                ((x) << 0)
0138 #define     CLK_V_MASK              (0x3ffffff << 0)
0139
0140 #define MC_ARB_DRAM_TIMING              0x2774
0141 #define MC_ARB_DRAM_TIMING2             0x2778
0142
0143 #define MC_ARB_RFSH_RATE                0x27b0
0144 #define     POWERMODE0(x)               ((x) << 0)
0145 #define     POWERMODE0_MASK             (0xff << 0)
0146 #define     POWERMODE1(x)               ((x) << 8)
0147 #define     POWERMODE1_MASK             (0xff << 8)
0148 #define     POWERMODE2(x)               ((x) << 16)
0149 #define     POWERMODE2_MASK             (0xff << 16)
0150 #define     POWERMODE3(x)               ((x) << 24)
0151 #define     POWERMODE3_MASK             (0xff << 24)
0152
0153 #define MC_ARB_DRAM_TIMING_1                0x27f0
0154 #define MC_ARB_DRAM_TIMING_2                0x27f4
0155 #define MC_ARB_DRAM_TIMING_3                0x27f8
0156 #define MC_ARB_DRAM_TIMING2_1               0x27fc
0157 #define MC_ARB_DRAM_TIMING2_2               0x2800
0158 #define MC_ARB_DRAM_TIMING2_3               0x2804
0159
0160 #define MC4_IO_DQ_PAD_CNTL_D0_I0            0x2978
0161 #define MC4_IO_DQ_PAD_CNTL_D0_I1            0x297c
0162 #define MC4_IO_QS_PAD_CNTL_D0_I0            0x2980
0163 #define MC4_IO_QS_PAD_CNTL_D0_I1            0x2984
0164
0165 #endif