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0001 /*
0002  * Copyright 2011 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Alex Deucher
0023  */
0024 
0025 #include "radeon.h"
0026 #include "rv730d.h"
0027 #include "r600_dpm.h"
0028 #include "rv770.h"
0029 #include "rv770_dpm.h"
0030 #include "atom.h"
0031 
0032 #define MC_CG_ARB_FREQ_F0           0x0a
0033 #define MC_CG_ARB_FREQ_F1           0x0b
0034 #define MC_CG_ARB_FREQ_F2           0x0c
0035 #define MC_CG_ARB_FREQ_F3           0x0d
0036 
0037 int rv730_populate_sclk_value(struct radeon_device *rdev,
0038                   u32 engine_clock,
0039                   RV770_SMC_SCLK_VALUE *sclk)
0040 {
0041     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
0042     struct atom_clock_dividers dividers;
0043     u32 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl;
0044     u32 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2;
0045     u32 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3;
0046     u32 cg_spll_spread_spectrum = pi->clk_regs.rv730.cg_spll_spread_spectrum;
0047     u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv730.cg_spll_spread_spectrum_2;
0048     u64 tmp;
0049     u32 reference_clock = rdev->clock.spll.reference_freq;
0050     u32 reference_divider, post_divider;
0051     u32 fbdiv;
0052     int ret;
0053 
0054     ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
0055                          engine_clock, false, &dividers);
0056     if (ret)
0057         return ret;
0058 
0059     reference_divider = 1 + dividers.ref_div;
0060 
0061     if (dividers.enable_post_div)
0062         post_divider = ((dividers.post_div >> 4) & 0xf) +
0063             (dividers.post_div & 0xf) + 2;
0064     else
0065         post_divider = 1;
0066 
0067     tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
0068     do_div(tmp, reference_clock);
0069     fbdiv = (u32) tmp;
0070 
0071     /* set up registers */
0072     if (dividers.enable_post_div)
0073         spll_func_cntl |= SPLL_DIVEN;
0074     else
0075         spll_func_cntl &= ~SPLL_DIVEN;
0076     spll_func_cntl &= ~(SPLL_HILEN_MASK | SPLL_LOLEN_MASK | SPLL_REF_DIV_MASK);
0077     spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
0078     spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf);
0079     spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf);
0080 
0081     spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
0082     spll_func_cntl_2 |= SCLK_MUX_SEL(2);
0083 
0084     spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
0085     spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
0086     spll_func_cntl_3 |= SPLL_DITHEN;
0087 
0088     if (pi->sclk_ss) {
0089         struct radeon_atom_ss ss;
0090         u32 vco_freq = engine_clock * post_divider;
0091 
0092         if (radeon_atombios_get_asic_ss_info(rdev, &ss,
0093                              ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
0094             u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
0095             u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000);
0096 
0097             cg_spll_spread_spectrum &= ~CLK_S_MASK;
0098             cg_spll_spread_spectrum |= CLK_S(clk_s);
0099             cg_spll_spread_spectrum |= SSEN;
0100 
0101             cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
0102             cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
0103         }
0104     }
0105 
0106     sclk->sclk_value = cpu_to_be32(engine_clock);
0107     sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
0108     sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
0109     sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
0110     sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum);
0111     sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2);
0112 
0113     return 0;
0114 }
0115 
0116 int rv730_populate_mclk_value(struct radeon_device *rdev,
0117                   u32 engine_clock, u32 memory_clock,
0118                   LPRV7XX_SMC_MCLK_VALUE mclk)
0119 {
0120     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
0121     u32 mclk_pwrmgt_cntl = pi->clk_regs.rv730.mclk_pwrmgt_cntl;
0122     u32 dll_cntl = pi->clk_regs.rv730.dll_cntl;
0123     u32 mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl;
0124     u32 mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2;
0125     u32 mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3;
0126     u32 mpll_ss = pi->clk_regs.rv730.mpll_ss;
0127     u32 mpll_ss2 = pi->clk_regs.rv730.mpll_ss2;
0128     struct atom_clock_dividers dividers;
0129     u32 post_divider, reference_divider;
0130     int ret;
0131 
0132     ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
0133                          memory_clock, false, &dividers);
0134     if (ret)
0135         return ret;
0136 
0137     reference_divider = dividers.ref_div + 1;
0138 
0139     if (dividers.enable_post_div)
0140         post_divider = ((dividers.post_div >> 4) & 0xf) +
0141             (dividers.post_div & 0xf) + 2;
0142     else
0143         post_divider = 1;
0144 
0145     /* setup the registers */
0146     if (dividers.enable_post_div)
0147         mpll_func_cntl |= MPLL_DIVEN;
0148     else
0149         mpll_func_cntl &= ~MPLL_DIVEN;
0150 
0151     mpll_func_cntl &= ~(MPLL_REF_DIV_MASK | MPLL_HILEN_MASK | MPLL_LOLEN_MASK);
0152     mpll_func_cntl |= MPLL_REF_DIV(dividers.ref_div);
0153     mpll_func_cntl |= MPLL_HILEN((dividers.post_div >> 4) & 0xf);
0154     mpll_func_cntl |= MPLL_LOLEN(dividers.post_div & 0xf);
0155 
0156     mpll_func_cntl_3 &= ~MPLL_FB_DIV_MASK;
0157     mpll_func_cntl_3 |= MPLL_FB_DIV(dividers.fb_div);
0158     if (dividers.enable_dithen)
0159         mpll_func_cntl_3 |= MPLL_DITHEN;
0160     else
0161         mpll_func_cntl_3 &= ~MPLL_DITHEN;
0162 
0163     if (pi->mclk_ss) {
0164         struct radeon_atom_ss ss;
0165         u32 vco_freq = memory_clock * post_divider;
0166 
0167         if (radeon_atombios_get_asic_ss_info(rdev, &ss,
0168                              ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
0169             u32 reference_clock = rdev->clock.mpll.reference_freq;
0170             u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
0171             u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000);
0172 
0173             mpll_ss &= ~CLK_S_MASK;
0174             mpll_ss |= CLK_S(clk_s);
0175             mpll_ss |= SSEN;
0176 
0177             mpll_ss2 &= ~CLK_V_MASK;
0178             mpll_ss |= CLK_V(clk_v);
0179         }
0180     }
0181 
0182 
0183     mclk->mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
0184     mclk->mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl);
0185     mclk->mclk730.mclk_value = cpu_to_be32(memory_clock);
0186     mclk->mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
0187     mclk->mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2);
0188     mclk->mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3);
0189     mclk->mclk730.vMPLL_SS = cpu_to_be32(mpll_ss);
0190     mclk->mclk730.vMPLL_SS2 = cpu_to_be32(mpll_ss2);
0191 
0192     return 0;
0193 }
0194 
0195 void rv730_read_clock_registers(struct radeon_device *rdev)
0196 {
0197     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
0198 
0199     pi->clk_regs.rv730.cg_spll_func_cntl =
0200         RREG32(CG_SPLL_FUNC_CNTL);
0201     pi->clk_regs.rv730.cg_spll_func_cntl_2 =
0202         RREG32(CG_SPLL_FUNC_CNTL_2);
0203     pi->clk_regs.rv730.cg_spll_func_cntl_3 =
0204         RREG32(CG_SPLL_FUNC_CNTL_3);
0205     pi->clk_regs.rv730.cg_spll_spread_spectrum =
0206         RREG32(CG_SPLL_SPREAD_SPECTRUM);
0207     pi->clk_regs.rv730.cg_spll_spread_spectrum_2 =
0208         RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
0209 
0210     pi->clk_regs.rv730.mclk_pwrmgt_cntl =
0211         RREG32(TCI_MCLK_PWRMGT_CNTL);
0212     pi->clk_regs.rv730.dll_cntl =
0213         RREG32(TCI_DLL_CNTL);
0214     pi->clk_regs.rv730.mpll_func_cntl =
0215         RREG32(CG_MPLL_FUNC_CNTL);
0216     pi->clk_regs.rv730.mpll_func_cntl2 =
0217         RREG32(CG_MPLL_FUNC_CNTL_2);
0218     pi->clk_regs.rv730.mpll_func_cntl3 =
0219         RREG32(CG_MPLL_FUNC_CNTL_3);
0220     pi->clk_regs.rv730.mpll_ss =
0221         RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM);
0222     pi->clk_regs.rv730.mpll_ss2 =
0223         RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM_2);
0224 }
0225 
0226 int rv730_populate_smc_acpi_state(struct radeon_device *rdev,
0227                   RV770_SMC_STATETABLE *table)
0228 {
0229     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
0230     u32 mpll_func_cntl = 0;
0231     u32 mpll_func_cntl_2 = 0 ;
0232     u32 mpll_func_cntl_3 = 0;
0233     u32 mclk_pwrmgt_cntl;
0234     u32 dll_cntl;
0235     u32 spll_func_cntl;
0236     u32 spll_func_cntl_2;
0237     u32 spll_func_cntl_3;
0238 
0239     table->ACPIState = table->initialState;
0240     table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
0241 
0242     if (pi->acpi_vddc) {
0243         rv770_populate_vddc_value(rdev, pi->acpi_vddc,
0244                       &table->ACPIState.levels[0].vddc);
0245         table->ACPIState.levels[0].gen2PCIE = pi->pcie_gen2 ?
0246             pi->acpi_pcie_gen2 : 0;
0247         table->ACPIState.levels[0].gen2XSP =
0248             pi->acpi_pcie_gen2;
0249     } else {
0250         rv770_populate_vddc_value(rdev, pi->min_vddc_in_table,
0251                       &table->ACPIState.levels[0].vddc);
0252         table->ACPIState.levels[0].gen2PCIE = 0;
0253     }
0254 
0255     mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl;
0256     mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2;
0257     mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3;
0258 
0259     mpll_func_cntl |= MPLL_RESET | MPLL_BYPASS_EN;
0260     mpll_func_cntl &= ~MPLL_SLEEP;
0261 
0262     mpll_func_cntl_2 &= ~MCLK_MUX_SEL_MASK;
0263     mpll_func_cntl_2 |= MCLK_MUX_SEL(1);
0264 
0265     mclk_pwrmgt_cntl = (MRDCKA_RESET |
0266                 MRDCKB_RESET |
0267                 MRDCKC_RESET |
0268                 MRDCKD_RESET |
0269                 MRDCKE_RESET |
0270                 MRDCKF_RESET |
0271                 MRDCKG_RESET |
0272                 MRDCKH_RESET |
0273                 MRDCKA_SLEEP |
0274                 MRDCKB_SLEEP |
0275                 MRDCKC_SLEEP |
0276                 MRDCKD_SLEEP |
0277                 MRDCKE_SLEEP |
0278                 MRDCKF_SLEEP |
0279                 MRDCKG_SLEEP |
0280                 MRDCKH_SLEEP);
0281 
0282     dll_cntl = 0xff000000;
0283 
0284     spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl;
0285     spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2;
0286     spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3;
0287 
0288     spll_func_cntl |= SPLL_RESET | SPLL_BYPASS_EN;
0289     spll_func_cntl &= ~SPLL_SLEEP;
0290 
0291     spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
0292     spll_func_cntl_2 |= SCLK_MUX_SEL(4);
0293 
0294     table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
0295     table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2);
0296     table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3);
0297     table->ACPIState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
0298     table->ACPIState.levels[0].mclk.mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl);
0299 
0300     table->ACPIState.levels[0].mclk.mclk730.mclk_value = 0;
0301 
0302     table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
0303     table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
0304     table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
0305 
0306     table->ACPIState.levels[0].sclk.sclk_value = 0;
0307 
0308     rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
0309 
0310     table->ACPIState.levels[1] = table->ACPIState.levels[0];
0311     table->ACPIState.levels[2] = table->ACPIState.levels[0];
0312 
0313     return 0;
0314 }
0315 
0316 int rv730_populate_smc_initial_state(struct radeon_device *rdev,
0317                      struct radeon_ps *radeon_state,
0318                      RV770_SMC_STATETABLE *table)
0319 {
0320     struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state);
0321     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
0322     u32 a_t;
0323 
0324     table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL =
0325         cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl);
0326     table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 =
0327         cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl2);
0328     table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 =
0329         cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl3);
0330     table->initialState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL =
0331         cpu_to_be32(pi->clk_regs.rv730.mclk_pwrmgt_cntl);
0332     table->initialState.levels[0].mclk.mclk730.vDLL_CNTL =
0333         cpu_to_be32(pi->clk_regs.rv730.dll_cntl);
0334     table->initialState.levels[0].mclk.mclk730.vMPLL_SS =
0335         cpu_to_be32(pi->clk_regs.rv730.mpll_ss);
0336     table->initialState.levels[0].mclk.mclk730.vMPLL_SS2 =
0337         cpu_to_be32(pi->clk_regs.rv730.mpll_ss2);
0338 
0339     table->initialState.levels[0].mclk.mclk730.mclk_value =
0340         cpu_to_be32(initial_state->low.mclk);
0341 
0342     table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
0343         cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl);
0344     table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
0345         cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_2);
0346     table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
0347         cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_3);
0348     table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
0349         cpu_to_be32(pi->clk_regs.rv730.cg_spll_spread_spectrum);
0350     table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
0351         cpu_to_be32(pi->clk_regs.rv730.cg_spll_spread_spectrum_2);
0352 
0353     table->initialState.levels[0].sclk.sclk_value =
0354         cpu_to_be32(initial_state->low.sclk);
0355 
0356     table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
0357 
0358     table->initialState.levels[0].seqValue =
0359         rv770_get_seq_value(rdev, &initial_state->low);
0360 
0361     rv770_populate_vddc_value(rdev,
0362                   initial_state->low.vddc,
0363                   &table->initialState.levels[0].vddc);
0364     rv770_populate_initial_mvdd_value(rdev,
0365                       &table->initialState.levels[0].mvdd);
0366 
0367     a_t = CG_R(0xffff) | CG_L(0);
0368 
0369     table->initialState.levels[0].aT = cpu_to_be32(a_t);
0370 
0371     table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
0372 
0373     if (pi->boot_in_gen2)
0374         table->initialState.levels[0].gen2PCIE = 1;
0375     else
0376         table->initialState.levels[0].gen2PCIE = 0;
0377     if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
0378         table->initialState.levels[0].gen2XSP = 1;
0379     else
0380         table->initialState.levels[0].gen2XSP = 0;
0381 
0382     table->initialState.levels[1] = table->initialState.levels[0];
0383     table->initialState.levels[2] = table->initialState.levels[0];
0384 
0385     table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
0386 
0387     return 0;
0388 }
0389 
0390 void rv730_program_memory_timing_parameters(struct radeon_device *rdev,
0391                         struct radeon_ps *radeon_state)
0392 {
0393     struct rv7xx_ps *state = rv770_get_ps(radeon_state);
0394     u32 arb_refresh_rate = 0;
0395     u32 dram_timing = 0;
0396     u32 dram_timing2 = 0;
0397     u32 old_dram_timing = 0;
0398     u32 old_dram_timing2 = 0;
0399 
0400     arb_refresh_rate = RREG32(MC_ARB_RFSH_RATE) &
0401         ~(POWERMODE1_MASK | POWERMODE2_MASK | POWERMODE3_MASK);
0402     arb_refresh_rate |=
0403         (POWERMODE1(rv770_calculate_memory_refresh_rate(rdev, state->low.sclk)) |
0404          POWERMODE2(rv770_calculate_memory_refresh_rate(rdev, state->medium.sclk)) |
0405          POWERMODE3(rv770_calculate_memory_refresh_rate(rdev, state->high.sclk)));
0406     WREG32(MC_ARB_RFSH_RATE, arb_refresh_rate);
0407 
0408     /* save the boot dram timings */
0409     old_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
0410     old_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
0411 
0412     radeon_atom_set_engine_dram_timings(rdev,
0413                         state->high.sclk,
0414                         state->high.mclk);
0415 
0416     dram_timing = RREG32(MC_ARB_DRAM_TIMING);
0417     dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
0418 
0419     WREG32(MC_ARB_DRAM_TIMING_3, dram_timing);
0420     WREG32(MC_ARB_DRAM_TIMING2_3, dram_timing2);
0421 
0422     radeon_atom_set_engine_dram_timings(rdev,
0423                         state->medium.sclk,
0424                         state->medium.mclk);
0425 
0426     dram_timing = RREG32(MC_ARB_DRAM_TIMING);
0427     dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
0428 
0429     WREG32(MC_ARB_DRAM_TIMING_2, dram_timing);
0430     WREG32(MC_ARB_DRAM_TIMING2_2, dram_timing2);
0431 
0432     radeon_atom_set_engine_dram_timings(rdev,
0433                         state->low.sclk,
0434                         state->low.mclk);
0435 
0436     dram_timing = RREG32(MC_ARB_DRAM_TIMING);
0437     dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
0438 
0439     WREG32(MC_ARB_DRAM_TIMING_1, dram_timing);
0440     WREG32(MC_ARB_DRAM_TIMING2_1, dram_timing2);
0441 
0442     /* restore the boot dram timings */
0443     WREG32(MC_ARB_DRAM_TIMING, old_dram_timing);
0444     WREG32(MC_ARB_DRAM_TIMING2, old_dram_timing2);
0445 
0446 }
0447 
0448 void rv730_start_dpm(struct radeon_device *rdev)
0449 {
0450     WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
0451 
0452     WREG32_P(TCI_MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
0453 
0454     WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
0455 }
0456 
0457 void rv730_stop_dpm(struct radeon_device *rdev)
0458 {
0459     PPSMC_Result result;
0460 
0461     result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_TwoLevelsDisabled);
0462 
0463     if (result != PPSMC_Result_OK)
0464         DRM_DEBUG("Could not force DPM to low\n");
0465 
0466     WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
0467 
0468     WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
0469 
0470     WREG32_P(TCI_MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
0471 }
0472 
0473 void rv730_program_dcodt(struct radeon_device *rdev, bool use_dcodt)
0474 {
0475     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
0476     u32 i = use_dcodt ? 0 : 1;
0477     u32 mc4_io_pad_cntl;
0478 
0479     mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0);
0480     mc4_io_pad_cntl &= 0xFFFFFF00;
0481     mc4_io_pad_cntl |= pi->odt_value_0[i];
0482     WREG32(MC4_IO_DQ_PAD_CNTL_D0_I0, mc4_io_pad_cntl);
0483     WREG32(MC4_IO_DQ_PAD_CNTL_D0_I1, mc4_io_pad_cntl);
0484 
0485     mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0);
0486     mc4_io_pad_cntl &= 0xFFFFFF00;
0487     mc4_io_pad_cntl |= pi->odt_value_1[i];
0488     WREG32(MC4_IO_QS_PAD_CNTL_D0_I0, mc4_io_pad_cntl);
0489     WREG32(MC4_IO_QS_PAD_CNTL_D0_I1, mc4_io_pad_cntl);
0490 }
0491 
0492 void rv730_get_odt_values(struct radeon_device *rdev)
0493 {
0494     struct rv7xx_power_info *pi = rv770_get_pi(rdev);
0495     u32 mc4_io_pad_cntl;
0496 
0497     pi->odt_value_0[0] = (u8)0;
0498     pi->odt_value_1[0] = (u8)0x80;
0499 
0500     mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0);
0501     pi->odt_value_0[1] = (u8)(mc4_io_pad_cntl & 0xff);
0502 
0503     mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0);
0504     pi->odt_value_1[1] = (u8)(mc4_io_pad_cntl & 0xff);
0505 }
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