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0001 /*
0002  * Copyright 2011 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef RV6XXD_H
0024 #define RV6XXD_H
0025 
0026 /* RV6xx power management */
0027 #define SPLL_CNTL_MODE                                    0x60c
0028 #       define SPLL_DIV_SYNC                              (1 << 5)
0029 
0030 #define GENERAL_PWRMGT                                    0x618
0031 #       define GLOBAL_PWRMGT_EN                           (1 << 0)
0032 #       define STATIC_PM_EN                               (1 << 1)
0033 #       define MOBILE_SU                                  (1 << 2)
0034 #       define THERMAL_PROTECTION_DIS                     (1 << 3)
0035 #       define THERMAL_PROTECTION_TYPE                    (1 << 4)
0036 #       define ENABLE_GEN2PCIE                            (1 << 5)
0037 #       define SW_GPIO_INDEX(x)                           ((x) << 6)
0038 #       define SW_GPIO_INDEX_MASK                         (3 << 6)
0039 #       define LOW_VOLT_D2_ACPI                           (1 << 8)
0040 #       define LOW_VOLT_D3_ACPI                           (1 << 9)
0041 #       define VOLT_PWRMGT_EN                             (1 << 10)
0042 #       define BACKBIAS_PAD_EN                            (1 << 16)
0043 #       define BACKBIAS_VALUE                             (1 << 17)
0044 #       define BACKBIAS_DPM_CNTL                          (1 << 18)
0045 #       define DYN_SPREAD_SPECTRUM_EN                     (1 << 21)
0046 
0047 #define MCLK_PWRMGT_CNTL                                  0x624
0048 #       define MPLL_PWRMGT_OFF                            (1 << 0)
0049 #       define YCLK_TURNOFF                               (1 << 1)
0050 #       define MPLL_TURNOFF                               (1 << 2)
0051 #       define SU_MCLK_USE_BCLK                           (1 << 3)
0052 #       define DLL_READY                                  (1 << 4)
0053 #       define MC_BUSY                                    (1 << 5)
0054 #       define MC_INT_CNTL                                (1 << 7)
0055 #       define MRDCKA_SLEEP                               (1 << 8)
0056 #       define MRDCKB_SLEEP                               (1 << 9)
0057 #       define MRDCKC_SLEEP                               (1 << 10)
0058 #       define MRDCKD_SLEEP                               (1 << 11)
0059 #       define MRDCKE_SLEEP                               (1 << 12)
0060 #       define MRDCKF_SLEEP                               (1 << 13)
0061 #       define MRDCKG_SLEEP                               (1 << 14)
0062 #       define MRDCKH_SLEEP                               (1 << 15)
0063 #       define MRDCKA_RESET                               (1 << 16)
0064 #       define MRDCKB_RESET                               (1 << 17)
0065 #       define MRDCKC_RESET                               (1 << 18)
0066 #       define MRDCKD_RESET                               (1 << 19)
0067 #       define MRDCKE_RESET                               (1 << 20)
0068 #       define MRDCKF_RESET                               (1 << 21)
0069 #       define MRDCKG_RESET                               (1 << 22)
0070 #       define MRDCKH_RESET                               (1 << 23)
0071 #       define DLL_READY_READ                             (1 << 24)
0072 #       define USE_DISPLAY_GAP                            (1 << 25)
0073 #       define USE_DISPLAY_URGENT_NORMAL                  (1 << 26)
0074 #       define USE_DISPLAY_GAP_CTXSW                      (1 << 27)
0075 #       define MPLL_TURNOFF_D2                            (1 << 28)
0076 #       define USE_DISPLAY_URGENT_CTXSW                   (1 << 29)
0077 
0078 #define MPLL_FREQ_LEVEL_0                                 0x6e8
0079 #       define LEVEL0_MPLL_POST_DIV(x)                    ((x) << 0)
0080 #       define LEVEL0_MPLL_POST_DIV_MASK                  (0xff << 0)
0081 #       define LEVEL0_MPLL_FB_DIV(x)                      ((x) << 8)
0082 #       define LEVEL0_MPLL_FB_DIV_MASK                    (0xfff << 8)
0083 #       define LEVEL0_MPLL_REF_DIV(x)                     ((x) << 20)
0084 #       define LEVEL0_MPLL_REF_DIV_MASK                   (0x3f << 20)
0085 #       define LEVEL0_MPLL_DIV_EN                         (1 << 28)
0086 #       define LEVEL0_DLL_BYPASS                          (1 << 29)
0087 #       define LEVEL0_DLL_RESET                           (1 << 30)
0088 
0089 #define VID_RT                                            0x6f8
0090 #       define VID_CRT(x)                                 ((x) << 0)
0091 #       define VID_CRT_MASK                               (0x1fff << 0)
0092 #       define VID_CRTU(x)                                ((x) << 13)
0093 #       define VID_CRTU_MASK                              (7 << 13)
0094 #       define SSTU(x)                                    ((x) << 16)
0095 #       define SSTU_MASK                                  (7 << 16)
0096 #       define VID_SWT(x)                                 ((x) << 19)
0097 #       define VID_SWT_MASK                               (0x1f << 19)
0098 #       define BRT(x)                                     ((x) << 24)
0099 #       define BRT_MASK                                   (0xff << 24)
0100 
0101 #define TARGET_AND_CURRENT_PROFILE_INDEX                  0x70c
0102 #       define TARGET_PROFILE_INDEX_MASK                  (3 << 0)
0103 #       define TARGET_PROFILE_INDEX_SHIFT                 0
0104 #       define CURRENT_PROFILE_INDEX_MASK                 (3 << 2)
0105 #       define CURRENT_PROFILE_INDEX_SHIFT                2
0106 #       define DYN_PWR_ENTER_INDEX(x)                     ((x) << 4)
0107 #       define DYN_PWR_ENTER_INDEX_MASK                   (3 << 4)
0108 #       define DYN_PWR_ENTER_INDEX_SHIFT                  4
0109 #       define CURR_MCLK_INDEX_MASK                       (3 << 6)
0110 #       define CURR_MCLK_INDEX_SHIFT                      6
0111 #       define CURR_SCLK_INDEX_MASK                       (0x1f << 8)
0112 #       define CURR_SCLK_INDEX_SHIFT                      8
0113 #       define CURR_VID_INDEX_MASK                        (3 << 13)
0114 #       define CURR_VID_INDEX_SHIFT                       13
0115 
0116 #define VID_UPPER_GPIO_CNTL                               0x740
0117 #       define CTXSW_UPPER_GPIO_VALUES(x)                 ((x) << 0)
0118 #       define CTXSW_UPPER_GPIO_VALUES_MASK               (7 << 0)
0119 #       define HIGH_UPPER_GPIO_VALUES(x)                  ((x) << 3)
0120 #       define HIGH_UPPER_GPIO_VALUES_MASK                (7 << 3)
0121 #       define MEDIUM_UPPER_GPIO_VALUES(x)                ((x) << 6)
0122 #       define MEDIUM_UPPER_GPIO_VALUES_MASK              (7 << 6)
0123 #       define LOW_UPPER_GPIO_VALUES(x)                   ((x) << 9)
0124 #       define LOW_UPPER_GPIO_VALUES_MASK                 (7 << 9)
0125 #       define CTXSW_BACKBIAS_VALUE                       (1 << 12)
0126 #       define HIGH_BACKBIAS_VALUE                        (1 << 13)
0127 #       define MEDIUM_BACKBIAS_VALUE                      (1 << 14)
0128 #       define LOW_BACKBIAS_VALUE                         (1 << 15)
0129 
0130 #define CG_DISPLAY_GAP_CNTL                               0x7dc
0131 #       define DISP1_GAP(x)                               ((x) << 0)
0132 #       define DISP1_GAP_MASK                             (3 << 0)
0133 #       define DISP2_GAP(x)                               ((x) << 2)
0134 #       define DISP2_GAP_MASK                             (3 << 2)
0135 #       define VBI_TIMER_COUNT(x)                         ((x) << 4)
0136 #       define VBI_TIMER_COUNT_MASK                       (0x3fff << 4)
0137 #       define VBI_TIMER_UNIT(x)                          ((x) << 20)
0138 #       define VBI_TIMER_UNIT_MASK                        (7 << 20)
0139 #       define DISP1_GAP_MCHG(x)                          ((x) << 24)
0140 #       define DISP1_GAP_MCHG_MASK                        (3 << 24)
0141 #       define DISP2_GAP_MCHG(x)                          ((x) << 26)
0142 #       define DISP2_GAP_MCHG_MASK                        (3 << 26)
0143 
0144 #define CG_THERMAL_CTRL                                   0x7f0
0145 #       define DPM_EVENT_SRC(x)                           ((x) << 0)
0146 #       define DPM_EVENT_SRC_MASK                         (7 << 0)
0147 #       define THERM_INC_CLK                              (1 << 3)
0148 #       define TOFFSET(x)                                 ((x) << 4)
0149 #       define TOFFSET_MASK                               (0xff << 4)
0150 #       define DIG_THERM_DPM(x)                           ((x) << 12)
0151 #       define DIG_THERM_DPM_MASK                         (0xff << 12)
0152 #       define CTF_SEL(x)                                 ((x) << 20)
0153 #       define CTF_SEL_MASK                               (7 << 20)
0154 #       define CTF_PAD_POLARITY                           (1 << 23)
0155 #       define CTF_PAD_EN                                 (1 << 24)
0156 
0157 #define CG_SPLL_SPREAD_SPECTRUM_LOW                       0x820
0158 #       define SSEN                                       (1 << 0)
0159 #       define CLKS(x)                                    ((x) << 3)
0160 #       define CLKS_MASK                                  (0xff << 3)
0161 #       define CLKS_SHIFT                                 3
0162 #       define CLKV(x)                                    ((x) << 11)
0163 #       define CLKV_MASK                                  (0x7ff << 11)
0164 #       define CLKV_SHIFT                                 11
0165 #define CG_MPLL_SPREAD_SPECTRUM                           0x830
0166 
0167 #define CITF_CNTL                   0x200c
0168 #       define BLACKOUT_RD                              (1 << 0)
0169 #       define BLACKOUT_WR                              (1 << 1)
0170 
0171 #define RAMCFG                      0x2408
0172 #define     NOOFBANK_SHIFT                  0
0173 #define     NOOFBANK_MASK                   0x00000001
0174 #define     NOOFRANK_SHIFT                  1
0175 #define     NOOFRANK_MASK                   0x00000002
0176 #define     NOOFROWS_SHIFT                  2
0177 #define     NOOFROWS_MASK                   0x0000001C
0178 #define     NOOFCOLS_SHIFT                  5
0179 #define     NOOFCOLS_MASK                   0x00000060
0180 #define     CHANSIZE_SHIFT                  7
0181 #define     CHANSIZE_MASK                   0x00000080
0182 #define     BURSTLENGTH_SHIFT               8
0183 #define     BURSTLENGTH_MASK                0x00000100
0184 #define     CHANSIZE_OVERRIDE               (1 << 10)
0185 
0186 #define SQM_RATIO                   0x2424
0187 #       define STATE0(x)                                ((x) << 0)
0188 #       define STATE0_MASK                              (0xff << 0)
0189 #       define STATE1(x)                                ((x) << 8)
0190 #       define STATE1_MASK                              (0xff << 8)
0191 #       define STATE2(x)                                ((x) << 16)
0192 #       define STATE2_MASK                              (0xff << 16)
0193 #       define STATE3(x)                                ((x) << 24)
0194 #       define STATE3_MASK                              (0xff << 24)
0195 
0196 #define ARB_RFSH_CNTL                   0x2460
0197 #       define ENABLE                                   (1 << 0)
0198 #define ARB_RFSH_RATE                   0x2464
0199 #       define POWERMODE0(x)                            ((x) << 0)
0200 #       define POWERMODE0_MASK                          (0xff << 0)
0201 #       define POWERMODE1(x)                            ((x) << 8)
0202 #       define POWERMODE1_MASK                          (0xff << 8)
0203 #       define POWERMODE2(x)                            ((x) << 16)
0204 #       define POWERMODE2_MASK                          (0xff << 16)
0205 #       define POWERMODE3(x)                            ((x) << 24)
0206 #       define POWERMODE3_MASK                          (0xff << 24)
0207 
0208 #define MC_SEQ_DRAM                 0x2608
0209 #       define CKE_DYN                                  (1 << 12)
0210 
0211 #define MC_SEQ_CMD                  0x26c4
0212 
0213 #define MC_SEQ_RESERVE_S                0x2890
0214 #define MC_SEQ_RESERVE_M                0x2894
0215 
0216 #define LVTMA_DATA_SYNCHRONIZATION                      0x7adc
0217 #       define LVTMA_PFREQCHG                           (1 << 8)
0218 #define DCE3_LVTMA_DATA_SYNCHRONIZATION                 0x7f98
0219 
0220 /* PCIE indirect regs */
0221 #define PCIE_P_CNTL                                       0x40
0222 #       define P_PLL_PWRDN_IN_L1L23                       (1 << 3)
0223 #       define P_PLL_BUF_PDNB                             (1 << 4)
0224 #       define P_PLL_PDNB                                 (1 << 9)
0225 #       define P_ALLOW_PRX_FRONTEND_SHUTOFF               (1 << 12)
0226 /* PCIE PORT indirect regs */
0227 #define PCIE_LC_CNTL                                      0xa0
0228 #       define LC_L0S_INACTIVITY(x)                       ((x) << 8)
0229 #       define LC_L0S_INACTIVITY_MASK                     (0xf << 8)
0230 #       define LC_L0S_INACTIVITY_SHIFT                    8
0231 #       define LC_L1_INACTIVITY(x)                        ((x) << 12)
0232 #       define LC_L1_INACTIVITY_MASK                      (0xf << 12)
0233 #       define LC_L1_INACTIVITY_SHIFT                     12
0234 #       define LC_PMI_TO_L1_DIS                           (1 << 16)
0235 #       define LC_ASPM_TO_L1_DIS                          (1 << 24)
0236 #define PCIE_LC_SPEED_CNTL                                0xa4
0237 #       define LC_GEN2_EN                                 (1 << 0)
0238 #       define LC_INITIATE_LINK_SPEED_CHANGE              (1 << 7)
0239 #       define LC_CURRENT_DATA_RATE                       (1 << 11)
0240 #       define LC_HW_VOLTAGE_IF_CONTROL(x)                ((x) << 12)
0241 #       define LC_HW_VOLTAGE_IF_CONTROL_MASK              (3 << 12)
0242 #       define LC_HW_VOLTAGE_IF_CONTROL_SHIFT             12
0243 #       define LC_OTHER_SIDE_EVER_SENT_GEN2               (1 << 23)
0244 #       define LC_OTHER_SIDE_SUPPORTS_GEN2                (1 << 24)
0245 
0246 #endif
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