drm/radeon/rv6xx_dpm.h

0001 /*
0002  * Copyright 2011 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Alex Deucher
0023  */
0024
0025 #ifndef __RV6XX_DPM_H__
0026 #define __RV6XX_DPM_H__
0027
0028 #include "r600_dpm.h"
0029
0030 /* Represents a single SCLK step. */
0031 struct rv6xx_sclk_stepping
0032 {
0033     u32 vco_frequency;
0034     u32 post_divider;
0035 };
0036
0037 struct rv6xx_pm_hw_state {
0038     u32 sclks[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
0039     u32 mclks[R600_PM_NUMBER_OF_MCLKS];
0040     u16 vddc[R600_PM_NUMBER_OF_VOLTAGE_LEVELS];
0041     bool backbias[R600_PM_NUMBER_OF_VOLTAGE_LEVELS];
0042     bool pcie_gen2[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
0043     u8 high_sclk_index;
0044     u8 medium_sclk_index;
0045     u8 low_sclk_index;
0046     u8 high_mclk_index;
0047     u8 medium_mclk_index;
0048     u8 low_mclk_index;
0049     u8 high_vddc_index;
0050     u8 medium_vddc_index;
0051     u8 low_vddc_index;
0052     u8 rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
0053     u8 lp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
0054 };
0055
0056 struct rv6xx_power_info {
0057     /* flags */
0058     bool voltage_control;
0059     bool sclk_ss;
0060     bool mclk_ss;
0061     bool dynamic_ss;
0062     bool dynamic_pcie_gen2;
0063     bool thermal_protection;
0064     bool display_gap;
0065     bool gfx_clock_gating;
0066     /* clk values */
0067     u32 fb_div_scale;
0068     u32 spll_ref_div;
0069     u32 mpll_ref_div;
0070     u32 bsu;
0071     u32 bsp;
0072     /* */
0073     u32 active_auto_throttle_sources;
0074     /* current power state */
0075     u32 restricted_levels;
0076     struct rv6xx_pm_hw_state hw;
0077 };
0078
0079 struct rv6xx_pl {
0080     u32 sclk;
0081     u32 mclk;
0082     u16 vddc;
0083     u32 flags;
0084 };
0085
0086 struct rv6xx_ps {
0087     struct rv6xx_pl high;
0088     struct rv6xx_pl medium;
0089     struct rv6xx_pl low;
0090 };
0091
0092 #define RV6XX_DEFAULT_VCLK_FREQ  40000 /* 10 khz */
0093 #define RV6XX_DEFAULT_DCLK_FREQ  30000 /* 10 khz */
0094
0095 #endif