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0001 /*
0002  * Copyright 2011 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Alex Deucher
0023  */
0024 
0025 #include "radeon.h"
0026 #include "radeon_asic.h"
0027 #include "rv6xxd.h"
0028 #include "r600_dpm.h"
0029 #include "rv6xx_dpm.h"
0030 #include "atom.h"
0031 #include <linux/seq_file.h>
0032 
0033 static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,
0034                     u32 unscaled_count, u32 unit);
0035 
0036 static struct rv6xx_ps *rv6xx_get_ps(struct radeon_ps *rps)
0037 {
0038     struct rv6xx_ps *ps = rps->ps_priv;
0039 
0040     return ps;
0041 }
0042 
0043 static struct rv6xx_power_info *rv6xx_get_pi(struct radeon_device *rdev)
0044 {
0045     struct rv6xx_power_info *pi = rdev->pm.dpm.priv;
0046 
0047     return pi;
0048 }
0049 
0050 static void rv6xx_force_pcie_gen1(struct radeon_device *rdev)
0051 {
0052     u32 tmp;
0053     int i;
0054 
0055     tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
0056     tmp &= LC_GEN2_EN;
0057     WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
0058 
0059     tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
0060     tmp |= LC_INITIATE_LINK_SPEED_CHANGE;
0061     WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
0062 
0063     for (i = 0; i < rdev->usec_timeout; i++) {
0064         if (!(RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE))
0065             break;
0066         udelay(1);
0067     }
0068 
0069     tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
0070     tmp &= ~LC_INITIATE_LINK_SPEED_CHANGE;
0071     WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
0072 }
0073 
0074 static void rv6xx_enable_pcie_gen2_support(struct radeon_device *rdev)
0075 {
0076     u32 tmp;
0077 
0078     tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
0079 
0080     if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
0081         (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
0082         tmp |= LC_GEN2_EN;
0083         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
0084     }
0085 }
0086 
0087 static void rv6xx_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
0088                            bool enable)
0089 {
0090     u32 tmp;
0091 
0092     tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
0093     if (enable)
0094         tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
0095     else
0096         tmp |= LC_HW_VOLTAGE_IF_CONTROL(0);
0097     WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
0098 }
0099 
0100 static void rv6xx_enable_l0s(struct radeon_device *rdev)
0101 {
0102     u32 tmp;
0103 
0104     tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L0S_INACTIVITY_MASK;
0105     tmp |= LC_L0S_INACTIVITY(3);
0106     WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
0107 }
0108 
0109 static void rv6xx_enable_l1(struct radeon_device *rdev)
0110 {
0111     u32 tmp;
0112 
0113     tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL);
0114     tmp &= ~LC_L1_INACTIVITY_MASK;
0115     tmp |= LC_L1_INACTIVITY(4);
0116     tmp &= ~LC_PMI_TO_L1_DIS;
0117     tmp &= ~LC_ASPM_TO_L1_DIS;
0118     WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
0119 }
0120 
0121 static void rv6xx_enable_pll_sleep_in_l1(struct radeon_device *rdev)
0122 {
0123     u32 tmp;
0124 
0125     tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L1_INACTIVITY_MASK;
0126     tmp |= LC_L1_INACTIVITY(8);
0127     WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
0128 
0129     /* NOTE, this is a PCIE indirect reg, not PCIE PORT */
0130     tmp = RREG32_PCIE(PCIE_P_CNTL);
0131     tmp |= P_PLL_PWRDN_IN_L1L23;
0132     tmp &= ~P_PLL_BUF_PDNB;
0133     tmp &= ~P_PLL_PDNB;
0134     tmp |= P_ALLOW_PRX_FRONTEND_SHUTOFF;
0135     WREG32_PCIE(PCIE_P_CNTL, tmp);
0136 }
0137 
0138 static int rv6xx_convert_clock_to_stepping(struct radeon_device *rdev,
0139                        u32 clock, struct rv6xx_sclk_stepping *step)
0140 {
0141     int ret;
0142     struct atom_clock_dividers dividers;
0143 
0144     ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
0145                          clock, false, &dividers);
0146     if (ret)
0147         return ret;
0148 
0149     if (dividers.enable_post_div)
0150         step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4);
0151     else
0152         step->post_divider = 1;
0153 
0154     step->vco_frequency = clock * step->post_divider;
0155 
0156     return 0;
0157 }
0158 
0159 static void rv6xx_output_stepping(struct radeon_device *rdev,
0160                   u32 step_index, struct rv6xx_sclk_stepping *step)
0161 {
0162     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
0163     u32 ref_clk = rdev->clock.spll.reference_freq;
0164     u32 fb_divider;
0165     u32 spll_step_count = rv6xx_scale_count_given_unit(rdev,
0166                                R600_SPLLSTEPTIME_DFLT *
0167                                pi->spll_ref_div,
0168                                R600_SPLLSTEPUNIT_DFLT);
0169 
0170     r600_engine_clock_entry_enable(rdev, step_index, true);
0171     r600_engine_clock_entry_enable_pulse_skipping(rdev, step_index, false);
0172 
0173     if (step->post_divider == 1)
0174         r600_engine_clock_entry_enable_post_divider(rdev, step_index, false);
0175     else {
0176         u32 lo_len = (step->post_divider - 2) / 2;
0177         u32 hi_len = step->post_divider - 2 - lo_len;
0178 
0179         r600_engine_clock_entry_enable_post_divider(rdev, step_index, true);
0180         r600_engine_clock_entry_set_post_divider(rdev, step_index, (hi_len << 4) | lo_len);
0181     }
0182 
0183     fb_divider = ((step->vco_frequency * pi->spll_ref_div) / ref_clk) >>
0184         pi->fb_div_scale;
0185 
0186     r600_engine_clock_entry_set_reference_divider(rdev, step_index,
0187                               pi->spll_ref_div - 1);
0188     r600_engine_clock_entry_set_feedback_divider(rdev, step_index, fb_divider);
0189     r600_engine_clock_entry_set_step_time(rdev, step_index, spll_step_count);
0190 
0191 }
0192 
0193 static struct rv6xx_sclk_stepping rv6xx_next_vco_step(struct radeon_device *rdev,
0194                               struct rv6xx_sclk_stepping *cur,
0195                               bool increasing_vco, u32 step_size)
0196 {
0197     struct rv6xx_sclk_stepping next;
0198 
0199     next.post_divider = cur->post_divider;
0200 
0201     if (increasing_vco)
0202         next.vco_frequency = (cur->vco_frequency * (100 + step_size)) / 100;
0203     else
0204         next.vco_frequency = (cur->vco_frequency * 100 + 99 + step_size) / (100 + step_size);
0205 
0206     return next;
0207 }
0208 
0209 static bool rv6xx_can_step_post_div(struct radeon_device *rdev,
0210                     struct rv6xx_sclk_stepping *cur,
0211                     struct rv6xx_sclk_stepping *target)
0212 {
0213     return (cur->post_divider > target->post_divider) &&
0214         ((cur->vco_frequency * target->post_divider) <=
0215          (target->vco_frequency * (cur->post_divider - 1)));
0216 }
0217 
0218 static struct rv6xx_sclk_stepping rv6xx_next_post_div_step(struct radeon_device *rdev,
0219                                struct rv6xx_sclk_stepping *cur,
0220                                struct rv6xx_sclk_stepping *target)
0221 {
0222     struct rv6xx_sclk_stepping next = *cur;
0223 
0224     while (rv6xx_can_step_post_div(rdev, &next, target))
0225         next.post_divider--;
0226 
0227     return next;
0228 }
0229 
0230 static bool rv6xx_reached_stepping_target(struct radeon_device *rdev,
0231                       struct rv6xx_sclk_stepping *cur,
0232                       struct rv6xx_sclk_stepping *target,
0233                       bool increasing_vco)
0234 {
0235     return (increasing_vco && (cur->vco_frequency >= target->vco_frequency)) ||
0236         (!increasing_vco && (cur->vco_frequency <= target->vco_frequency));
0237 }
0238 
0239 static void rv6xx_generate_steps(struct radeon_device *rdev,
0240                  u32 low, u32 high,
0241                  u32 start_index, u8 *end_index)
0242 {
0243     struct rv6xx_sclk_stepping cur;
0244     struct rv6xx_sclk_stepping target;
0245     bool increasing_vco;
0246     u32 step_index = start_index;
0247 
0248     rv6xx_convert_clock_to_stepping(rdev, low, &cur);
0249     rv6xx_convert_clock_to_stepping(rdev, high, &target);
0250 
0251     rv6xx_output_stepping(rdev, step_index++, &cur);
0252 
0253     increasing_vco = (target.vco_frequency >= cur.vco_frequency);
0254 
0255     if (target.post_divider > cur.post_divider)
0256         cur.post_divider = target.post_divider;
0257 
0258     while (1) {
0259         struct rv6xx_sclk_stepping next;
0260 
0261         if (rv6xx_can_step_post_div(rdev, &cur, &target))
0262             next = rv6xx_next_post_div_step(rdev, &cur, &target);
0263         else
0264             next = rv6xx_next_vco_step(rdev, &cur, increasing_vco, R600_VCOSTEPPCT_DFLT);
0265 
0266         if (rv6xx_reached_stepping_target(rdev, &next, &target, increasing_vco)) {
0267             struct rv6xx_sclk_stepping tiny =
0268                 rv6xx_next_vco_step(rdev, &target, !increasing_vco, R600_ENDINGVCOSTEPPCT_DFLT);
0269             tiny.post_divider = next.post_divider;
0270 
0271             if (!rv6xx_reached_stepping_target(rdev, &tiny, &cur, !increasing_vco))
0272                 rv6xx_output_stepping(rdev, step_index++, &tiny);
0273 
0274             if ((next.post_divider != target.post_divider) &&
0275                 (next.vco_frequency != target.vco_frequency)) {
0276                 struct rv6xx_sclk_stepping final_vco;
0277 
0278                 final_vco.vco_frequency = target.vco_frequency;
0279                 final_vco.post_divider = next.post_divider;
0280 
0281                 rv6xx_output_stepping(rdev, step_index++, &final_vco);
0282             }
0283 
0284             rv6xx_output_stepping(rdev, step_index++, &target);
0285             break;
0286         } else
0287             rv6xx_output_stepping(rdev, step_index++, &next);
0288 
0289         cur = next;
0290     }
0291 
0292     *end_index = (u8)step_index - 1;
0293 
0294 }
0295 
0296 static void rv6xx_generate_single_step(struct radeon_device *rdev,
0297                        u32 clock, u32 index)
0298 {
0299     struct rv6xx_sclk_stepping step;
0300 
0301     rv6xx_convert_clock_to_stepping(rdev, clock, &step);
0302     rv6xx_output_stepping(rdev, index, &step);
0303 }
0304 
0305 static void rv6xx_invalidate_intermediate_steps_range(struct radeon_device *rdev,
0306                               u32 start_index, u32 end_index)
0307 {
0308     u32 step_index;
0309 
0310     for (step_index = start_index + 1; step_index < end_index; step_index++)
0311         r600_engine_clock_entry_enable(rdev, step_index, false);
0312 }
0313 
0314 static void rv6xx_set_engine_spread_spectrum_clk_s(struct radeon_device *rdev,
0315                            u32 index, u32 clk_s)
0316 {
0317     WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
0318          CLKS(clk_s), ~CLKS_MASK);
0319 }
0320 
0321 static void rv6xx_set_engine_spread_spectrum_clk_v(struct radeon_device *rdev,
0322                            u32 index, u32 clk_v)
0323 {
0324     WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
0325          CLKV(clk_v), ~CLKV_MASK);
0326 }
0327 
0328 static void rv6xx_enable_engine_spread_spectrum(struct radeon_device *rdev,
0329                         u32 index, bool enable)
0330 {
0331     if (enable)
0332         WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
0333              SSEN, ~SSEN);
0334     else
0335         WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
0336              0, ~SSEN);
0337 }
0338 
0339 static void rv6xx_set_memory_spread_spectrum_clk_s(struct radeon_device *rdev,
0340                            u32 clk_s)
0341 {
0342     WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_s), ~CLKS_MASK);
0343 }
0344 
0345 static void rv6xx_set_memory_spread_spectrum_clk_v(struct radeon_device *rdev,
0346                            u32 clk_v)
0347 {
0348     WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKV(clk_v), ~CLKV_MASK);
0349 }
0350 
0351 static void rv6xx_enable_memory_spread_spectrum(struct radeon_device *rdev,
0352                         bool enable)
0353 {
0354     if (enable)
0355         WREG32_P(CG_MPLL_SPREAD_SPECTRUM, SSEN, ~SSEN);
0356     else
0357         WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN);
0358 }
0359 
0360 static void rv6xx_enable_dynamic_spread_spectrum(struct radeon_device *rdev,
0361                          bool enable)
0362 {
0363     if (enable)
0364         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
0365     else
0366         WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
0367 }
0368 
0369 static void rv6xx_memory_clock_entry_enable_post_divider(struct radeon_device *rdev,
0370                              u32 index, bool enable)
0371 {
0372     if (enable)
0373         WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
0374              LEVEL0_MPLL_DIV_EN, ~LEVEL0_MPLL_DIV_EN);
0375     else
0376         WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), 0, ~LEVEL0_MPLL_DIV_EN);
0377 }
0378 
0379 static void rv6xx_memory_clock_entry_set_post_divider(struct radeon_device *rdev,
0380                               u32 index, u32 divider)
0381 {
0382     WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
0383          LEVEL0_MPLL_POST_DIV(divider), ~LEVEL0_MPLL_POST_DIV_MASK);
0384 }
0385 
0386 static void rv6xx_memory_clock_entry_set_feedback_divider(struct radeon_device *rdev,
0387                               u32 index, u32 divider)
0388 {
0389     WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider),
0390          ~LEVEL0_MPLL_FB_DIV_MASK);
0391 }
0392 
0393 static void rv6xx_memory_clock_entry_set_reference_divider(struct radeon_device *rdev,
0394                                u32 index, u32 divider)
0395 {
0396     WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
0397          LEVEL0_MPLL_REF_DIV(divider), ~LEVEL0_MPLL_REF_DIV_MASK);
0398 }
0399 
0400 static void rv6xx_vid_response_set_brt(struct radeon_device *rdev, u32 rt)
0401 {
0402     WREG32_P(VID_RT, BRT(rt), ~BRT_MASK);
0403 }
0404 
0405 static void rv6xx_enable_engine_feedback_and_reference_sync(struct radeon_device *rdev)
0406 {
0407     WREG32_P(SPLL_CNTL_MODE, SPLL_DIV_SYNC, ~SPLL_DIV_SYNC);
0408 }
0409 
0410 static u32 rv6xx_clocks_per_unit(u32 unit)
0411 {
0412     u32 tmp = 1 << (2 * unit);
0413 
0414     return tmp;
0415 }
0416 
0417 static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,
0418                     u32 unscaled_count, u32 unit)
0419 {
0420     u32 count_per_unit = rv6xx_clocks_per_unit(unit);
0421 
0422     return (unscaled_count + count_per_unit - 1) / count_per_unit;
0423 }
0424 
0425 static u32 rv6xx_compute_count_for_delay(struct radeon_device *rdev,
0426                      u32 delay_us, u32 unit)
0427 {
0428     u32 ref_clk = rdev->clock.spll.reference_freq;
0429 
0430     return rv6xx_scale_count_given_unit(rdev, delay_us * (ref_clk / 100), unit);
0431 }
0432 
0433 static void rv6xx_calculate_engine_speed_stepping_parameters(struct radeon_device *rdev,
0434                                  struct rv6xx_ps *state)
0435 {
0436     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
0437 
0438     pi->hw.sclks[R600_POWER_LEVEL_LOW] =
0439         state->low.sclk;
0440     pi->hw.sclks[R600_POWER_LEVEL_MEDIUM] =
0441         state->medium.sclk;
0442     pi->hw.sclks[R600_POWER_LEVEL_HIGH] =
0443         state->high.sclk;
0444 
0445     pi->hw.low_sclk_index = R600_POWER_LEVEL_LOW;
0446     pi->hw.medium_sclk_index = R600_POWER_LEVEL_MEDIUM;
0447     pi->hw.high_sclk_index = R600_POWER_LEVEL_HIGH;
0448 }
0449 
0450 static void rv6xx_calculate_memory_clock_stepping_parameters(struct radeon_device *rdev,
0451                                  struct rv6xx_ps *state)
0452 {
0453     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
0454 
0455     pi->hw.mclks[R600_POWER_LEVEL_CTXSW] =
0456         state->high.mclk;
0457     pi->hw.mclks[R600_POWER_LEVEL_HIGH] =
0458         state->high.mclk;
0459     pi->hw.mclks[R600_POWER_LEVEL_MEDIUM] =
0460         state->medium.mclk;
0461     pi->hw.mclks[R600_POWER_LEVEL_LOW] =
0462         state->low.mclk;
0463 
0464     pi->hw.high_mclk_index = R600_POWER_LEVEL_HIGH;
0465 
0466     if (state->high.mclk == state->medium.mclk)
0467         pi->hw.medium_mclk_index =
0468             pi->hw.high_mclk_index;
0469     else
0470         pi->hw.medium_mclk_index = R600_POWER_LEVEL_MEDIUM;
0471 
0472 
0473     if (state->medium.mclk == state->low.mclk)
0474         pi->hw.low_mclk_index =
0475             pi->hw.medium_mclk_index;
0476     else
0477         pi->hw.low_mclk_index = R600_POWER_LEVEL_LOW;
0478 }
0479 
0480 static void rv6xx_calculate_voltage_stepping_parameters(struct radeon_device *rdev,
0481                             struct rv6xx_ps *state)
0482 {
0483     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
0484 
0485     pi->hw.vddc[R600_POWER_LEVEL_CTXSW] = state->high.vddc;
0486     pi->hw.vddc[R600_POWER_LEVEL_HIGH] = state->high.vddc;
0487     pi->hw.vddc[R600_POWER_LEVEL_MEDIUM] = state->medium.vddc;
0488     pi->hw.vddc[R600_POWER_LEVEL_LOW] = state->low.vddc;
0489 
0490     pi->hw.backbias[R600_POWER_LEVEL_CTXSW] =
0491         (state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
0492     pi->hw.backbias[R600_POWER_LEVEL_HIGH] =
0493         (state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
0494     pi->hw.backbias[R600_POWER_LEVEL_MEDIUM] =
0495         (state->medium.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
0496     pi->hw.backbias[R600_POWER_LEVEL_LOW] =
0497         (state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
0498 
0499     pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH] =
0500         (state->high.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;
0501     pi->hw.pcie_gen2[R600_POWER_LEVEL_MEDIUM] =
0502         (state->medium.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;
0503     pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW] =
0504         (state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;
0505 
0506     pi->hw.high_vddc_index = R600_POWER_LEVEL_HIGH;
0507 
0508     if ((state->high.vddc == state->medium.vddc) &&
0509         ((state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ==
0510          (state->medium.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE)))
0511         pi->hw.medium_vddc_index =
0512             pi->hw.high_vddc_index;
0513     else
0514         pi->hw.medium_vddc_index = R600_POWER_LEVEL_MEDIUM;
0515 
0516     if ((state->medium.vddc == state->low.vddc) &&
0517         ((state->medium.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ==
0518          (state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE)))
0519         pi->hw.low_vddc_index =
0520             pi->hw.medium_vddc_index;
0521     else
0522         pi->hw.medium_vddc_index = R600_POWER_LEVEL_LOW;
0523 }
0524 
0525 static inline u32 rv6xx_calculate_vco_frequency(u32 ref_clock,
0526                         struct atom_clock_dividers *dividers,
0527                         u32 fb_divider_scale)
0528 {
0529     return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) /
0530         (dividers->ref_div + 1);
0531 }
0532 
0533 static inline u32 rv6xx_calculate_spread_spectrum_clk_v(u32 vco_freq, u32 ref_freq,
0534                             u32 ss_rate, u32 ss_percent,
0535                             u32 fb_divider_scale)
0536 {
0537     u32 fb_divider = vco_freq / ref_freq;
0538 
0539     return (ss_percent * ss_rate * 4 * (fb_divider * fb_divider) /
0540         (5375 * ((vco_freq * 10) / (4096 >> fb_divider_scale))));
0541 }
0542 
0543 static inline u32 rv6xx_calculate_spread_spectrum_clk_s(u32 ss_rate, u32 ref_freq)
0544 {
0545     return (((ref_freq * 10) / (ss_rate * 2)) - 1) / 4;
0546 }
0547 
0548 static void rv6xx_program_engine_spread_spectrum(struct radeon_device *rdev,
0549                          u32 clock, enum r600_power_level level)
0550 {
0551     u32 ref_clk = rdev->clock.spll.reference_freq;
0552     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
0553     struct atom_clock_dividers dividers;
0554     struct radeon_atom_ss ss;
0555     u32 vco_freq, clk_v, clk_s;
0556 
0557     rv6xx_enable_engine_spread_spectrum(rdev, level, false);
0558 
0559     if (clock && pi->sclk_ss) {
0560         if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, &dividers) == 0) {
0561             vco_freq = rv6xx_calculate_vco_frequency(ref_clk, &dividers,
0562                                  pi->fb_div_scale);
0563 
0564             if (radeon_atombios_get_asic_ss_info(rdev, &ss,
0565                                  ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
0566                 clk_v = rv6xx_calculate_spread_spectrum_clk_v(vco_freq,
0567                                           (ref_clk / (dividers.ref_div + 1)),
0568                                           ss.rate,
0569                                           ss.percentage,
0570                                           pi->fb_div_scale);
0571 
0572                 clk_s = rv6xx_calculate_spread_spectrum_clk_s(ss.rate,
0573                                           (ref_clk / (dividers.ref_div + 1)));
0574 
0575                 rv6xx_set_engine_spread_spectrum_clk_v(rdev, level, clk_v);
0576                 rv6xx_set_engine_spread_spectrum_clk_s(rdev, level, clk_s);
0577                 rv6xx_enable_engine_spread_spectrum(rdev, level, true);
0578             }
0579         }
0580     }
0581 }
0582 
0583 static void rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry(struct radeon_device *rdev)
0584 {
0585     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
0586 
0587     rv6xx_program_engine_spread_spectrum(rdev,
0588                          pi->hw.sclks[R600_POWER_LEVEL_HIGH],
0589                          R600_POWER_LEVEL_HIGH);
0590 
0591     rv6xx_program_engine_spread_spectrum(rdev,
0592                          pi->hw.sclks[R600_POWER_LEVEL_MEDIUM],
0593                          R600_POWER_LEVEL_MEDIUM);
0594 
0595 }
0596 
0597 static int rv6xx_program_mclk_stepping_entry(struct radeon_device *rdev,
0598                          u32 entry, u32 clock)
0599 {
0600     struct atom_clock_dividers dividers;
0601 
0602     if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, clock, false, &dividers))
0603         return -EINVAL;
0604 
0605 
0606     rv6xx_memory_clock_entry_set_reference_divider(rdev, entry, dividers.ref_div);
0607     rv6xx_memory_clock_entry_set_feedback_divider(rdev, entry, dividers.fb_div);
0608     rv6xx_memory_clock_entry_set_post_divider(rdev, entry, dividers.post_div);
0609 
0610     if (dividers.enable_post_div)
0611         rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, true);
0612     else
0613         rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, false);
0614 
0615     return 0;
0616 }
0617 
0618 static void rv6xx_program_mclk_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
0619 {
0620     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
0621     int i;
0622 
0623     for (i = 1; i < R600_PM_NUMBER_OF_MCLKS; i++) {
0624         if (pi->hw.mclks[i])
0625             rv6xx_program_mclk_stepping_entry(rdev, i,
0626                               pi->hw.mclks[i]);
0627     }
0628 }
0629 
0630 static void rv6xx_find_memory_clock_with_highest_vco(struct radeon_device *rdev,
0631                              u32 requested_memory_clock,
0632                              u32 ref_clk,
0633                              struct atom_clock_dividers *dividers,
0634                              u32 *vco_freq)
0635 {
0636     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
0637     struct atom_clock_dividers req_dividers;
0638     u32 vco_freq_temp;
0639 
0640     if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
0641                        requested_memory_clock, false, &req_dividers) == 0) {
0642         vco_freq_temp = rv6xx_calculate_vco_frequency(ref_clk, &req_dividers,
0643                                   pi->fb_div_scale);
0644 
0645         if (vco_freq_temp > *vco_freq) {
0646             *dividers = req_dividers;
0647             *vco_freq = vco_freq_temp;
0648         }
0649     }
0650 }
0651 
0652 static void rv6xx_program_mclk_spread_spectrum_parameters(struct radeon_device *rdev)
0653 {
0654     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
0655     u32 ref_clk = rdev->clock.mpll.reference_freq;
0656     struct atom_clock_dividers dividers;
0657     struct radeon_atom_ss ss;
0658     u32 vco_freq = 0, clk_v, clk_s;
0659 
0660     rv6xx_enable_memory_spread_spectrum(rdev, false);
0661 
0662     if (pi->mclk_ss) {
0663         rv6xx_find_memory_clock_with_highest_vco(rdev,
0664                              pi->hw.mclks[pi->hw.high_mclk_index],
0665                              ref_clk,
0666                              &dividers,
0667                              &vco_freq);
0668 
0669         rv6xx_find_memory_clock_with_highest_vco(rdev,
0670                              pi->hw.mclks[pi->hw.medium_mclk_index],
0671                              ref_clk,
0672                              &dividers,
0673                              &vco_freq);
0674 
0675         rv6xx_find_memory_clock_with_highest_vco(rdev,
0676                              pi->hw.mclks[pi->hw.low_mclk_index],
0677                              ref_clk,
0678                              &dividers,
0679                              &vco_freq);
0680 
0681         if (vco_freq) {
0682             if (radeon_atombios_get_asic_ss_info(rdev, &ss,
0683                                  ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
0684                 clk_v = rv6xx_calculate_spread_spectrum_clk_v(vco_freq,
0685                                          (ref_clk / (dividers.ref_div + 1)),
0686                                          ss.rate,
0687                                          ss.percentage,
0688                                          pi->fb_div_scale);
0689 
0690                 clk_s = rv6xx_calculate_spread_spectrum_clk_s(ss.rate,
0691                                          (ref_clk / (dividers.ref_div + 1)));
0692 
0693                 rv6xx_set_memory_spread_spectrum_clk_v(rdev, clk_v);
0694                 rv6xx_set_memory_spread_spectrum_clk_s(rdev, clk_s);
0695                 rv6xx_enable_memory_spread_spectrum(rdev, true);
0696             }
0697         }
0698     }
0699 }
0700 
0701 static int rv6xx_program_voltage_stepping_entry(struct radeon_device *rdev,
0702                         u32 entry, u16 voltage)
0703 {
0704     u32 mask, set_pins;
0705     int ret;
0706 
0707     ret = radeon_atom_get_voltage_gpio_settings(rdev, voltage,
0708                             SET_VOLTAGE_TYPE_ASIC_VDDC,
0709                             &set_pins, &mask);
0710     if (ret)
0711         return ret;
0712 
0713     r600_voltage_control_program_voltages(rdev, entry, set_pins);
0714 
0715     return 0;
0716 }
0717 
0718 static void rv6xx_program_voltage_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
0719 {
0720     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
0721     int i;
0722 
0723     for (i = 1; i < R600_PM_NUMBER_OF_VOLTAGE_LEVELS; i++)
0724         rv6xx_program_voltage_stepping_entry(rdev, i,
0725                              pi->hw.vddc[i]);
0726 
0727 }
0728 
0729 static void rv6xx_program_backbias_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
0730 {
0731     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
0732 
0733     if (pi->hw.backbias[1])
0734         WREG32_P(VID_UPPER_GPIO_CNTL, MEDIUM_BACKBIAS_VALUE, ~MEDIUM_BACKBIAS_VALUE);
0735     else
0736         WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~MEDIUM_BACKBIAS_VALUE);
0737 
0738     if (pi->hw.backbias[2])
0739         WREG32_P(VID_UPPER_GPIO_CNTL, HIGH_BACKBIAS_VALUE, ~HIGH_BACKBIAS_VALUE);
0740     else
0741         WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~HIGH_BACKBIAS_VALUE);
0742 }
0743 
0744 static void rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry(struct radeon_device *rdev)
0745 {
0746     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
0747 
0748     rv6xx_program_engine_spread_spectrum(rdev,
0749                          pi->hw.sclks[R600_POWER_LEVEL_LOW],
0750                          R600_POWER_LEVEL_LOW);
0751 }
0752 
0753 static void rv6xx_program_mclk_stepping_parameters_lowest_entry(struct radeon_device *rdev)
0754 {
0755     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
0756 
0757     if (pi->hw.mclks[0])
0758         rv6xx_program_mclk_stepping_entry(rdev, 0,
0759                           pi->hw.mclks[0]);
0760 }
0761 
0762 static void rv6xx_program_voltage_stepping_parameters_lowest_entry(struct radeon_device *rdev)
0763 {
0764     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
0765 
0766     rv6xx_program_voltage_stepping_entry(rdev, 0,
0767                          pi->hw.vddc[0]);
0768 
0769 }
0770 
0771 static void rv6xx_program_backbias_stepping_parameters_lowest_entry(struct radeon_device *rdev)
0772 {
0773     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
0774 
0775     if (pi->hw.backbias[0])
0776         WREG32_P(VID_UPPER_GPIO_CNTL, LOW_BACKBIAS_VALUE, ~LOW_BACKBIAS_VALUE);
0777     else
0778         WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~LOW_BACKBIAS_VALUE);
0779 }
0780 
0781 static u32 calculate_memory_refresh_rate(struct radeon_device *rdev,
0782                      u32 engine_clock)
0783 {
0784     u32 dram_rows, dram_refresh_rate;
0785     u32 tmp;
0786 
0787     tmp = (RREG32(RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
0788     dram_rows = 1 << (tmp + 10);
0789     dram_refresh_rate = 1 << ((RREG32(MC_SEQ_RESERVE_M) & 0x3) + 3);
0790 
0791     return ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
0792 }
0793 
0794 static void rv6xx_program_memory_timing_parameters(struct radeon_device *rdev)
0795 {
0796     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
0797     u32 sqm_ratio;
0798     u32 arb_refresh_rate;
0799     u32 high_clock;
0800 
0801     if (pi->hw.sclks[R600_POWER_LEVEL_HIGH] <
0802         (pi->hw.sclks[R600_POWER_LEVEL_LOW] * 0xFF / 0x40))
0803         high_clock = pi->hw.sclks[R600_POWER_LEVEL_HIGH];
0804     else
0805         high_clock =
0806             pi->hw.sclks[R600_POWER_LEVEL_LOW] * 0xFF / 0x40;
0807 
0808     radeon_atom_set_engine_dram_timings(rdev, high_clock, 0);
0809 
0810     sqm_ratio = (STATE0(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_LOW]) |
0811              STATE1(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_MEDIUM]) |
0812              STATE2(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_HIGH]) |
0813              STATE3(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_HIGH]));
0814     WREG32(SQM_RATIO, sqm_ratio);
0815 
0816     arb_refresh_rate =
0817         (POWERMODE0(calculate_memory_refresh_rate(rdev,
0818                               pi->hw.sclks[R600_POWER_LEVEL_LOW])) |
0819          POWERMODE1(calculate_memory_refresh_rate(rdev,
0820                               pi->hw.sclks[R600_POWER_LEVEL_MEDIUM])) |
0821          POWERMODE2(calculate_memory_refresh_rate(rdev,
0822                               pi->hw.sclks[R600_POWER_LEVEL_HIGH])) |
0823          POWERMODE3(calculate_memory_refresh_rate(rdev,
0824                               pi->hw.sclks[R600_POWER_LEVEL_HIGH])));
0825     WREG32(ARB_RFSH_RATE, arb_refresh_rate);
0826 }
0827 
0828 static void rv6xx_program_mpll_timing_parameters(struct radeon_device *rdev)
0829 {
0830     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
0831 
0832     r600_set_mpll_lock_time(rdev, R600_MPLLLOCKTIME_DFLT *
0833                 pi->mpll_ref_div);
0834     r600_set_mpll_reset_time(rdev, R600_MPLLRESETTIME_DFLT);
0835 }
0836 
0837 static void rv6xx_program_bsp(struct radeon_device *rdev)
0838 {
0839     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
0840     u32 ref_clk = rdev->clock.spll.reference_freq;
0841 
0842     r600_calculate_u_and_p(R600_ASI_DFLT,
0843                    ref_clk, 16,
0844                    &pi->bsp,
0845                    &pi->bsu);
0846 
0847     r600_set_bsp(rdev, pi->bsu, pi->bsp);
0848 }
0849 
0850 static void rv6xx_program_at(struct radeon_device *rdev)
0851 {
0852     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
0853 
0854     r600_set_at(rdev,
0855             (pi->hw.rp[0] * pi->bsp) / 200,
0856             (pi->hw.rp[1] * pi->bsp) / 200,
0857             (pi->hw.lp[2] * pi->bsp) / 200,
0858             (pi->hw.lp[1] * pi->bsp) / 200);
0859 }
0860 
0861 static void rv6xx_program_git(struct radeon_device *rdev)
0862 {
0863     r600_set_git(rdev, R600_GICST_DFLT);
0864 }
0865 
0866 static void rv6xx_program_tp(struct radeon_device *rdev)
0867 {
0868     int i;
0869 
0870     for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
0871         r600_set_tc(rdev, i, r600_utc[i], r600_dtc[i]);
0872 
0873     r600_select_td(rdev, R600_TD_DFLT);
0874 }
0875 
0876 static void rv6xx_program_vc(struct radeon_device *rdev)
0877 {
0878     r600_set_vrc(rdev, R600_VRC_DFLT);
0879 }
0880 
0881 static void rv6xx_clear_vc(struct radeon_device *rdev)
0882 {
0883     r600_set_vrc(rdev, 0);
0884 }
0885 
0886 static void rv6xx_program_tpp(struct radeon_device *rdev)
0887 {
0888     r600_set_tpu(rdev, R600_TPU_DFLT);
0889     r600_set_tpc(rdev, R600_TPC_DFLT);
0890 }
0891 
0892 static void rv6xx_program_sstp(struct radeon_device *rdev)
0893 {
0894     r600_set_sstu(rdev, R600_SSTU_DFLT);
0895     r600_set_sst(rdev, R600_SST_DFLT);
0896 }
0897 
0898 static void rv6xx_program_fcp(struct radeon_device *rdev)
0899 {
0900     r600_set_fctu(rdev, R600_FCTU_DFLT);
0901     r600_set_fct(rdev, R600_FCT_DFLT);
0902 }
0903 
0904 static void rv6xx_program_vddc3d_parameters(struct radeon_device *rdev)
0905 {
0906     r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT);
0907     r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT);
0908     r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT);
0909     r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT);
0910     r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT);
0911 }
0912 
0913 static void rv6xx_program_voltage_timing_parameters(struct radeon_device *rdev)
0914 {
0915     u32 rt;
0916 
0917     r600_vid_rt_set_vru(rdev, R600_VRU_DFLT);
0918 
0919     r600_vid_rt_set_vrt(rdev,
0920                 rv6xx_compute_count_for_delay(rdev,
0921                               rdev->pm.dpm.voltage_response_time,
0922                               R600_VRU_DFLT));
0923 
0924     rt = rv6xx_compute_count_for_delay(rdev,
0925                        rdev->pm.dpm.backbias_response_time,
0926                        R600_VRU_DFLT);
0927 
0928     rv6xx_vid_response_set_brt(rdev, (rt + 0x1F) >> 5);
0929 }
0930 
0931 static void rv6xx_program_engine_speed_parameters(struct radeon_device *rdev)
0932 {
0933     r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT);
0934     rv6xx_enable_engine_feedback_and_reference_sync(rdev);
0935 }
0936 
0937 static u64 rv6xx_get_master_voltage_mask(struct radeon_device *rdev)
0938 {
0939     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
0940     u64 master_mask = 0;
0941     int i;
0942 
0943     for (i = 0; i < R600_PM_NUMBER_OF_VOLTAGE_LEVELS; i++) {
0944         u32 tmp_mask, tmp_set_pins;
0945         int ret;
0946 
0947         ret = radeon_atom_get_voltage_gpio_settings(rdev,
0948                                 pi->hw.vddc[i],
0949                                 SET_VOLTAGE_TYPE_ASIC_VDDC,
0950                                 &tmp_set_pins, &tmp_mask);
0951 
0952         if (ret == 0)
0953             master_mask |= tmp_mask;
0954     }
0955 
0956     return master_mask;
0957 }
0958 
0959 static void rv6xx_program_voltage_gpio_pins(struct radeon_device *rdev)
0960 {
0961     r600_voltage_control_enable_pins(rdev,
0962                      rv6xx_get_master_voltage_mask(rdev));
0963 }
0964 
0965 static void rv6xx_enable_static_voltage_control(struct radeon_device *rdev,
0966                         struct radeon_ps *new_ps,
0967                         bool enable)
0968 {
0969     struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
0970 
0971     if (enable)
0972         radeon_atom_set_voltage(rdev,
0973                     new_state->low.vddc,
0974                     SET_VOLTAGE_TYPE_ASIC_VDDC);
0975     else
0976         r600_voltage_control_deactivate_static_control(rdev,
0977                                    rv6xx_get_master_voltage_mask(rdev));
0978 }
0979 
0980 static void rv6xx_enable_display_gap(struct radeon_device *rdev, bool enable)
0981 {
0982     if (enable) {
0983         u32 tmp = (DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM) |
0984                DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM) |
0985                DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) |
0986                DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) |
0987                VBI_TIMER_COUNT(0x3FFF) |
0988                VBI_TIMER_UNIT(7));
0989         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
0990 
0991         WREG32_P(MCLK_PWRMGT_CNTL, USE_DISPLAY_GAP, ~USE_DISPLAY_GAP);
0992     } else
0993         WREG32_P(MCLK_PWRMGT_CNTL, 0, ~USE_DISPLAY_GAP);
0994 }
0995 
0996 static void rv6xx_program_power_level_enter_state(struct radeon_device *rdev)
0997 {
0998     r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_MEDIUM);
0999 }
1000 
1001 static void rv6xx_calculate_t(u32 l_f, u32 h_f, int h,
1002                   int d_l, int d_r, u8 *l, u8 *r)
1003 {
1004     int a_n, a_d, h_r, l_r;
1005 
1006     h_r = d_l;
1007     l_r = 100 - d_r;
1008 
1009     a_n = (int)h_f * d_l + (int)l_f * (h - d_r);
1010     a_d = (int)l_f * l_r + (int)h_f * h_r;
1011 
1012     if (a_d != 0) {
1013         *l = d_l - h_r * a_n / a_d;
1014         *r = d_r + l_r * a_n / a_d;
1015     }
1016 }
1017 
1018 static void rv6xx_calculate_ap(struct radeon_device *rdev,
1019                    struct rv6xx_ps *state)
1020 {
1021     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1022 
1023     pi->hw.lp[0] = 0;
1024     pi->hw.rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS - 1]
1025         = 100;
1026 
1027     rv6xx_calculate_t(state->low.sclk,
1028               state->medium.sclk,
1029               R600_AH_DFLT,
1030               R600_LMP_DFLT,
1031               R600_RLP_DFLT,
1032               &pi->hw.lp[1],
1033               &pi->hw.rp[0]);
1034 
1035     rv6xx_calculate_t(state->medium.sclk,
1036               state->high.sclk,
1037               R600_AH_DFLT,
1038               R600_LHP_DFLT,
1039               R600_RMP_DFLT,
1040               &pi->hw.lp[2],
1041               &pi->hw.rp[1]);
1042 
1043 }
1044 
1045 static void rv6xx_calculate_stepping_parameters(struct radeon_device *rdev,
1046                         struct radeon_ps *new_ps)
1047 {
1048     struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1049 
1050     rv6xx_calculate_engine_speed_stepping_parameters(rdev, new_state);
1051     rv6xx_calculate_memory_clock_stepping_parameters(rdev, new_state);
1052     rv6xx_calculate_voltage_stepping_parameters(rdev, new_state);
1053     rv6xx_calculate_ap(rdev, new_state);
1054 }
1055 
1056 static void rv6xx_program_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
1057 {
1058     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1059 
1060     rv6xx_program_mclk_stepping_parameters_except_lowest_entry(rdev);
1061     if (pi->voltage_control)
1062         rv6xx_program_voltage_stepping_parameters_except_lowest_entry(rdev);
1063     rv6xx_program_backbias_stepping_parameters_except_lowest_entry(rdev);
1064     rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry(rdev);
1065     rv6xx_program_mclk_spread_spectrum_parameters(rdev);
1066     rv6xx_program_memory_timing_parameters(rdev);
1067 }
1068 
1069 static void rv6xx_program_stepping_parameters_lowest_entry(struct radeon_device *rdev)
1070 {
1071     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1072 
1073     rv6xx_program_mclk_stepping_parameters_lowest_entry(rdev);
1074     if (pi->voltage_control)
1075         rv6xx_program_voltage_stepping_parameters_lowest_entry(rdev);
1076     rv6xx_program_backbias_stepping_parameters_lowest_entry(rdev);
1077     rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry(rdev);
1078 }
1079 
1080 static void rv6xx_program_power_level_low(struct radeon_device *rdev)
1081 {
1082     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1083 
1084     r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW,
1085                        pi->hw.low_vddc_index);
1086     r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW,
1087                          pi->hw.low_mclk_index);
1088     r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW,
1089                          pi->hw.low_sclk_index);
1090     r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW,
1091                       R600_DISPLAY_WATERMARK_LOW);
1092     r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW,
1093                        pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
1094 }
1095 
1096 static void rv6xx_program_power_level_low_to_lowest_state(struct radeon_device *rdev)
1097 {
1098     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1099 
1100     r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0);
1101     r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
1102     r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
1103 
1104     r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW,
1105                       R600_DISPLAY_WATERMARK_LOW);
1106 
1107     r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW,
1108                        pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
1109 
1110 }
1111 
1112 static void rv6xx_program_power_level_medium(struct radeon_device *rdev)
1113 {
1114     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1115 
1116     r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM,
1117                       pi->hw.medium_vddc_index);
1118     r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
1119                         pi->hw.medium_mclk_index);
1120     r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
1121                         pi->hw.medium_sclk_index);
1122     r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM,
1123                      R600_DISPLAY_WATERMARK_LOW);
1124     r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM,
1125                       pi->hw.pcie_gen2[R600_POWER_LEVEL_MEDIUM]);
1126 }
1127 
1128 static void rv6xx_program_power_level_medium_for_transition(struct radeon_device *rdev)
1129 {
1130     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1131 
1132     rv6xx_program_mclk_stepping_entry(rdev,
1133                       R600_POWER_LEVEL_CTXSW,
1134                       pi->hw.mclks[pi->hw.low_mclk_index]);
1135 
1136     r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 1);
1137 
1138     r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
1139                          R600_POWER_LEVEL_CTXSW);
1140     r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
1141                          pi->hw.medium_sclk_index);
1142 
1143     r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM,
1144                       R600_DISPLAY_WATERMARK_LOW);
1145 
1146     rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false);
1147 
1148     r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM,
1149                        pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
1150 }
1151 
1152 static void rv6xx_program_power_level_high(struct radeon_device *rdev)
1153 {
1154     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1155 
1156     r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH,
1157                        pi->hw.high_vddc_index);
1158     r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH,
1159                          pi->hw.high_mclk_index);
1160     r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH,
1161                          pi->hw.high_sclk_index);
1162 
1163     r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH,
1164                       R600_DISPLAY_WATERMARK_HIGH);
1165 
1166     r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_HIGH,
1167                        pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH]);
1168 }
1169 
1170 static void rv6xx_enable_backbias(struct radeon_device *rdev, bool enable)
1171 {
1172     if (enable)
1173         WREG32_P(GENERAL_PWRMGT, BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL,
1174              ~(BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL));
1175     else
1176         WREG32_P(GENERAL_PWRMGT, 0,
1177              ~(BACKBIAS_VALUE | BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL));
1178 }
1179 
1180 static void rv6xx_program_display_gap(struct radeon_device *rdev)
1181 {
1182     u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
1183 
1184     tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
1185     if (rdev->pm.dpm.new_active_crtcs & 1) {
1186         tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
1187         tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1188     } else if (rdev->pm.dpm.new_active_crtcs & 2) {
1189         tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1190         tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
1191     } else {
1192         tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1193         tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1194     }
1195     WREG32(CG_DISPLAY_GAP_CNTL, tmp);
1196 }
1197 
1198 static void rv6xx_set_sw_voltage_to_safe(struct radeon_device *rdev,
1199                      struct radeon_ps *new_ps,
1200                      struct radeon_ps *old_ps)
1201 {
1202     struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1203     struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1204     u16 safe_voltage;
1205 
1206     safe_voltage = (new_state->low.vddc >= old_state->low.vddc) ?
1207         new_state->low.vddc : old_state->low.vddc;
1208 
1209     rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW,
1210                          safe_voltage);
1211 
1212     WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),
1213          ~SW_GPIO_INDEX_MASK);
1214 }
1215 
1216 static void rv6xx_set_sw_voltage_to_low(struct radeon_device *rdev,
1217                     struct radeon_ps *old_ps)
1218 {
1219     struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1220 
1221     rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW,
1222                          old_state->low.vddc);
1223 
1224     WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),
1225         ~SW_GPIO_INDEX_MASK);
1226 }
1227 
1228 static void rv6xx_set_safe_backbias(struct radeon_device *rdev,
1229                     struct radeon_ps *new_ps,
1230                     struct radeon_ps *old_ps)
1231 {
1232     struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1233     struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1234 
1235     if ((new_state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) &&
1236         (old_state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE))
1237         WREG32_P(GENERAL_PWRMGT, BACKBIAS_VALUE, ~BACKBIAS_VALUE);
1238     else
1239         WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_VALUE);
1240 }
1241 
1242 static void rv6xx_set_safe_pcie_gen2(struct radeon_device *rdev,
1243                      struct radeon_ps *new_ps,
1244                      struct radeon_ps *old_ps)
1245 {
1246     struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1247     struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1248 
1249     if ((new_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) !=
1250         (old_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2))
1251         rv6xx_force_pcie_gen1(rdev);
1252 }
1253 
1254 static void rv6xx_enable_dynamic_voltage_control(struct radeon_device *rdev,
1255                          bool enable)
1256 {
1257     if (enable)
1258         WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
1259     else
1260         WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
1261 }
1262 
1263 static void rv6xx_enable_dynamic_backbias_control(struct radeon_device *rdev,
1264                           bool enable)
1265 {
1266     if (enable)
1267         WREG32_P(GENERAL_PWRMGT, BACKBIAS_DPM_CNTL, ~BACKBIAS_DPM_CNTL);
1268     else
1269         WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_DPM_CNTL);
1270 }
1271 
1272 static int rv6xx_step_sw_voltage(struct radeon_device *rdev,
1273                  u16 initial_voltage,
1274                  u16 target_voltage)
1275 {
1276     u16 current_voltage;
1277     u16 true_target_voltage;
1278     u16 voltage_step;
1279     int signed_voltage_step;
1280 
1281     if ((radeon_atom_get_voltage_step(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
1282                       &voltage_step)) ||
1283         (radeon_atom_round_to_true_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
1284                            initial_voltage, &current_voltage)) ||
1285         (radeon_atom_round_to_true_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
1286                            target_voltage, &true_target_voltage)))
1287         return -EINVAL;
1288 
1289     if (true_target_voltage < current_voltage)
1290         signed_voltage_step = -(int)voltage_step;
1291     else
1292         signed_voltage_step = voltage_step;
1293 
1294     while (current_voltage != true_target_voltage) {
1295         current_voltage += signed_voltage_step;
1296         rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW,
1297                              current_voltage);
1298         msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000);
1299     }
1300 
1301     return 0;
1302 }
1303 
1304 static int rv6xx_step_voltage_if_increasing(struct radeon_device *rdev,
1305                         struct radeon_ps *new_ps,
1306                         struct radeon_ps *old_ps)
1307 {
1308     struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1309     struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1310 
1311     if (new_state->low.vddc > old_state->low.vddc)
1312         return rv6xx_step_sw_voltage(rdev,
1313                          old_state->low.vddc,
1314                          new_state->low.vddc);
1315 
1316     return 0;
1317 }
1318 
1319 static int rv6xx_step_voltage_if_decreasing(struct radeon_device *rdev,
1320                         struct radeon_ps *new_ps,
1321                         struct radeon_ps *old_ps)
1322 {
1323     struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1324     struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1325 
1326     if (new_state->low.vddc < old_state->low.vddc)
1327         return rv6xx_step_sw_voltage(rdev,
1328                          old_state->low.vddc,
1329                          new_state->low.vddc);
1330     else
1331         return 0;
1332 }
1333 
1334 static void rv6xx_enable_high(struct radeon_device *rdev)
1335 {
1336     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1337 
1338     if ((pi->restricted_levels < 1) ||
1339         (pi->restricted_levels == 3))
1340         r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true);
1341 }
1342 
1343 static void rv6xx_enable_medium(struct radeon_device *rdev)
1344 {
1345     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1346 
1347     if (pi->restricted_levels < 2)
1348         r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
1349 }
1350 
1351 static void rv6xx_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
1352 {
1353     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1354     bool want_thermal_protection;
1355     enum radeon_dpm_event_src dpm_event_src;
1356 
1357     switch (sources) {
1358     case 0:
1359     default:
1360         want_thermal_protection = false;
1361         break;
1362     case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
1363         want_thermal_protection = true;
1364         dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
1365         break;
1366 
1367     case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1368         want_thermal_protection = true;
1369         dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
1370         break;
1371 
1372     case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1373           (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1374             want_thermal_protection = true;
1375         dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1376         break;
1377     }
1378 
1379     if (want_thermal_protection) {
1380         WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
1381         if (pi->thermal_protection)
1382             WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
1383     } else {
1384         WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
1385     }
1386 }
1387 
1388 static void rv6xx_enable_auto_throttle_source(struct radeon_device *rdev,
1389                           enum radeon_dpm_auto_throttle_src source,
1390                           bool enable)
1391 {
1392     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1393 
1394     if (enable) {
1395         if (!(pi->active_auto_throttle_sources & (1 << source))) {
1396             pi->active_auto_throttle_sources |= 1 << source;
1397             rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1398         }
1399     } else {
1400         if (pi->active_auto_throttle_sources & (1 << source)) {
1401             pi->active_auto_throttle_sources &= ~(1 << source);
1402             rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1403         }
1404     }
1405 }
1406 
1407 
1408 static void rv6xx_enable_thermal_protection(struct radeon_device *rdev,
1409                         bool enable)
1410 {
1411     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1412 
1413     if (pi->active_auto_throttle_sources)
1414         r600_enable_thermal_protection(rdev, enable);
1415 }
1416 
1417 static void rv6xx_generate_transition_stepping(struct radeon_device *rdev,
1418                            struct radeon_ps *new_ps,
1419                            struct radeon_ps *old_ps)
1420 {
1421     struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1422     struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1423     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1424 
1425     rv6xx_generate_steps(rdev,
1426                  old_state->low.sclk,
1427                  new_state->low.sclk,
1428                  0, &pi->hw.medium_sclk_index);
1429 }
1430 
1431 static void rv6xx_generate_low_step(struct radeon_device *rdev,
1432                     struct radeon_ps *new_ps)
1433 {
1434     struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1435     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1436 
1437     pi->hw.low_sclk_index = 0;
1438     rv6xx_generate_single_step(rdev,
1439                    new_state->low.sclk,
1440                    0);
1441 }
1442 
1443 static void rv6xx_invalidate_intermediate_steps(struct radeon_device *rdev)
1444 {
1445     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1446 
1447     rv6xx_invalidate_intermediate_steps_range(rdev, 0,
1448                           pi->hw.medium_sclk_index);
1449 }
1450 
1451 static void rv6xx_generate_stepping_table(struct radeon_device *rdev,
1452                       struct radeon_ps *new_ps)
1453 {
1454     struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1455     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1456 
1457     pi->hw.low_sclk_index = 0;
1458 
1459     rv6xx_generate_steps(rdev,
1460                  new_state->low.sclk,
1461                  new_state->medium.sclk,
1462                  0,
1463                  &pi->hw.medium_sclk_index);
1464     rv6xx_generate_steps(rdev,
1465                  new_state->medium.sclk,
1466                  new_state->high.sclk,
1467                  pi->hw.medium_sclk_index,
1468                  &pi->hw.high_sclk_index);
1469 }
1470 
1471 static void rv6xx_enable_spread_spectrum(struct radeon_device *rdev,
1472                      bool enable)
1473 {
1474     if (enable)
1475         rv6xx_enable_dynamic_spread_spectrum(rdev, true);
1476     else {
1477         rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_LOW, false);
1478         rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false);
1479         rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_HIGH, false);
1480         rv6xx_enable_dynamic_spread_spectrum(rdev, false);
1481         rv6xx_enable_memory_spread_spectrum(rdev, false);
1482     }
1483 }
1484 
1485 static void rv6xx_reset_lvtm_data_sync(struct radeon_device *rdev)
1486 {
1487     if (ASIC_IS_DCE3(rdev))
1488         WREG32_P(DCE3_LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG);
1489     else
1490         WREG32_P(LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG);
1491 }
1492 
1493 static void rv6xx_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
1494                        struct radeon_ps *new_ps,
1495                        bool enable)
1496 {
1497     struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1498 
1499     if (enable) {
1500         rv6xx_enable_bif_dynamic_pcie_gen2(rdev, true);
1501         rv6xx_enable_pcie_gen2_support(rdev);
1502         r600_enable_dynamic_pcie_gen2(rdev, true);
1503     } else {
1504         if (!(new_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2))
1505             rv6xx_force_pcie_gen1(rdev);
1506         rv6xx_enable_bif_dynamic_pcie_gen2(rdev, false);
1507         r600_enable_dynamic_pcie_gen2(rdev, false);
1508     }
1509 }
1510 
1511 static void rv6xx_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
1512                              struct radeon_ps *new_ps,
1513                              struct radeon_ps *old_ps)
1514 {
1515     struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1516     struct rv6xx_ps *current_state = rv6xx_get_ps(old_ps);
1517 
1518     if ((new_ps->vclk == old_ps->vclk) &&
1519         (new_ps->dclk == old_ps->dclk))
1520         return;
1521 
1522     if (new_state->high.sclk >= current_state->high.sclk)
1523         return;
1524 
1525     radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1526 }
1527 
1528 static void rv6xx_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
1529                             struct radeon_ps *new_ps,
1530                             struct radeon_ps *old_ps)
1531 {
1532     struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1533     struct rv6xx_ps *current_state = rv6xx_get_ps(old_ps);
1534 
1535     if ((new_ps->vclk == old_ps->vclk) &&
1536         (new_ps->dclk == old_ps->dclk))
1537         return;
1538 
1539     if (new_state->high.sclk < current_state->high.sclk)
1540         return;
1541 
1542     radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1543 }
1544 
1545 int rv6xx_dpm_enable(struct radeon_device *rdev)
1546 {
1547     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1548     struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1549 
1550     if (r600_dynamicpm_enabled(rdev))
1551         return -EINVAL;
1552 
1553     if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1554         rv6xx_enable_backbias(rdev, true);
1555 
1556     if (pi->dynamic_ss)
1557         rv6xx_enable_spread_spectrum(rdev, true);
1558 
1559     rv6xx_program_mpll_timing_parameters(rdev);
1560     rv6xx_program_bsp(rdev);
1561     rv6xx_program_git(rdev);
1562     rv6xx_program_tp(rdev);
1563     rv6xx_program_tpp(rdev);
1564     rv6xx_program_sstp(rdev);
1565     rv6xx_program_fcp(rdev);
1566     rv6xx_program_vddc3d_parameters(rdev);
1567     rv6xx_program_voltage_timing_parameters(rdev);
1568     rv6xx_program_engine_speed_parameters(rdev);
1569 
1570     rv6xx_enable_display_gap(rdev, true);
1571     if (pi->display_gap == false)
1572         rv6xx_enable_display_gap(rdev, false);
1573 
1574     rv6xx_program_power_level_enter_state(rdev);
1575 
1576     rv6xx_calculate_stepping_parameters(rdev, boot_ps);
1577 
1578     if (pi->voltage_control)
1579         rv6xx_program_voltage_gpio_pins(rdev);
1580 
1581     rv6xx_generate_stepping_table(rdev, boot_ps);
1582 
1583     rv6xx_program_stepping_parameters_except_lowest_entry(rdev);
1584     rv6xx_program_stepping_parameters_lowest_entry(rdev);
1585 
1586     rv6xx_program_power_level_low(rdev);
1587     rv6xx_program_power_level_medium(rdev);
1588     rv6xx_program_power_level_high(rdev);
1589     rv6xx_program_vc(rdev);
1590     rv6xx_program_at(rdev);
1591 
1592     r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
1593     r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
1594     r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true);
1595 
1596     rv6xx_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
1597 
1598     r600_start_dpm(rdev);
1599 
1600     if (pi->voltage_control)
1601         rv6xx_enable_static_voltage_control(rdev, boot_ps, false);
1602 
1603     if (pi->dynamic_pcie_gen2)
1604         rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, true);
1605 
1606     if (pi->gfx_clock_gating)
1607         r600_gfx_clockgating_enable(rdev, true);
1608 
1609     return 0;
1610 }
1611 
1612 void rv6xx_dpm_disable(struct radeon_device *rdev)
1613 {
1614     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1615     struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1616 
1617     if (!r600_dynamicpm_enabled(rdev))
1618         return;
1619 
1620     r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
1621     r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
1622     rv6xx_enable_display_gap(rdev, false);
1623     rv6xx_clear_vc(rdev);
1624     r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF);
1625 
1626     if (pi->thermal_protection)
1627         r600_enable_thermal_protection(rdev, false);
1628 
1629     r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
1630     r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
1631     r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
1632 
1633     if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1634         rv6xx_enable_backbias(rdev, false);
1635 
1636     rv6xx_enable_spread_spectrum(rdev, false);
1637 
1638     if (pi->voltage_control)
1639         rv6xx_enable_static_voltage_control(rdev, boot_ps, true);
1640 
1641     if (pi->dynamic_pcie_gen2)
1642         rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, false);
1643 
1644     if (rdev->irq.installed &&
1645         r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1646         rdev->irq.dpm_thermal = false;
1647         radeon_irq_set(rdev);
1648     }
1649 
1650     if (pi->gfx_clock_gating)
1651         r600_gfx_clockgating_enable(rdev, false);
1652 
1653     r600_stop_dpm(rdev);
1654 }
1655 
1656 int rv6xx_dpm_set_power_state(struct radeon_device *rdev)
1657 {
1658     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1659     struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
1660     struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
1661     int ret;
1662 
1663     pi->restricted_levels = 0;
1664 
1665     rv6xx_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
1666 
1667     rv6xx_clear_vc(rdev);
1668     r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
1669     r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF);
1670 
1671     if (pi->thermal_protection)
1672         r600_enable_thermal_protection(rdev, false);
1673 
1674     r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
1675     r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
1676     r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
1677 
1678     rv6xx_generate_transition_stepping(rdev, new_ps, old_ps);
1679     rv6xx_program_power_level_medium_for_transition(rdev);
1680 
1681     if (pi->voltage_control) {
1682         rv6xx_set_sw_voltage_to_safe(rdev, new_ps, old_ps);
1683         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1684             rv6xx_set_sw_voltage_to_low(rdev, old_ps);
1685     }
1686 
1687     if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1688         rv6xx_set_safe_backbias(rdev, new_ps, old_ps);
1689 
1690     if (pi->dynamic_pcie_gen2)
1691         rv6xx_set_safe_pcie_gen2(rdev, new_ps, old_ps);
1692 
1693     if (pi->voltage_control)
1694         rv6xx_enable_dynamic_voltage_control(rdev, false);
1695 
1696     if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1697         rv6xx_enable_dynamic_backbias_control(rdev, false);
1698 
1699     if (pi->voltage_control) {
1700         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1701             rv6xx_step_voltage_if_increasing(rdev, new_ps, old_ps);
1702         msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000);
1703     }
1704 
1705     r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
1706     r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false);
1707     r600_wait_for_power_level_unequal(rdev, R600_POWER_LEVEL_LOW);
1708 
1709     rv6xx_generate_low_step(rdev, new_ps);
1710     rv6xx_invalidate_intermediate_steps(rdev);
1711     rv6xx_calculate_stepping_parameters(rdev, new_ps);
1712     rv6xx_program_stepping_parameters_lowest_entry(rdev);
1713     rv6xx_program_power_level_low_to_lowest_state(rdev);
1714 
1715     r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
1716     r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
1717     r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
1718 
1719     if (pi->voltage_control) {
1720         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) {
1721             ret = rv6xx_step_voltage_if_decreasing(rdev, new_ps, old_ps);
1722             if (ret)
1723                 return ret;
1724         }
1725         rv6xx_enable_dynamic_voltage_control(rdev, true);
1726     }
1727 
1728     if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1729         rv6xx_enable_dynamic_backbias_control(rdev, true);
1730 
1731     if (pi->dynamic_pcie_gen2)
1732         rv6xx_enable_dynamic_pcie_gen2(rdev, new_ps, true);
1733 
1734     rv6xx_reset_lvtm_data_sync(rdev);
1735 
1736     rv6xx_generate_stepping_table(rdev, new_ps);
1737     rv6xx_program_stepping_parameters_except_lowest_entry(rdev);
1738     rv6xx_program_power_level_low(rdev);
1739     rv6xx_program_power_level_medium(rdev);
1740     rv6xx_program_power_level_high(rdev);
1741     rv6xx_enable_medium(rdev);
1742     rv6xx_enable_high(rdev);
1743 
1744     if (pi->thermal_protection)
1745         rv6xx_enable_thermal_protection(rdev, true);
1746     rv6xx_program_vc(rdev);
1747     rv6xx_program_at(rdev);
1748 
1749     rv6xx_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
1750 
1751     return 0;
1752 }
1753 
1754 void rv6xx_setup_asic(struct radeon_device *rdev)
1755 {
1756     r600_enable_acpi_pm(rdev);
1757 
1758     if (radeon_aspm != 0) {
1759         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s)
1760             rv6xx_enable_l0s(rdev);
1761         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1)
1762             rv6xx_enable_l1(rdev);
1763         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1)
1764             rv6xx_enable_pll_sleep_in_l1(rdev);
1765     }
1766 }
1767 
1768 void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev)
1769 {
1770     rv6xx_program_display_gap(rdev);
1771 }
1772 
1773 union power_info {
1774     struct _ATOM_POWERPLAY_INFO info;
1775     struct _ATOM_POWERPLAY_INFO_V2 info_2;
1776     struct _ATOM_POWERPLAY_INFO_V3 info_3;
1777     struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1778     struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1779     struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1780 };
1781 
1782 union pplib_clock_info {
1783     struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1784     struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1785     struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1786     struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1787 };
1788 
1789 union pplib_power_state {
1790     struct _ATOM_PPLIB_STATE v1;
1791     struct _ATOM_PPLIB_STATE_V2 v2;
1792 };
1793 
1794 static void rv6xx_parse_pplib_non_clock_info(struct radeon_device *rdev,
1795                          struct radeon_ps *rps,
1796                          struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
1797 {
1798     rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1799     rps->class = le16_to_cpu(non_clock_info->usClassification);
1800     rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
1801 
1802     if (r600_is_uvd_state(rps->class, rps->class2)) {
1803         rps->vclk = RV6XX_DEFAULT_VCLK_FREQ;
1804         rps->dclk = RV6XX_DEFAULT_DCLK_FREQ;
1805     } else {
1806         rps->vclk = 0;
1807         rps->dclk = 0;
1808     }
1809 
1810     if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
1811         rdev->pm.dpm.boot_ps = rps;
1812     if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
1813         rdev->pm.dpm.uvd_ps = rps;
1814 }
1815 
1816 static void rv6xx_parse_pplib_clock_info(struct radeon_device *rdev,
1817                      struct radeon_ps *rps, int index,
1818                      union pplib_clock_info *clock_info)
1819 {
1820     struct rv6xx_ps *ps = rv6xx_get_ps(rps);
1821     u32 sclk, mclk;
1822     u16 vddc;
1823     struct rv6xx_pl *pl;
1824 
1825     switch (index) {
1826     case 0:
1827         pl = &ps->low;
1828         break;
1829     case 1:
1830         pl = &ps->medium;
1831         break;
1832     case 2:
1833     default:
1834         pl = &ps->high;
1835         break;
1836     }
1837 
1838     sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
1839     sclk |= clock_info->r600.ucEngineClockHigh << 16;
1840     mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
1841     mclk |= clock_info->r600.ucMemoryClockHigh << 16;
1842 
1843     pl->mclk = mclk;
1844     pl->sclk = sclk;
1845     pl->vddc = le16_to_cpu(clock_info->r600.usVDDC);
1846     pl->flags = le32_to_cpu(clock_info->r600.ulFlags);
1847 
1848     /* patch up vddc if necessary */
1849     if (pl->vddc == 0xff01) {
1850         if (radeon_atom_get_max_vddc(rdev, 0, 0, &vddc) == 0)
1851             pl->vddc = vddc;
1852     }
1853 
1854     /* fix up pcie gen2 */
1855     if (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) {
1856         if ((rdev->family == CHIP_RV610) || (rdev->family == CHIP_RV630)) {
1857             if (pl->vddc < 1100)
1858                 pl->flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2;
1859         }
1860     }
1861 
1862     /* patch up boot state */
1863     if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1864         u16 vddc, vddci, mvdd;
1865         radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
1866         pl->mclk = rdev->clock.default_mclk;
1867         pl->sclk = rdev->clock.default_sclk;
1868         pl->vddc = vddc;
1869     }
1870 }
1871 
1872 static int rv6xx_parse_power_table(struct radeon_device *rdev)
1873 {
1874     struct radeon_mode_info *mode_info = &rdev->mode_info;
1875     struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1876     union pplib_power_state *power_state;
1877     int i, j;
1878     union pplib_clock_info *clock_info;
1879     union power_info *power_info;
1880     int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1881     u16 data_offset;
1882     u8 frev, crev;
1883     struct rv6xx_ps *ps;
1884 
1885     if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1886                    &frev, &crev, &data_offset))
1887         return -EINVAL;
1888     power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1889 
1890     rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates,
1891                   sizeof(struct radeon_ps),
1892                   GFP_KERNEL);
1893     if (!rdev->pm.dpm.ps)
1894         return -ENOMEM;
1895 
1896     for (i = 0; i < power_info->pplib.ucNumStates; i++) {
1897         power_state = (union pplib_power_state *)
1898             (mode_info->atom_context->bios + data_offset +
1899              le16_to_cpu(power_info->pplib.usStateArrayOffset) +
1900              i * power_info->pplib.ucStateEntrySize);
1901         non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1902             (mode_info->atom_context->bios + data_offset +
1903              le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
1904              (power_state->v1.ucNonClockStateIndex *
1905               power_info->pplib.ucNonClockSize));
1906         if (power_info->pplib.ucStateEntrySize - 1) {
1907             u8 *idx;
1908             ps = kzalloc(sizeof(struct rv6xx_ps), GFP_KERNEL);
1909             if (ps == NULL) {
1910                 kfree(rdev->pm.dpm.ps);
1911                 return -ENOMEM;
1912             }
1913             rdev->pm.dpm.ps[i].ps_priv = ps;
1914             rv6xx_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
1915                              non_clock_info);
1916             idx = (u8 *)&power_state->v1.ucClockStateIndices[0];
1917             for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
1918                 clock_info = (union pplib_clock_info *)
1919                     (mode_info->atom_context->bios + data_offset +
1920                      le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
1921                      (idx[j] * power_info->pplib.ucClockInfoSize));
1922                 rv6xx_parse_pplib_clock_info(rdev,
1923                                  &rdev->pm.dpm.ps[i], j,
1924                                  clock_info);
1925             }
1926         }
1927     }
1928     rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
1929     return 0;
1930 }
1931 
1932 int rv6xx_dpm_init(struct radeon_device *rdev)
1933 {
1934     struct radeon_atom_ss ss;
1935     struct atom_clock_dividers dividers;
1936     struct rv6xx_power_info *pi;
1937     int ret;
1938 
1939     pi = kzalloc(sizeof(struct rv6xx_power_info), GFP_KERNEL);
1940     if (pi == NULL)
1941         return -ENOMEM;
1942     rdev->pm.dpm.priv = pi;
1943 
1944     ret = r600_get_platform_caps(rdev);
1945     if (ret)
1946         return ret;
1947 
1948     ret = rv6xx_parse_power_table(rdev);
1949     if (ret)
1950         return ret;
1951 
1952     if (rdev->pm.dpm.voltage_response_time == 0)
1953         rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
1954     if (rdev->pm.dpm.backbias_response_time == 0)
1955         rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
1956 
1957     ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1958                          0, false, &dividers);
1959     if (ret)
1960         pi->spll_ref_div = dividers.ref_div + 1;
1961     else
1962         pi->spll_ref_div = R600_REFERENCEDIVIDER_DFLT;
1963 
1964     ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
1965                          0, false, &dividers);
1966     if (ret)
1967         pi->mpll_ref_div = dividers.ref_div + 1;
1968     else
1969         pi->mpll_ref_div = R600_REFERENCEDIVIDER_DFLT;
1970 
1971     if (rdev->family >= CHIP_RV670)
1972         pi->fb_div_scale = 1;
1973     else
1974         pi->fb_div_scale = 0;
1975 
1976     pi->voltage_control =
1977         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0);
1978 
1979     pi->gfx_clock_gating = true;
1980 
1981     pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
1982                                ASIC_INTERNAL_ENGINE_SS, 0);
1983     pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
1984                                ASIC_INTERNAL_MEMORY_SS, 0);
1985 
1986     /* Disable sclk ss, causes hangs on a lot of systems */
1987     pi->sclk_ss = false;
1988 
1989     if (pi->sclk_ss || pi->mclk_ss)
1990         pi->dynamic_ss = true;
1991     else
1992         pi->dynamic_ss = false;
1993 
1994     pi->dynamic_pcie_gen2 = true;
1995 
1996     if (pi->gfx_clock_gating &&
1997         (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
1998         pi->thermal_protection = true;
1999     else
2000         pi->thermal_protection = false;
2001 
2002     pi->display_gap = true;
2003 
2004     return 0;
2005 }
2006 
2007 void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
2008                  struct radeon_ps *rps)
2009 {
2010     struct rv6xx_ps *ps = rv6xx_get_ps(rps);
2011     struct rv6xx_pl *pl;
2012 
2013     r600_dpm_print_class_info(rps->class, rps->class2);
2014     r600_dpm_print_cap_info(rps->caps);
2015     printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
2016     pl = &ps->low;
2017     printk("\t\tpower level 0    sclk: %u mclk: %u vddc: %u\n",
2018            pl->sclk, pl->mclk, pl->vddc);
2019     pl = &ps->medium;
2020     printk("\t\tpower level 1    sclk: %u mclk: %u vddc: %u\n",
2021            pl->sclk, pl->mclk, pl->vddc);
2022     pl = &ps->high;
2023     printk("\t\tpower level 2    sclk: %u mclk: %u vddc: %u\n",
2024            pl->sclk, pl->mclk, pl->vddc);
2025     r600_dpm_print_ps_status(rdev, rps);
2026 }
2027 
2028 void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
2029                                struct seq_file *m)
2030 {
2031     struct radeon_ps *rps = rdev->pm.dpm.current_ps;
2032     struct rv6xx_ps *ps = rv6xx_get_ps(rps);
2033     struct rv6xx_pl *pl;
2034     u32 current_index =
2035         (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
2036         CURRENT_PROFILE_INDEX_SHIFT;
2037 
2038     if (current_index > 2) {
2039         seq_printf(m, "invalid dpm profile %d\n", current_index);
2040     } else {
2041         if (current_index == 0)
2042             pl = &ps->low;
2043         else if (current_index == 1)
2044             pl = &ps->medium;
2045         else /* current_index == 2 */
2046             pl = &ps->high;
2047         seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
2048         seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u\n",
2049                current_index, pl->sclk, pl->mclk, pl->vddc);
2050     }
2051 }
2052 
2053 /* get the current sclk in 10 khz units */
2054 u32 rv6xx_dpm_get_current_sclk(struct radeon_device *rdev)
2055 {
2056     struct radeon_ps *rps = rdev->pm.dpm.current_ps;
2057     struct rv6xx_ps *ps = rv6xx_get_ps(rps);
2058     struct rv6xx_pl *pl;
2059     u32 current_index =
2060         (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
2061         CURRENT_PROFILE_INDEX_SHIFT;
2062 
2063     if (current_index > 2) {
2064         return 0;
2065     } else {
2066         if (current_index == 0)
2067             pl = &ps->low;
2068         else if (current_index == 1)
2069             pl = &ps->medium;
2070         else /* current_index == 2 */
2071             pl = &ps->high;
2072         return pl->sclk;
2073     }
2074 }
2075 
2076 /* get the current mclk in 10 khz units */
2077 u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev)
2078 {
2079     struct radeon_ps *rps = rdev->pm.dpm.current_ps;
2080     struct rv6xx_ps *ps = rv6xx_get_ps(rps);
2081     struct rv6xx_pl *pl;
2082     u32 current_index =
2083         (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
2084         CURRENT_PROFILE_INDEX_SHIFT;
2085 
2086     if (current_index > 2) {
2087         return 0;
2088     } else {
2089         if (current_index == 0)
2090             pl = &ps->low;
2091         else if (current_index == 1)
2092             pl = &ps->medium;
2093         else /* current_index == 2 */
2094             pl = &ps->high;
2095         return pl->mclk;
2096     }
2097 }
2098 
2099 void rv6xx_dpm_fini(struct radeon_device *rdev)
2100 {
2101     int i;
2102 
2103     for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2104         kfree(rdev->pm.dpm.ps[i].ps_priv);
2105     }
2106     kfree(rdev->pm.dpm.ps);
2107     kfree(rdev->pm.dpm.priv);
2108 }
2109 
2110 u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low)
2111 {
2112     struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);
2113 
2114     if (low)
2115         return requested_state->low.sclk;
2116     else
2117         return requested_state->high.sclk;
2118 }
2119 
2120 u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low)
2121 {
2122     struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);
2123 
2124     if (low)
2125         return requested_state->low.mclk;
2126     else
2127         return requested_state->high.mclk;
2128 }
2129 
2130 int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
2131                       enum radeon_dpm_forced_level level)
2132 {
2133     struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
2134 
2135     if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
2136         pi->restricted_levels = 3;
2137     } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
2138         pi->restricted_levels = 2;
2139     } else {
2140         pi->restricted_levels = 0;
2141     }
2142 
2143     rv6xx_clear_vc(rdev);
2144     r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
2145     r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF);
2146     r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
2147     r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
2148     r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
2149     rv6xx_enable_medium(rdev);
2150     rv6xx_enable_high(rdev);
2151     if (pi->restricted_levels == 3)
2152         r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false);
2153     rv6xx_program_vc(rdev);
2154     rv6xx_program_at(rdev);
2155 
2156     rdev->pm.dpm.forced_level = level;
2157 
2158     return 0;
2159 }
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