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0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  * Copyright 2009 Jerome Glisse.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors: Dave Airlie
0025  *          Alex Deucher
0026  *          Jerome Glisse
0027  */
0028 
0029 #include <linux/seq_file.h>
0030 #include <linux/slab.h>
0031 
0032 #include <drm/drm_device.h>
0033 #include <drm/drm_file.h>
0034 
0035 #include "atom.h"
0036 #include "radeon.h"
0037 #include "radeon_asic.h"
0038 #include "rv515_reg_safe.h"
0039 #include "rv515d.h"
0040 
0041 /* This files gather functions specifics to: rv515 */
0042 static void rv515_gpu_init(struct radeon_device *rdev);
0043 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
0044 
0045 static const u32 crtc_offsets[2] =
0046 {
0047     0,
0048     AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
0049 };
0050 
0051 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
0052 {
0053     int r;
0054 
0055     r = radeon_ring_lock(rdev, ring, 64);
0056     if (r) {
0057         return;
0058     }
0059     radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
0060     radeon_ring_write(ring,
0061               ISYNC_ANY2D_IDLE3D |
0062               ISYNC_ANY3D_IDLE2D |
0063               ISYNC_WAIT_IDLEGUI |
0064               ISYNC_CPSCRATCH_IDLEGUI);
0065     radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
0066     radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
0067     radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
0068     radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
0069     radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
0070     radeon_ring_write(ring, 0);
0071     radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
0072     radeon_ring_write(ring, 0);
0073     radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));
0074     radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1);
0075     radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));
0076     radeon_ring_write(ring, 0);
0077     radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
0078     radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
0079     radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
0080     radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
0081     radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
0082     radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
0083     radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0));
0084     radeon_ring_write(ring, 0);
0085     radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
0086     radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
0087     radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
0088     radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
0089     radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0));
0090     radeon_ring_write(ring,
0091               ((6 << MS_X0_SHIFT) |
0092                (6 << MS_Y0_SHIFT) |
0093                (6 << MS_X1_SHIFT) |
0094                (6 << MS_Y1_SHIFT) |
0095                (6 << MS_X2_SHIFT) |
0096                (6 << MS_Y2_SHIFT) |
0097                (6 << MSBD0_Y_SHIFT) |
0098                (6 << MSBD0_X_SHIFT)));
0099     radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0));
0100     radeon_ring_write(ring,
0101               ((6 << MS_X3_SHIFT) |
0102                (6 << MS_Y3_SHIFT) |
0103                (6 << MS_X4_SHIFT) |
0104                (6 << MS_Y4_SHIFT) |
0105                (6 << MS_X5_SHIFT) |
0106                (6 << MS_Y5_SHIFT) |
0107                (6 << MSBD1_SHIFT)));
0108     radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0));
0109     radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
0110     radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0));
0111     radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
0112     radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0));
0113     radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
0114     radeon_ring_write(ring, PACKET0(0x20C8, 0));
0115     radeon_ring_write(ring, 0);
0116     radeon_ring_unlock_commit(rdev, ring, false);
0117 }
0118 
0119 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
0120 {
0121     unsigned i;
0122     uint32_t tmp;
0123 
0124     for (i = 0; i < rdev->usec_timeout; i++) {
0125         /* read MC_STATUS */
0126         tmp = RREG32_MC(MC_STATUS);
0127         if (tmp & MC_STATUS_IDLE) {
0128             return 0;
0129         }
0130         udelay(1);
0131     }
0132     return -1;
0133 }
0134 
0135 void rv515_vga_render_disable(struct radeon_device *rdev)
0136 {
0137     WREG32(R_000300_VGA_RENDER_CONTROL,
0138         RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
0139 }
0140 
0141 static void rv515_gpu_init(struct radeon_device *rdev)
0142 {
0143     unsigned pipe_select_current, gb_pipe_select, tmp;
0144 
0145     if (r100_gui_wait_for_idle(rdev)) {
0146         pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n");
0147     }
0148     rv515_vga_render_disable(rdev);
0149     r420_pipes_init(rdev);
0150     gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
0151     tmp = RREG32(R300_DST_PIPE_CONFIG);
0152     pipe_select_current = (tmp >> 2) & 3;
0153     tmp = (1 << pipe_select_current) |
0154           (((gb_pipe_select >> 8) & 0xF) << 4);
0155     WREG32_PLL(0x000D, tmp);
0156     if (r100_gui_wait_for_idle(rdev)) {
0157         pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n");
0158     }
0159     if (rv515_mc_wait_for_idle(rdev)) {
0160         pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n");
0161     }
0162 }
0163 
0164 static void rv515_vram_get_type(struct radeon_device *rdev)
0165 {
0166     uint32_t tmp;
0167 
0168     rdev->mc.vram_width = 128;
0169     rdev->mc.vram_is_ddr = true;
0170     tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
0171     switch (tmp) {
0172     case 0:
0173         rdev->mc.vram_width = 64;
0174         break;
0175     case 1:
0176         rdev->mc.vram_width = 128;
0177         break;
0178     default:
0179         rdev->mc.vram_width = 128;
0180         break;
0181     }
0182 }
0183 
0184 static void rv515_mc_init(struct radeon_device *rdev)
0185 {
0186 
0187     rv515_vram_get_type(rdev);
0188     r100_vram_init_sizes(rdev);
0189     radeon_vram_location(rdev, &rdev->mc, 0);
0190     rdev->mc.gtt_base_align = 0;
0191     if (!(rdev->flags & RADEON_IS_AGP))
0192         radeon_gtt_location(rdev, &rdev->mc);
0193     radeon_update_bandwidth_info(rdev);
0194 }
0195 
0196 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
0197 {
0198     unsigned long flags;
0199     uint32_t r;
0200 
0201     spin_lock_irqsave(&rdev->mc_idx_lock, flags);
0202     WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
0203     r = RREG32(MC_IND_DATA);
0204     WREG32(MC_IND_INDEX, 0);
0205     spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
0206 
0207     return r;
0208 }
0209 
0210 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
0211 {
0212     unsigned long flags;
0213 
0214     spin_lock_irqsave(&rdev->mc_idx_lock, flags);
0215     WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
0216     WREG32(MC_IND_DATA, (v));
0217     WREG32(MC_IND_INDEX, 0);
0218     spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
0219 }
0220 
0221 #if defined(CONFIG_DEBUG_FS)
0222 static int rv515_debugfs_pipes_info_show(struct seq_file *m, void *unused)
0223 {
0224     struct radeon_device *rdev = (struct radeon_device *)m->private;
0225     uint32_t tmp;
0226 
0227     tmp = RREG32(GB_PIPE_SELECT);
0228     seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
0229     tmp = RREG32(SU_REG_DEST);
0230     seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
0231     tmp = RREG32(GB_TILE_CONFIG);
0232     seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
0233     tmp = RREG32(DST_PIPE_CONFIG);
0234     seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
0235     return 0;
0236 }
0237 
0238 static int rv515_debugfs_ga_info_show(struct seq_file *m, void *unused)
0239 {
0240     struct radeon_device *rdev = (struct radeon_device *)m->private;
0241     uint32_t tmp;
0242 
0243     tmp = RREG32(0x2140);
0244     seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
0245     radeon_asic_reset(rdev);
0246     tmp = RREG32(0x425C);
0247     seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
0248     return 0;
0249 }
0250 
0251 DEFINE_SHOW_ATTRIBUTE(rv515_debugfs_pipes_info);
0252 DEFINE_SHOW_ATTRIBUTE(rv515_debugfs_ga_info);
0253 #endif
0254 
0255 void rv515_debugfs(struct radeon_device *rdev)
0256 {
0257 #if defined(CONFIG_DEBUG_FS)
0258     struct dentry *root = rdev->ddev->primary->debugfs_root;
0259 
0260     debugfs_create_file("rv515_pipes_info", 0444, root, rdev,
0261                 &rv515_debugfs_pipes_info_fops);
0262     debugfs_create_file("rv515_ga_info", 0444, root, rdev,
0263                 &rv515_debugfs_ga_info_fops);
0264 #endif
0265     r100_debugfs_rbbm_init(rdev);
0266 }
0267 
0268 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
0269 {
0270     u32 crtc_enabled, tmp, frame_count, blackout;
0271     int i, j;
0272 
0273     save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
0274     save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
0275 
0276     /* disable VGA render */
0277     WREG32(R_000300_VGA_RENDER_CONTROL, 0);
0278     /* blank the display controllers */
0279     for (i = 0; i < rdev->num_crtc; i++) {
0280         crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;
0281         if (crtc_enabled) {
0282             save->crtc_enabled[i] = true;
0283             tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
0284             if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
0285                 radeon_wait_for_vblank(rdev, i);
0286                 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
0287                 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
0288                 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
0289                 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
0290             }
0291             /* wait for the next frame */
0292             frame_count = radeon_get_vblank_counter(rdev, i);
0293             for (j = 0; j < rdev->usec_timeout; j++) {
0294                 if (radeon_get_vblank_counter(rdev, i) != frame_count)
0295                     break;
0296                 udelay(1);
0297             }
0298 
0299             /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
0300             WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
0301             tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
0302             tmp &= ~AVIVO_CRTC_EN;
0303             WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
0304             WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
0305             save->crtc_enabled[i] = false;
0306             /* ***** */
0307         } else {
0308             save->crtc_enabled[i] = false;
0309         }
0310     }
0311 
0312     radeon_mc_wait_for_idle(rdev);
0313 
0314     if (rdev->family >= CHIP_R600) {
0315         if (rdev->family >= CHIP_RV770)
0316             blackout = RREG32(R700_MC_CITF_CNTL);
0317         else
0318             blackout = RREG32(R600_CITF_CNTL);
0319         if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) {
0320             /* Block CPU access */
0321             WREG32(R600_BIF_FB_EN, 0);
0322             /* blackout the MC */
0323             blackout |= R600_BLACKOUT_MASK;
0324             if (rdev->family >= CHIP_RV770)
0325                 WREG32(R700_MC_CITF_CNTL, blackout);
0326             else
0327                 WREG32(R600_CITF_CNTL, blackout);
0328         }
0329     }
0330     /* wait for the MC to settle */
0331     udelay(100);
0332 
0333     /* lock double buffered regs */
0334     for (i = 0; i < rdev->num_crtc; i++) {
0335         if (save->crtc_enabled[i]) {
0336             tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
0337             if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
0338                 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
0339                 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
0340             }
0341             tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
0342             if (!(tmp & 1)) {
0343                 tmp |= 1;
0344                 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
0345             }
0346         }
0347     }
0348 }
0349 
0350 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
0351 {
0352     u32 tmp, frame_count;
0353     int i, j;
0354 
0355     /* update crtc base addresses */
0356     for (i = 0; i < rdev->num_crtc; i++) {
0357         if (rdev->family >= CHIP_RV770) {
0358             if (i == 0) {
0359                 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
0360                        upper_32_bits(rdev->mc.vram_start));
0361                 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
0362                        upper_32_bits(rdev->mc.vram_start));
0363             } else {
0364                 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
0365                        upper_32_bits(rdev->mc.vram_start));
0366                 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
0367                        upper_32_bits(rdev->mc.vram_start));
0368             }
0369         }
0370         WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
0371                (u32)rdev->mc.vram_start);
0372         WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
0373                (u32)rdev->mc.vram_start);
0374     }
0375     WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
0376 
0377     /* unlock regs and wait for update */
0378     for (i = 0; i < rdev->num_crtc; i++) {
0379         if (save->crtc_enabled[i]) {
0380             tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
0381             if ((tmp & 0x7) != 3) {
0382                 tmp &= ~0x7;
0383                 tmp |= 0x3;
0384                 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
0385             }
0386             tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
0387             if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
0388                 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
0389                 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
0390             }
0391             tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
0392             if (tmp & 1) {
0393                 tmp &= ~1;
0394                 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
0395             }
0396             for (j = 0; j < rdev->usec_timeout; j++) {
0397                 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
0398                 if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
0399                     break;
0400                 udelay(1);
0401             }
0402         }
0403     }
0404 
0405     if (rdev->family >= CHIP_R600) {
0406         /* unblackout the MC */
0407         if (rdev->family >= CHIP_RV770)
0408             tmp = RREG32(R700_MC_CITF_CNTL);
0409         else
0410             tmp = RREG32(R600_CITF_CNTL);
0411         tmp &= ~R600_BLACKOUT_MASK;
0412         if (rdev->family >= CHIP_RV770)
0413             WREG32(R700_MC_CITF_CNTL, tmp);
0414         else
0415             WREG32(R600_CITF_CNTL, tmp);
0416         /* allow CPU access */
0417         WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN);
0418     }
0419 
0420     for (i = 0; i < rdev->num_crtc; i++) {
0421         if (save->crtc_enabled[i]) {
0422             tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
0423             tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
0424             WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
0425             /* wait for the next frame */
0426             frame_count = radeon_get_vblank_counter(rdev, i);
0427             for (j = 0; j < rdev->usec_timeout; j++) {
0428                 if (radeon_get_vblank_counter(rdev, i) != frame_count)
0429                     break;
0430                 udelay(1);
0431             }
0432         }
0433     }
0434     /* Unlock vga access */
0435     WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
0436     mdelay(1);
0437     WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
0438 }
0439 
0440 static void rv515_mc_program(struct radeon_device *rdev)
0441 {
0442     struct rv515_mc_save save;
0443 
0444     /* Stops all mc clients */
0445     rv515_mc_stop(rdev, &save);
0446 
0447     /* Wait for mc idle */
0448     if (rv515_mc_wait_for_idle(rdev))
0449         dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
0450     /* Write VRAM size in case we are limiting it */
0451     WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
0452     /* Program MC, should be a 32bits limited address space */
0453     WREG32_MC(R_000001_MC_FB_LOCATION,
0454             S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
0455             S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
0456     WREG32(R_000134_HDP_FB_LOCATION,
0457         S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
0458     if (rdev->flags & RADEON_IS_AGP) {
0459         WREG32_MC(R_000002_MC_AGP_LOCATION,
0460             S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
0461             S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
0462         WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
0463         WREG32_MC(R_000004_MC_AGP_BASE_2,
0464             S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
0465     } else {
0466         WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
0467         WREG32_MC(R_000003_MC_AGP_BASE, 0);
0468         WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
0469     }
0470 
0471     rv515_mc_resume(rdev, &save);
0472 }
0473 
0474 void rv515_clock_startup(struct radeon_device *rdev)
0475 {
0476     if (radeon_dynclks != -1 && radeon_dynclks)
0477         radeon_atom_set_clock_gating(rdev, 1);
0478     /* We need to force on some of the block */
0479     WREG32_PLL(R_00000F_CP_DYN_CNTL,
0480         RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
0481     WREG32_PLL(R_000011_E2_DYN_CNTL,
0482         RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
0483     WREG32_PLL(R_000013_IDCT_DYN_CNTL,
0484         RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
0485 }
0486 
0487 static int rv515_startup(struct radeon_device *rdev)
0488 {
0489     int r;
0490 
0491     rv515_mc_program(rdev);
0492     /* Resume clock */
0493     rv515_clock_startup(rdev);
0494     /* Initialize GPU configuration (# pipes, ...) */
0495     rv515_gpu_init(rdev);
0496     /* Initialize GART (initialize after TTM so we can allocate
0497      * memory through TTM but finalize after TTM) */
0498     if (rdev->flags & RADEON_IS_PCIE) {
0499         r = rv370_pcie_gart_enable(rdev);
0500         if (r)
0501             return r;
0502     }
0503 
0504     /* allocate wb buffer */
0505     r = radeon_wb_init(rdev);
0506     if (r)
0507         return r;
0508 
0509     r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
0510     if (r) {
0511         dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
0512         return r;
0513     }
0514 
0515     /* Enable IRQ */
0516     if (!rdev->irq.installed) {
0517         r = radeon_irq_kms_init(rdev);
0518         if (r)
0519             return r;
0520     }
0521 
0522     rs600_irq_set(rdev);
0523     rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
0524     /* 1M ring buffer */
0525     r = r100_cp_init(rdev, 1024 * 1024);
0526     if (r) {
0527         dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
0528         return r;
0529     }
0530 
0531     r = radeon_ib_pool_init(rdev);
0532     if (r) {
0533         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
0534         return r;
0535     }
0536 
0537     return 0;
0538 }
0539 
0540 int rv515_resume(struct radeon_device *rdev)
0541 {
0542     int r;
0543 
0544     /* Make sur GART are not working */
0545     if (rdev->flags & RADEON_IS_PCIE)
0546         rv370_pcie_gart_disable(rdev);
0547     /* Resume clock before doing reset */
0548     rv515_clock_startup(rdev);
0549     /* Reset gpu before posting otherwise ATOM will enter infinite loop */
0550     if (radeon_asic_reset(rdev)) {
0551         dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
0552             RREG32(R_000E40_RBBM_STATUS),
0553             RREG32(R_0007C0_CP_STAT));
0554     }
0555     /* post */
0556     atom_asic_init(rdev->mode_info.atom_context);
0557     /* Resume clock after posting */
0558     rv515_clock_startup(rdev);
0559     /* Initialize surface registers */
0560     radeon_surface_init(rdev);
0561 
0562     rdev->accel_working = true;
0563     r =  rv515_startup(rdev);
0564     if (r) {
0565         rdev->accel_working = false;
0566     }
0567     return r;
0568 }
0569 
0570 int rv515_suspend(struct radeon_device *rdev)
0571 {
0572     radeon_pm_suspend(rdev);
0573     r100_cp_disable(rdev);
0574     radeon_wb_disable(rdev);
0575     rs600_irq_disable(rdev);
0576     if (rdev->flags & RADEON_IS_PCIE)
0577         rv370_pcie_gart_disable(rdev);
0578     return 0;
0579 }
0580 
0581 void rv515_set_safe_registers(struct radeon_device *rdev)
0582 {
0583     rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
0584     rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
0585 }
0586 
0587 void rv515_fini(struct radeon_device *rdev)
0588 {
0589     radeon_pm_fini(rdev);
0590     r100_cp_fini(rdev);
0591     radeon_wb_fini(rdev);
0592     radeon_ib_pool_fini(rdev);
0593     radeon_gem_fini(rdev);
0594     rv370_pcie_gart_fini(rdev);
0595     radeon_agp_fini(rdev);
0596     radeon_irq_kms_fini(rdev);
0597     radeon_fence_driver_fini(rdev);
0598     radeon_bo_fini(rdev);
0599     radeon_atombios_fini(rdev);
0600     kfree(rdev->bios);
0601     rdev->bios = NULL;
0602 }
0603 
0604 int rv515_init(struct radeon_device *rdev)
0605 {
0606     int r;
0607 
0608     /* Initialize scratch registers */
0609     radeon_scratch_init(rdev);
0610     /* Initialize surface registers */
0611     radeon_surface_init(rdev);
0612     /* TODO: disable VGA need to use VGA request */
0613     /* restore some register to sane defaults */
0614     r100_restore_sanity(rdev);
0615     /* BIOS*/
0616     if (!radeon_get_bios(rdev)) {
0617         if (ASIC_IS_AVIVO(rdev))
0618             return -EINVAL;
0619     }
0620     if (rdev->is_atom_bios) {
0621         r = radeon_atombios_init(rdev);
0622         if (r)
0623             return r;
0624     } else {
0625         dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
0626         return -EINVAL;
0627     }
0628     /* Reset gpu before posting otherwise ATOM will enter infinite loop */
0629     if (radeon_asic_reset(rdev)) {
0630         dev_warn(rdev->dev,
0631             "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
0632             RREG32(R_000E40_RBBM_STATUS),
0633             RREG32(R_0007C0_CP_STAT));
0634     }
0635     /* check if cards are posted or not */
0636     if (radeon_boot_test_post_card(rdev) == false)
0637         return -EINVAL;
0638     /* Initialize clocks */
0639     radeon_get_clock_info(rdev->ddev);
0640     /* initialize AGP */
0641     if (rdev->flags & RADEON_IS_AGP) {
0642         r = radeon_agp_init(rdev);
0643         if (r) {
0644             radeon_agp_disable(rdev);
0645         }
0646     }
0647     /* initialize memory controller */
0648     rv515_mc_init(rdev);
0649     rv515_debugfs(rdev);
0650     /* Fence driver */
0651     radeon_fence_driver_init(rdev);
0652     /* Memory manager */
0653     r = radeon_bo_init(rdev);
0654     if (r)
0655         return r;
0656     r = rv370_pcie_gart_init(rdev);
0657     if (r)
0658         return r;
0659     rv515_set_safe_registers(rdev);
0660 
0661     /* Initialize power management */
0662     radeon_pm_init(rdev);
0663 
0664     rdev->accel_working = true;
0665     r = rv515_startup(rdev);
0666     if (r) {
0667         /* Somethings want wront with the accel init stop accel */
0668         dev_err(rdev->dev, "Disabling GPU acceleration\n");
0669         r100_cp_fini(rdev);
0670         radeon_wb_fini(rdev);
0671         radeon_ib_pool_fini(rdev);
0672         radeon_irq_kms_fini(rdev);
0673         rv370_pcie_gart_fini(rdev);
0674         radeon_agp_fini(rdev);
0675         rdev->accel_working = false;
0676     }
0677     return 0;
0678 }
0679 
0680 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
0681 {
0682     int index_reg = 0x6578 + crtc->crtc_offset;
0683     int data_reg = 0x657c + crtc->crtc_offset;
0684 
0685     WREG32(0x659C + crtc->crtc_offset, 0x0);
0686     WREG32(0x6594 + crtc->crtc_offset, 0x705);
0687     WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
0688     WREG32(0x65D8 + crtc->crtc_offset, 0x0);
0689     WREG32(0x65B0 + crtc->crtc_offset, 0x0);
0690     WREG32(0x65C0 + crtc->crtc_offset, 0x0);
0691     WREG32(0x65D4 + crtc->crtc_offset, 0x0);
0692     WREG32(index_reg, 0x0);
0693     WREG32(data_reg, 0x841880A8);
0694     WREG32(index_reg, 0x1);
0695     WREG32(data_reg, 0x84208680);
0696     WREG32(index_reg, 0x2);
0697     WREG32(data_reg, 0xBFF880B0);
0698     WREG32(index_reg, 0x100);
0699     WREG32(data_reg, 0x83D88088);
0700     WREG32(index_reg, 0x101);
0701     WREG32(data_reg, 0x84608680);
0702     WREG32(index_reg, 0x102);
0703     WREG32(data_reg, 0xBFF080D0);
0704     WREG32(index_reg, 0x200);
0705     WREG32(data_reg, 0x83988068);
0706     WREG32(index_reg, 0x201);
0707     WREG32(data_reg, 0x84A08680);
0708     WREG32(index_reg, 0x202);
0709     WREG32(data_reg, 0xBFF080F8);
0710     WREG32(index_reg, 0x300);
0711     WREG32(data_reg, 0x83588058);
0712     WREG32(index_reg, 0x301);
0713     WREG32(data_reg, 0x84E08660);
0714     WREG32(index_reg, 0x302);
0715     WREG32(data_reg, 0xBFF88120);
0716     WREG32(index_reg, 0x400);
0717     WREG32(data_reg, 0x83188040);
0718     WREG32(index_reg, 0x401);
0719     WREG32(data_reg, 0x85008660);
0720     WREG32(index_reg, 0x402);
0721     WREG32(data_reg, 0xBFF88150);
0722     WREG32(index_reg, 0x500);
0723     WREG32(data_reg, 0x82D88030);
0724     WREG32(index_reg, 0x501);
0725     WREG32(data_reg, 0x85408640);
0726     WREG32(index_reg, 0x502);
0727     WREG32(data_reg, 0xBFF88180);
0728     WREG32(index_reg, 0x600);
0729     WREG32(data_reg, 0x82A08018);
0730     WREG32(index_reg, 0x601);
0731     WREG32(data_reg, 0x85808620);
0732     WREG32(index_reg, 0x602);
0733     WREG32(data_reg, 0xBFF081B8);
0734     WREG32(index_reg, 0x700);
0735     WREG32(data_reg, 0x82608010);
0736     WREG32(index_reg, 0x701);
0737     WREG32(data_reg, 0x85A08600);
0738     WREG32(index_reg, 0x702);
0739     WREG32(data_reg, 0x800081F0);
0740     WREG32(index_reg, 0x800);
0741     WREG32(data_reg, 0x8228BFF8);
0742     WREG32(index_reg, 0x801);
0743     WREG32(data_reg, 0x85E085E0);
0744     WREG32(index_reg, 0x802);
0745     WREG32(data_reg, 0xBFF88228);
0746     WREG32(index_reg, 0x10000);
0747     WREG32(data_reg, 0x82A8BF00);
0748     WREG32(index_reg, 0x10001);
0749     WREG32(data_reg, 0x82A08CC0);
0750     WREG32(index_reg, 0x10002);
0751     WREG32(data_reg, 0x8008BEF8);
0752     WREG32(index_reg, 0x10100);
0753     WREG32(data_reg, 0x81F0BF28);
0754     WREG32(index_reg, 0x10101);
0755     WREG32(data_reg, 0x83608CA0);
0756     WREG32(index_reg, 0x10102);
0757     WREG32(data_reg, 0x8018BED0);
0758     WREG32(index_reg, 0x10200);
0759     WREG32(data_reg, 0x8148BF38);
0760     WREG32(index_reg, 0x10201);
0761     WREG32(data_reg, 0x84408C80);
0762     WREG32(index_reg, 0x10202);
0763     WREG32(data_reg, 0x8008BEB8);
0764     WREG32(index_reg, 0x10300);
0765     WREG32(data_reg, 0x80B0BF78);
0766     WREG32(index_reg, 0x10301);
0767     WREG32(data_reg, 0x85008C20);
0768     WREG32(index_reg, 0x10302);
0769     WREG32(data_reg, 0x8020BEA0);
0770     WREG32(index_reg, 0x10400);
0771     WREG32(data_reg, 0x8028BF90);
0772     WREG32(index_reg, 0x10401);
0773     WREG32(data_reg, 0x85E08BC0);
0774     WREG32(index_reg, 0x10402);
0775     WREG32(data_reg, 0x8018BE90);
0776     WREG32(index_reg, 0x10500);
0777     WREG32(data_reg, 0xBFB8BFB0);
0778     WREG32(index_reg, 0x10501);
0779     WREG32(data_reg, 0x86C08B40);
0780     WREG32(index_reg, 0x10502);
0781     WREG32(data_reg, 0x8010BE90);
0782     WREG32(index_reg, 0x10600);
0783     WREG32(data_reg, 0xBF58BFC8);
0784     WREG32(index_reg, 0x10601);
0785     WREG32(data_reg, 0x87A08AA0);
0786     WREG32(index_reg, 0x10602);
0787     WREG32(data_reg, 0x8010BE98);
0788     WREG32(index_reg, 0x10700);
0789     WREG32(data_reg, 0xBF10BFF0);
0790     WREG32(index_reg, 0x10701);
0791     WREG32(data_reg, 0x886089E0);
0792     WREG32(index_reg, 0x10702);
0793     WREG32(data_reg, 0x8018BEB0);
0794     WREG32(index_reg, 0x10800);
0795     WREG32(data_reg, 0xBED8BFE8);
0796     WREG32(index_reg, 0x10801);
0797     WREG32(data_reg, 0x89408940);
0798     WREG32(index_reg, 0x10802);
0799     WREG32(data_reg, 0xBFE8BED8);
0800     WREG32(index_reg, 0x20000);
0801     WREG32(data_reg, 0x80008000);
0802     WREG32(index_reg, 0x20001);
0803     WREG32(data_reg, 0x90008000);
0804     WREG32(index_reg, 0x20002);
0805     WREG32(data_reg, 0x80008000);
0806     WREG32(index_reg, 0x20003);
0807     WREG32(data_reg, 0x80008000);
0808     WREG32(index_reg, 0x20100);
0809     WREG32(data_reg, 0x80108000);
0810     WREG32(index_reg, 0x20101);
0811     WREG32(data_reg, 0x8FE0BF70);
0812     WREG32(index_reg, 0x20102);
0813     WREG32(data_reg, 0xBFE880C0);
0814     WREG32(index_reg, 0x20103);
0815     WREG32(data_reg, 0x80008000);
0816     WREG32(index_reg, 0x20200);
0817     WREG32(data_reg, 0x8018BFF8);
0818     WREG32(index_reg, 0x20201);
0819     WREG32(data_reg, 0x8F80BF08);
0820     WREG32(index_reg, 0x20202);
0821     WREG32(data_reg, 0xBFD081A0);
0822     WREG32(index_reg, 0x20203);
0823     WREG32(data_reg, 0xBFF88000);
0824     WREG32(index_reg, 0x20300);
0825     WREG32(data_reg, 0x80188000);
0826     WREG32(index_reg, 0x20301);
0827     WREG32(data_reg, 0x8EE0BEC0);
0828     WREG32(index_reg, 0x20302);
0829     WREG32(data_reg, 0xBFB082A0);
0830     WREG32(index_reg, 0x20303);
0831     WREG32(data_reg, 0x80008000);
0832     WREG32(index_reg, 0x20400);
0833     WREG32(data_reg, 0x80188000);
0834     WREG32(index_reg, 0x20401);
0835     WREG32(data_reg, 0x8E00BEA0);
0836     WREG32(index_reg, 0x20402);
0837     WREG32(data_reg, 0xBF8883C0);
0838     WREG32(index_reg, 0x20403);
0839     WREG32(data_reg, 0x80008000);
0840     WREG32(index_reg, 0x20500);
0841     WREG32(data_reg, 0x80188000);
0842     WREG32(index_reg, 0x20501);
0843     WREG32(data_reg, 0x8D00BE90);
0844     WREG32(index_reg, 0x20502);
0845     WREG32(data_reg, 0xBF588500);
0846     WREG32(index_reg, 0x20503);
0847     WREG32(data_reg, 0x80008008);
0848     WREG32(index_reg, 0x20600);
0849     WREG32(data_reg, 0x80188000);
0850     WREG32(index_reg, 0x20601);
0851     WREG32(data_reg, 0x8BC0BE98);
0852     WREG32(index_reg, 0x20602);
0853     WREG32(data_reg, 0xBF308660);
0854     WREG32(index_reg, 0x20603);
0855     WREG32(data_reg, 0x80008008);
0856     WREG32(index_reg, 0x20700);
0857     WREG32(data_reg, 0x80108000);
0858     WREG32(index_reg, 0x20701);
0859     WREG32(data_reg, 0x8A80BEB0);
0860     WREG32(index_reg, 0x20702);
0861     WREG32(data_reg, 0xBF0087C0);
0862     WREG32(index_reg, 0x20703);
0863     WREG32(data_reg, 0x80008008);
0864     WREG32(index_reg, 0x20800);
0865     WREG32(data_reg, 0x80108000);
0866     WREG32(index_reg, 0x20801);
0867     WREG32(data_reg, 0x8920BED0);
0868     WREG32(index_reg, 0x20802);
0869     WREG32(data_reg, 0xBED08920);
0870     WREG32(index_reg, 0x20803);
0871     WREG32(data_reg, 0x80008010);
0872     WREG32(index_reg, 0x30000);
0873     WREG32(data_reg, 0x90008000);
0874     WREG32(index_reg, 0x30001);
0875     WREG32(data_reg, 0x80008000);
0876     WREG32(index_reg, 0x30100);
0877     WREG32(data_reg, 0x8FE0BF90);
0878     WREG32(index_reg, 0x30101);
0879     WREG32(data_reg, 0xBFF880A0);
0880     WREG32(index_reg, 0x30200);
0881     WREG32(data_reg, 0x8F60BF40);
0882     WREG32(index_reg, 0x30201);
0883     WREG32(data_reg, 0xBFE88180);
0884     WREG32(index_reg, 0x30300);
0885     WREG32(data_reg, 0x8EC0BF00);
0886     WREG32(index_reg, 0x30301);
0887     WREG32(data_reg, 0xBFC88280);
0888     WREG32(index_reg, 0x30400);
0889     WREG32(data_reg, 0x8DE0BEE0);
0890     WREG32(index_reg, 0x30401);
0891     WREG32(data_reg, 0xBFA083A0);
0892     WREG32(index_reg, 0x30500);
0893     WREG32(data_reg, 0x8CE0BED0);
0894     WREG32(index_reg, 0x30501);
0895     WREG32(data_reg, 0xBF7884E0);
0896     WREG32(index_reg, 0x30600);
0897     WREG32(data_reg, 0x8BA0BED8);
0898     WREG32(index_reg, 0x30601);
0899     WREG32(data_reg, 0xBF508640);
0900     WREG32(index_reg, 0x30700);
0901     WREG32(data_reg, 0x8A60BEE8);
0902     WREG32(index_reg, 0x30701);
0903     WREG32(data_reg, 0xBF2087A0);
0904     WREG32(index_reg, 0x30800);
0905     WREG32(data_reg, 0x8900BF00);
0906     WREG32(index_reg, 0x30801);
0907     WREG32(data_reg, 0xBF008900);
0908 }
0909 
0910 struct rv515_watermark {
0911     u32        lb_request_fifo_depth;
0912     fixed20_12 num_line_pair;
0913     fixed20_12 estimated_width;
0914     fixed20_12 worst_case_latency;
0915     fixed20_12 consumption_rate;
0916     fixed20_12 active_time;
0917     fixed20_12 dbpp;
0918     fixed20_12 priority_mark_max;
0919     fixed20_12 priority_mark;
0920     fixed20_12 sclk;
0921 };
0922 
0923 static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
0924                      struct radeon_crtc *crtc,
0925                      struct rv515_watermark *wm,
0926                      bool low)
0927 {
0928     struct drm_display_mode *mode = &crtc->base.mode;
0929     fixed20_12 a, b, c;
0930     fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
0931     fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
0932     fixed20_12 sclk;
0933     u32 selected_sclk;
0934 
0935     if (!crtc->base.enabled) {
0936         /* FIXME: wouldn't it better to set priority mark to maximum */
0937         wm->lb_request_fifo_depth = 4;
0938         return;
0939     }
0940 
0941     /* rv6xx, rv7xx */
0942     if ((rdev->family >= CHIP_RV610) &&
0943         (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
0944         selected_sclk = radeon_dpm_get_sclk(rdev, low);
0945     else
0946         selected_sclk = rdev->pm.current_sclk;
0947 
0948     /* sclk in Mhz */
0949     a.full = dfixed_const(100);
0950     sclk.full = dfixed_const(selected_sclk);
0951     sclk.full = dfixed_div(sclk, a);
0952 
0953     if (crtc->vsc.full > dfixed_const(2))
0954         wm->num_line_pair.full = dfixed_const(2);
0955     else
0956         wm->num_line_pair.full = dfixed_const(1);
0957 
0958     b.full = dfixed_const(mode->crtc_hdisplay);
0959     c.full = dfixed_const(256);
0960     a.full = dfixed_div(b, c);
0961     request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
0962     request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
0963     if (a.full < dfixed_const(4)) {
0964         wm->lb_request_fifo_depth = 4;
0965     } else {
0966         wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
0967     }
0968 
0969     /* Determine consumption rate
0970      *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
0971      *  vtaps = number of vertical taps,
0972      *  vsc = vertical scaling ratio, defined as source/destination
0973      *  hsc = horizontal scaling ration, defined as source/destination
0974      */
0975     a.full = dfixed_const(mode->clock);
0976     b.full = dfixed_const(1000);
0977     a.full = dfixed_div(a, b);
0978     pclk.full = dfixed_div(b, a);
0979     if (crtc->rmx_type != RMX_OFF) {
0980         b.full = dfixed_const(2);
0981         if (crtc->vsc.full > b.full)
0982             b.full = crtc->vsc.full;
0983         b.full = dfixed_mul(b, crtc->hsc);
0984         c.full = dfixed_const(2);
0985         b.full = dfixed_div(b, c);
0986         consumption_time.full = dfixed_div(pclk, b);
0987     } else {
0988         consumption_time.full = pclk.full;
0989     }
0990     a.full = dfixed_const(1);
0991     wm->consumption_rate.full = dfixed_div(a, consumption_time);
0992 
0993 
0994     /* Determine line time
0995      *  LineTime = total time for one line of displayhtotal
0996      *  LineTime = total number of horizontal pixels
0997      *  pclk = pixel clock period(ns)
0998      */
0999     a.full = dfixed_const(crtc->base.mode.crtc_htotal);
1000     line_time.full = dfixed_mul(a, pclk);
1001 
1002     /* Determine active time
1003      *  ActiveTime = time of active region of display within one line,
1004      *  hactive = total number of horizontal active pixels
1005      *  htotal = total number of horizontal pixels
1006      */
1007     a.full = dfixed_const(crtc->base.mode.crtc_htotal);
1008     b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
1009     wm->active_time.full = dfixed_mul(line_time, b);
1010     wm->active_time.full = dfixed_div(wm->active_time, a);
1011 
1012     /* Determine chunk time
1013      * ChunkTime = the time it takes the DCP to send one chunk of data
1014      * to the LB which consists of pipeline delay and inter chunk gap
1015      * sclk = system clock(Mhz)
1016      */
1017     a.full = dfixed_const(600 * 1000);
1018     chunk_time.full = dfixed_div(a, sclk);
1019     read_delay_latency.full = dfixed_const(1000);
1020 
1021     /* Determine the worst case latency
1022      * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
1023      * WorstCaseLatency = worst case time from urgent to when the MC starts
1024      *                    to return data
1025      * READ_DELAY_IDLE_MAX = constant of 1us
1026      * ChunkTime = time it takes the DCP to send one chunk of data to the LB
1027      *             which consists of pipeline delay and inter chunk gap
1028      */
1029     if (dfixed_trunc(wm->num_line_pair) > 1) {
1030         a.full = dfixed_const(3);
1031         wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
1032         wm->worst_case_latency.full += read_delay_latency.full;
1033     } else {
1034         wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
1035     }
1036 
1037     /* Determine the tolerable latency
1038      * TolerableLatency = Any given request has only 1 line time
1039      *                    for the data to be returned
1040      * LBRequestFifoDepth = Number of chunk requests the LB can
1041      *                      put into the request FIFO for a display
1042      *  LineTime = total time for one line of display
1043      *  ChunkTime = the time it takes the DCP to send one chunk
1044      *              of data to the LB which consists of
1045      *  pipeline delay and inter chunk gap
1046      */
1047     if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
1048         tolerable_latency.full = line_time.full;
1049     } else {
1050         tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
1051         tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
1052         tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
1053         tolerable_latency.full = line_time.full - tolerable_latency.full;
1054     }
1055     /* We assume worst case 32bits (4 bytes) */
1056     wm->dbpp.full = dfixed_const(2 * 16);
1057 
1058     /* Determine the maximum priority mark
1059      *  width = viewport width in pixels
1060      */
1061     a.full = dfixed_const(16);
1062     wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
1063     wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
1064     wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
1065 
1066     /* Determine estimated width */
1067     estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
1068     estimated_width.full = dfixed_div(estimated_width, consumption_time);
1069     if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
1070         wm->priority_mark.full = wm->priority_mark_max.full;
1071     } else {
1072         a.full = dfixed_const(16);
1073         wm->priority_mark.full = dfixed_div(estimated_width, a);
1074         wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
1075         wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
1076     }
1077 }
1078 
1079 static void rv515_compute_mode_priority(struct radeon_device *rdev,
1080                     struct rv515_watermark *wm0,
1081                     struct rv515_watermark *wm1,
1082                     struct drm_display_mode *mode0,
1083                     struct drm_display_mode *mode1,
1084                     u32 *d1mode_priority_a_cnt,
1085                     u32 *d2mode_priority_a_cnt)
1086 {
1087     fixed20_12 priority_mark02, priority_mark12, fill_rate;
1088     fixed20_12 a, b;
1089 
1090     *d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
1091     *d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
1092 
1093     if (mode0 && mode1) {
1094         if (dfixed_trunc(wm0->dbpp) > 64)
1095             a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
1096         else
1097             a.full = wm0->num_line_pair.full;
1098         if (dfixed_trunc(wm1->dbpp) > 64)
1099             b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
1100         else
1101             b.full = wm1->num_line_pair.full;
1102         a.full += b.full;
1103         fill_rate.full = dfixed_div(wm0->sclk, a);
1104         if (wm0->consumption_rate.full > fill_rate.full) {
1105             b.full = wm0->consumption_rate.full - fill_rate.full;
1106             b.full = dfixed_mul(b, wm0->active_time);
1107             a.full = dfixed_const(16);
1108             b.full = dfixed_div(b, a);
1109             a.full = dfixed_mul(wm0->worst_case_latency,
1110                         wm0->consumption_rate);
1111             priority_mark02.full = a.full + b.full;
1112         } else {
1113             a.full = dfixed_mul(wm0->worst_case_latency,
1114                         wm0->consumption_rate);
1115             b.full = dfixed_const(16 * 1000);
1116             priority_mark02.full = dfixed_div(a, b);
1117         }
1118         if (wm1->consumption_rate.full > fill_rate.full) {
1119             b.full = wm1->consumption_rate.full - fill_rate.full;
1120             b.full = dfixed_mul(b, wm1->active_time);
1121             a.full = dfixed_const(16);
1122             b.full = dfixed_div(b, a);
1123             a.full = dfixed_mul(wm1->worst_case_latency,
1124                         wm1->consumption_rate);
1125             priority_mark12.full = a.full + b.full;
1126         } else {
1127             a.full = dfixed_mul(wm1->worst_case_latency,
1128                         wm1->consumption_rate);
1129             b.full = dfixed_const(16 * 1000);
1130             priority_mark12.full = dfixed_div(a, b);
1131         }
1132         if (wm0->priority_mark.full > priority_mark02.full)
1133             priority_mark02.full = wm0->priority_mark.full;
1134         if (wm0->priority_mark_max.full > priority_mark02.full)
1135             priority_mark02.full = wm0->priority_mark_max.full;
1136         if (wm1->priority_mark.full > priority_mark12.full)
1137             priority_mark12.full = wm1->priority_mark.full;
1138         if (wm1->priority_mark_max.full > priority_mark12.full)
1139             priority_mark12.full = wm1->priority_mark_max.full;
1140         *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1141         *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1142         if (rdev->disp_priority == 2) {
1143             *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1144             *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1145         }
1146     } else if (mode0) {
1147         if (dfixed_trunc(wm0->dbpp) > 64)
1148             a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
1149         else
1150             a.full = wm0->num_line_pair.full;
1151         fill_rate.full = dfixed_div(wm0->sclk, a);
1152         if (wm0->consumption_rate.full > fill_rate.full) {
1153             b.full = wm0->consumption_rate.full - fill_rate.full;
1154             b.full = dfixed_mul(b, wm0->active_time);
1155             a.full = dfixed_const(16);
1156             b.full = dfixed_div(b, a);
1157             a.full = dfixed_mul(wm0->worst_case_latency,
1158                         wm0->consumption_rate);
1159             priority_mark02.full = a.full + b.full;
1160         } else {
1161             a.full = dfixed_mul(wm0->worst_case_latency,
1162                         wm0->consumption_rate);
1163             b.full = dfixed_const(16);
1164             priority_mark02.full = dfixed_div(a, b);
1165         }
1166         if (wm0->priority_mark.full > priority_mark02.full)
1167             priority_mark02.full = wm0->priority_mark.full;
1168         if (wm0->priority_mark_max.full > priority_mark02.full)
1169             priority_mark02.full = wm0->priority_mark_max.full;
1170         *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1171         if (rdev->disp_priority == 2)
1172             *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1173     } else if (mode1) {
1174         if (dfixed_trunc(wm1->dbpp) > 64)
1175             a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
1176         else
1177             a.full = wm1->num_line_pair.full;
1178         fill_rate.full = dfixed_div(wm1->sclk, a);
1179         if (wm1->consumption_rate.full > fill_rate.full) {
1180             b.full = wm1->consumption_rate.full - fill_rate.full;
1181             b.full = dfixed_mul(b, wm1->active_time);
1182             a.full = dfixed_const(16);
1183             b.full = dfixed_div(b, a);
1184             a.full = dfixed_mul(wm1->worst_case_latency,
1185                         wm1->consumption_rate);
1186             priority_mark12.full = a.full + b.full;
1187         } else {
1188             a.full = dfixed_mul(wm1->worst_case_latency,
1189                         wm1->consumption_rate);
1190             b.full = dfixed_const(16 * 1000);
1191             priority_mark12.full = dfixed_div(a, b);
1192         }
1193         if (wm1->priority_mark.full > priority_mark12.full)
1194             priority_mark12.full = wm1->priority_mark.full;
1195         if (wm1->priority_mark_max.full > priority_mark12.full)
1196             priority_mark12.full = wm1->priority_mark_max.full;
1197         *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1198         if (rdev->disp_priority == 2)
1199             *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1200     }
1201 }
1202 
1203 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1204 {
1205     struct drm_display_mode *mode0 = NULL;
1206     struct drm_display_mode *mode1 = NULL;
1207     struct rv515_watermark wm0_high, wm0_low;
1208     struct rv515_watermark wm1_high, wm1_low;
1209     u32 tmp;
1210     u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
1211     u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
1212 
1213     if (rdev->mode_info.crtcs[0]->base.enabled)
1214         mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1215     if (rdev->mode_info.crtcs[1]->base.enabled)
1216         mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1217     rs690_line_buffer_adjust(rdev, mode0, mode1);
1218 
1219     rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
1220     rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
1221 
1222     rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false);
1223     rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false);
1224 
1225     tmp = wm0_high.lb_request_fifo_depth;
1226     tmp |= wm1_high.lb_request_fifo_depth << 16;
1227     WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
1228 
1229     rv515_compute_mode_priority(rdev,
1230                     &wm0_high, &wm1_high,
1231                     mode0, mode1,
1232                     &d1mode_priority_a_cnt, &d2mode_priority_a_cnt);
1233     rv515_compute_mode_priority(rdev,
1234                     &wm0_low, &wm1_low,
1235                     mode0, mode1,
1236                     &d1mode_priority_b_cnt, &d2mode_priority_b_cnt);
1237 
1238     WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1239     WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
1240     WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1241     WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);
1242 }
1243 
1244 void rv515_bandwidth_update(struct radeon_device *rdev)
1245 {
1246     uint32_t tmp;
1247     struct drm_display_mode *mode0 = NULL;
1248     struct drm_display_mode *mode1 = NULL;
1249 
1250     if (!rdev->mode_info.mode_config_initialized)
1251         return;
1252 
1253     radeon_update_display_priority(rdev);
1254 
1255     if (rdev->mode_info.crtcs[0]->base.enabled)
1256         mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1257     if (rdev->mode_info.crtcs[1]->base.enabled)
1258         mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1259     /*
1260      * Set display0/1 priority up in the memory controller for
1261      * modes if the user specifies HIGH for displaypriority
1262      * option.
1263      */
1264     if ((rdev->disp_priority == 2) &&
1265         (rdev->family == CHIP_RV515)) {
1266         tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1267         tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1268         tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1269         if (mode1)
1270             tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1271         if (mode0)
1272             tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1273         WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1274     }
1275     rv515_bandwidth_avivo_update(rdev);
1276 }
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