drm/radeon/rs780d.h

0001 /*
0002  * Copyright 2011 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __RS780D_H__
0024 #define __RS780D_H__
0025
0026 #define CG_SPLL_FUNC_CNTL                                 0x600
0027 #       define SPLL_RESET                                (1 << 0)
0028 #       define SPLL_SLEEP                                (1 << 1)
0029 #       define SPLL_REF_DIV(x)                           ((x) << 2)
0030 #       define SPLL_REF_DIV_MASK                         (7 << 2)
0031 #       define SPLL_REF_DIV_SHIFT                        2
0032 #       define SPLL_FB_DIV(x)                            ((x) << 5)
0033 #       define SPLL_FB_DIV_MASK                          (0xff << 2)
0034 #       define SPLL_FB_DIV_SHIFT                         2
0035 #       define SPLL_PULSEEN                              (1 << 13)
0036 #       define SPLL_PULSENUM(x)                          ((x) << 14)
0037 #       define SPLL_PULSENUM_MASK                        (3 << 14)
0038 #       define SPLL_SW_HILEN(x)                          ((x) << 16)
0039 #       define SPLL_SW_HILEN_MASK                        (0xf << 16)
0040 #       define SPLL_SW_HILEN_SHIFT                       16
0041 #       define SPLL_SW_LOLEN(x)                          ((x) << 20)
0042 #       define SPLL_SW_LOLEN_MASK                        (0xf << 20)
0043 #       define SPLL_SW_LOLEN_SHIFT                       20
0044 #       define SPLL_DIVEN                                (1 << 24)
0045 #       define SPLL_BYPASS_EN                            (1 << 25)
0046 #       define SPLL_CHG_STATUS                           (1 << 29)
0047 #       define SPLL_CTLREQ                               (1 << 30)
0048 #       define SPLL_CTLACK                               (1 << 31)
0049
0050 /* RS780/RS880 PM */
0051 #define FVTHROT_CNTRL_REG               0x3000
0052 #define     DONT_WAIT_FOR_FBDIV_WRAP        (1 << 0)
0053 #define     MINIMUM_CIP(x)              ((x) << 1)
0054 #define     MINIMUM_CIP_SHIFT           1
0055 #define     MINIMUM_CIP_MASK            0x1fffffe
0056 #define     REFRESH_RATE_DIVISOR(x)         ((x) << 25)
0057 #define     REFRESH_RATE_DIVISOR_SHIFT      25
0058 #define     REFRESH_RATE_DIVISOR_MASK       (0x3 << 25)
0059 #define     ENABLE_FV_THROT             (1 << 27)
0060 #define     ENABLE_FV_UPDATE            (1 << 28)
0061 #define     TREND_SEL_MODE              (1 << 29)
0062 #define     FORCE_TREND_SEL             (1 << 30)
0063 #define     ENABLE_FV_THROT_IO          (1 << 31)
0064 #define FVTHROT_TARGET_REG              0x3004
0065 #define     TARGET_IDLE_COUNT(x)            ((x) << 0)
0066 #define     TARGET_IDLE_COUNT_MASK          0xffffff
0067 #define     TARGET_IDLE_COUNT_SHIFT         0
0068 #define FVTHROT_CB1                 0x3008
0069 #define FVTHROT_CB2                 0x300c
0070 #define FVTHROT_CB3                 0x3010
0071 #define FVTHROT_CB4                 0x3014
0072 #define FVTHROT_UTC0                    0x3018
0073 #define FVTHROT_UTC1                    0x301c
0074 #define FVTHROT_UTC2                    0x3020
0075 #define FVTHROT_UTC3                    0x3024
0076 #define FVTHROT_UTC4                    0x3028
0077 #define FVTHROT_DTC0                    0x302c
0078 #define FVTHROT_DTC1                    0x3030
0079 #define FVTHROT_DTC2                    0x3034
0080 #define FVTHROT_DTC3                    0x3038
0081 #define FVTHROT_DTC4                    0x303c
0082 #define FVTHROT_FBDIV_REG0              0x3040
0083 #define     MIN_FEEDBACK_DIV(x)         ((x) << 0)
0084 #define     MIN_FEEDBACK_DIV_MASK           0xfff
0085 #define     MIN_FEEDBACK_DIV_SHIFT          0
0086 #define     MAX_FEEDBACK_DIV(x)         ((x) << 12)
0087 #define     MAX_FEEDBACK_DIV_MASK           (0xfff << 12)
0088 #define     MAX_FEEDBACK_DIV_SHIFT          12
0089 #define FVTHROT_FBDIV_REG1              0x3044
0090 #define     MAX_FEEDBACK_STEP(x)            ((x) << 0)
0091 #define     MAX_FEEDBACK_STEP_MASK          0xfff
0092 #define     MAX_FEEDBACK_STEP_SHIFT         0
0093 #define     STARTING_FEEDBACK_DIV(x)        ((x) << 12)
0094 #define     STARTING_FEEDBACK_DIV_MASK      (0xfff << 12)
0095 #define     STARTING_FEEDBACK_DIV_SHIFT     12
0096 #define     FORCE_FEEDBACK_DIV          (1 << 24)
0097 #define FVTHROT_FBDIV_REG2              0x3048
0098 #define     FORCED_FEEDBACK_DIV(x)          ((x) << 0)
0099 #define     FORCED_FEEDBACK_DIV_MASK        0xfff
0100 #define     FORCED_FEEDBACK_DIV_SHIFT       0
0101 #define     FB_DIV_TIMER_VAL(x)         ((x) << 12)
0102 #define     FB_DIV_TIMER_VAL_MASK           (0xffff << 12)
0103 #define     FB_DIV_TIMER_VAL_SHIFT          12
0104 #define FVTHROT_FB_US_REG0              0x304c
0105 #define FVTHROT_FB_US_REG1              0x3050
0106 #define FVTHROT_FB_DS_REG0              0x3054
0107 #define FVTHROT_FB_DS_REG1              0x3058
0108 #define FVTHROT_PWM_CTRL_REG0               0x305c
0109 #define     STARTING_PWM_HIGHTIME(x)        ((x) << 0)
0110 #define     STARTING_PWM_HIGHTIME_MASK      0xfff
0111 #define     STARTING_PWM_HIGHTIME_SHIFT     0
0112 #define     NUMBER_OF_CYCLES_IN_PERIOD(x)       ((x) << 12)
0113 #define     NUMBER_OF_CYCLES_IN_PERIOD_MASK     (0xfff << 12)
0114 #define     NUMBER_OF_CYCLES_IN_PERIOD_SHIFT    12
0115 #define     FORCE_STARTING_PWM_HIGHTIME     (1 << 24)
0116 #define     INVERT_PWM_WAVEFORM         (1 << 25)
0117 #define FVTHROT_PWM_CTRL_REG1               0x3060
0118 #define     MIN_PWM_HIGHTIME(x)         ((x) << 0)
0119 #define     MIN_PWM_HIGHTIME_MASK           0xfff
0120 #define     MIN_PWM_HIGHTIME_SHIFT          0
0121 #define     MAX_PWM_HIGHTIME(x)         ((x) << 12)
0122 #define     MAX_PWM_HIGHTIME_MASK           (0xfff << 12)
0123 #define     MAX_PWM_HIGHTIME_SHIFT          12
0124 #define FVTHROT_PWM_US_REG0             0x3064
0125 #define FVTHROT_PWM_US_REG1             0x3068
0126 #define FVTHROT_PWM_DS_REG0             0x306c
0127 #define FVTHROT_PWM_DS_REG1             0x3070
0128 #define FVTHROT_STATUS_REG0             0x3074
0129 #define     CURRENT_FEEDBACK_DIV_MASK       0xfff
0130 #define     CURRENT_FEEDBACK_DIV_SHIFT      0
0131 #define FVTHROT_STATUS_REG1             0x3078
0132 #define FVTHROT_STATUS_REG2             0x307c
0133 #define CG_INTGFX_MISC                  0x3080
0134 #define     FVTHROT_VBLANK_SEL          (1 << 9)
0135 #define FVTHROT_PWM_FEEDBACK_DIV_REG1           0x308c
0136 #define     RANGE0_PWM_FEEDBACK_DIV(x)      ((x) << 0)
0137 #define     RANGE0_PWM_FEEDBACK_DIV_MASK        0xfff
0138 #define     RANGE0_PWM_FEEDBACK_DIV_SHIFT       0
0139 #define     RANGE_PWM_FEEDBACK_DIV_EN       (1 << 12)
0140 #define FVTHROT_PWM_FEEDBACK_DIV_REG2           0x3090
0141 #define     RANGE1_PWM_FEEDBACK_DIV(x)      ((x) << 0)
0142 #define     RANGE1_PWM_FEEDBACK_DIV_MASK        0xfff
0143 #define     RANGE1_PWM_FEEDBACK_DIV_SHIFT       0
0144 #define     RANGE2_PWM_FEEDBACK_DIV(x)      ((x) << 12)
0145 #define     RANGE2_PWM_FEEDBACK_DIV_MASK        (0xfff << 12)
0146 #define     RANGE2_PWM_FEEDBACK_DIV_SHIFT       12
0147 #define FVTHROT_PWM_FEEDBACK_DIV_REG3           0x3094
0148 #define     RANGE0_PWM(x)               ((x) << 0)
0149 #define     RANGE0_PWM_MASK             0xfff
0150 #define     RANGE0_PWM_SHIFT            0
0151 #define     RANGE1_PWM(x)               ((x) << 12)
0152 #define     RANGE1_PWM_MASK             (0xfff << 12)
0153 #define     RANGE1_PWM_SHIFT            12
0154 #define FVTHROT_PWM_FEEDBACK_DIV_REG4           0x3098
0155 #define     RANGE2_PWM(x)               ((x) << 0)
0156 #define     RANGE2_PWM_MASK             0xfff
0157 #define     RANGE2_PWM_SHIFT            0
0158 #define     RANGE3_PWM(x)               ((x) << 12)
0159 #define     RANGE3_PWM_MASK             (0xfff << 12)
0160 #define     RANGE3_PWM_SHIFT            12
0161 #define FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1      0x30ac
0162 #define     RANGE0_SLOW_CLK_FEEDBACK_DIV(x)     ((x) << 0)
0163 #define     RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK   0xfff
0164 #define     RANGE0_SLOW_CLK_FEEDBACK_DIV_SHIFT  0
0165 #define     RANGE_SLOW_CLK_FEEDBACK_DIV_EN      (1 << 12)
0166
0167 #define GFX_MACRO_BYPASS_CNTL               0x30c0
0168 #define     SPLL_BYPASS_CNTL            (1 << 0)
0169 #define     UPLL_BYPASS_CNTL            (1 << 1)
0170
0171 #endif