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0001 /*
0002  * Copyright 2011 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Alex Deucher
0023  */
0024 
0025 #include <linux/pci.h>
0026 #include <linux/seq_file.h>
0027 
0028 #include "atom.h"
0029 #include "r600_dpm.h"
0030 #include "radeon.h"
0031 #include "radeon_asic.h"
0032 #include "rs780_dpm.h"
0033 #include "rs780d.h"
0034 
0035 static struct igp_ps *rs780_get_ps(struct radeon_ps *rps)
0036 {
0037     struct igp_ps *ps = rps->ps_priv;
0038 
0039     return ps;
0040 }
0041 
0042 static struct igp_power_info *rs780_get_pi(struct radeon_device *rdev)
0043 {
0044     struct igp_power_info *pi = rdev->pm.dpm.priv;
0045 
0046     return pi;
0047 }
0048 
0049 static void rs780_get_pm_mode_parameters(struct radeon_device *rdev)
0050 {
0051     struct igp_power_info *pi = rs780_get_pi(rdev);
0052     struct radeon_mode_info *minfo = &rdev->mode_info;
0053     struct drm_crtc *crtc;
0054     struct radeon_crtc *radeon_crtc;
0055     int i;
0056 
0057     /* defaults */
0058     pi->crtc_id = 0;
0059     pi->refresh_rate = 60;
0060 
0061     for (i = 0; i < rdev->num_crtc; i++) {
0062         crtc = (struct drm_crtc *)minfo->crtcs[i];
0063         if (crtc && crtc->enabled) {
0064             radeon_crtc = to_radeon_crtc(crtc);
0065             pi->crtc_id = radeon_crtc->crtc_id;
0066             if (crtc->mode.htotal && crtc->mode.vtotal)
0067                 pi->refresh_rate = drm_mode_vrefresh(&crtc->mode);
0068             break;
0069         }
0070     }
0071 }
0072 
0073 static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable);
0074 
0075 static int rs780_initialize_dpm_power_state(struct radeon_device *rdev,
0076                         struct radeon_ps *boot_ps)
0077 {
0078     struct atom_clock_dividers dividers;
0079     struct igp_ps *default_state = rs780_get_ps(boot_ps);
0080     int i, ret;
0081 
0082     ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
0083                          default_state->sclk_low, false, &dividers);
0084     if (ret)
0085         return ret;
0086 
0087     r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div);
0088     r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div);
0089     r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div);
0090 
0091     if (dividers.enable_post_div)
0092         r600_engine_clock_entry_enable_post_divider(rdev, 0, true);
0093     else
0094         r600_engine_clock_entry_enable_post_divider(rdev, 0, false);
0095 
0096     r600_engine_clock_entry_set_step_time(rdev, 0, R600_SST_DFLT);
0097     r600_engine_clock_entry_enable_pulse_skipping(rdev, 0, false);
0098 
0099     r600_engine_clock_entry_enable(rdev, 0, true);
0100     for (i = 1; i < R600_PM_NUMBER_OF_SCLKS; i++)
0101         r600_engine_clock_entry_enable(rdev, i, false);
0102 
0103     r600_enable_mclk_control(rdev, false);
0104     r600_voltage_control_enable_pins(rdev, 0);
0105 
0106     return 0;
0107 }
0108 
0109 static int rs780_initialize_dpm_parameters(struct radeon_device *rdev,
0110                        struct radeon_ps *boot_ps)
0111 {
0112     int ret = 0;
0113     int i;
0114 
0115     r600_set_bsp(rdev, R600_BSU_DFLT, R600_BSP_DFLT);
0116 
0117     r600_set_at(rdev, 0, 0, 0, 0);
0118 
0119     r600_set_git(rdev, R600_GICST_DFLT);
0120 
0121     for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
0122         r600_set_tc(rdev, i, 0, 0);
0123 
0124     r600_select_td(rdev, R600_TD_DFLT);
0125     r600_set_vrc(rdev, 0);
0126 
0127     r600_set_tpu(rdev, R600_TPU_DFLT);
0128     r600_set_tpc(rdev, R600_TPC_DFLT);
0129 
0130     r600_set_sstu(rdev, R600_SSTU_DFLT);
0131     r600_set_sst(rdev, R600_SST_DFLT);
0132 
0133     r600_set_fctu(rdev, R600_FCTU_DFLT);
0134     r600_set_fct(rdev, R600_FCT_DFLT);
0135 
0136     r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT);
0137     r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT);
0138     r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT);
0139     r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT);
0140     r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT);
0141 
0142     r600_vid_rt_set_vru(rdev, R600_VRU_DFLT);
0143     r600_vid_rt_set_vrt(rdev, R600_VOLTAGERESPONSETIME_DFLT);
0144     r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT);
0145 
0146     ret = rs780_initialize_dpm_power_state(rdev, boot_ps);
0147 
0148     r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW,     0);
0149     r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM,  0);
0150     r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH,    0);
0151 
0152     r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW,    0);
0153     r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
0154     r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH,   0);
0155 
0156     r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW,    0);
0157     r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
0158     r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH,   0);
0159 
0160     r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW,    R600_DISPLAY_WATERMARK_HIGH);
0161     r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM, R600_DISPLAY_WATERMARK_HIGH);
0162     r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH,   R600_DISPLAY_WATERMARK_HIGH);
0163 
0164     r600_power_level_enable(rdev, R600_POWER_LEVEL_CTXSW, false);
0165     r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
0166     r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
0167     r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
0168 
0169     r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_LOW);
0170 
0171     r600_set_vrc(rdev, RS780_CGFTV_DFLT);
0172 
0173     return ret;
0174 }
0175 
0176 static void rs780_start_dpm(struct radeon_device *rdev)
0177 {
0178     r600_enable_sclk_control(rdev, false);
0179     r600_enable_mclk_control(rdev, false);
0180 
0181     r600_dynamicpm_enable(rdev, true);
0182 
0183     radeon_wait_for_vblank(rdev, 0);
0184     radeon_wait_for_vblank(rdev, 1);
0185 
0186     r600_enable_spll_bypass(rdev, true);
0187     r600_wait_for_spll_change(rdev);
0188     r600_enable_spll_bypass(rdev, false);
0189     r600_wait_for_spll_change(rdev);
0190 
0191     r600_enable_spll_bypass(rdev, true);
0192     r600_wait_for_spll_change(rdev);
0193     r600_enable_spll_bypass(rdev, false);
0194     r600_wait_for_spll_change(rdev);
0195 
0196     r600_enable_sclk_control(rdev, true);
0197 }
0198 
0199 
0200 static void rs780_preset_ranges_slow_clk_fbdiv_en(struct radeon_device *rdev)
0201 {
0202     WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN,
0203          ~RANGE_SLOW_CLK_FEEDBACK_DIV_EN);
0204 
0205     WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1,
0206          RANGE0_SLOW_CLK_FEEDBACK_DIV(RS780_SLOWCLKFEEDBACKDIV_DFLT),
0207          ~RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK);
0208 }
0209 
0210 static void rs780_preset_starting_fbdiv(struct radeon_device *rdev)
0211 {
0212     u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
0213 
0214     WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv),
0215          ~STARTING_FEEDBACK_DIV_MASK);
0216 
0217     WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv),
0218          ~FORCED_FEEDBACK_DIV_MASK);
0219 
0220     WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
0221 }
0222 
0223 static void rs780_voltage_scaling_init(struct radeon_device *rdev)
0224 {
0225     struct igp_power_info *pi = rs780_get_pi(rdev);
0226     u32 fv_throt_pwm_fb_div_range[3];
0227     u32 fv_throt_pwm_range[4];
0228 
0229     if (rdev->pdev->device == 0x9614) {
0230         fv_throt_pwm_fb_div_range[0] = RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
0231         fv_throt_pwm_fb_div_range[1] = RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
0232         fv_throt_pwm_fb_div_range[2] = RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
0233     } else if ((rdev->pdev->device == 0x9714) ||
0234            (rdev->pdev->device == 0x9715)) {
0235         fv_throt_pwm_fb_div_range[0] = RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
0236         fv_throt_pwm_fb_div_range[1] = RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
0237         fv_throt_pwm_fb_div_range[2] = RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
0238     } else {
0239         fv_throt_pwm_fb_div_range[0] = RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT;
0240         fv_throt_pwm_fb_div_range[1] = RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT;
0241         fv_throt_pwm_fb_div_range[2] = RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT;
0242     }
0243 
0244     if (pi->pwm_voltage_control) {
0245         fv_throt_pwm_range[0] = pi->min_voltage;
0246         fv_throt_pwm_range[1] = pi->min_voltage;
0247         fv_throt_pwm_range[2] = pi->max_voltage;
0248         fv_throt_pwm_range[3] = pi->max_voltage;
0249     } else {
0250         fv_throt_pwm_range[0] = pi->invert_pwm_required ?
0251             RS780_FVTHROTPWMRANGE3_GPIO_DFLT : RS780_FVTHROTPWMRANGE0_GPIO_DFLT;
0252         fv_throt_pwm_range[1] = pi->invert_pwm_required ?
0253             RS780_FVTHROTPWMRANGE2_GPIO_DFLT : RS780_FVTHROTPWMRANGE1_GPIO_DFLT;
0254         fv_throt_pwm_range[2] = pi->invert_pwm_required ?
0255             RS780_FVTHROTPWMRANGE1_GPIO_DFLT : RS780_FVTHROTPWMRANGE2_GPIO_DFLT;
0256         fv_throt_pwm_range[3] = pi->invert_pwm_required ?
0257             RS780_FVTHROTPWMRANGE0_GPIO_DFLT : RS780_FVTHROTPWMRANGE3_GPIO_DFLT;
0258     }
0259 
0260     WREG32_P(FVTHROT_PWM_CTRL_REG0,
0261          STARTING_PWM_HIGHTIME(pi->max_voltage),
0262          ~STARTING_PWM_HIGHTIME_MASK);
0263 
0264     WREG32_P(FVTHROT_PWM_CTRL_REG0,
0265          NUMBER_OF_CYCLES_IN_PERIOD(pi->num_of_cycles_in_period),
0266          ~NUMBER_OF_CYCLES_IN_PERIOD_MASK);
0267 
0268     WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME,
0269          ~FORCE_STARTING_PWM_HIGHTIME);
0270 
0271     if (pi->invert_pwm_required)
0272         WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM);
0273     else
0274         WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~INVERT_PWM_WAVEFORM);
0275 
0276     rs780_voltage_scaling_enable(rdev, true);
0277 
0278     WREG32(FVTHROT_PWM_CTRL_REG1,
0279            (MIN_PWM_HIGHTIME(pi->min_voltage) |
0280         MAX_PWM_HIGHTIME(pi->max_voltage)));
0281 
0282     WREG32(FVTHROT_PWM_US_REG0, RS780_FVTHROTPWMUSREG0_DFLT);
0283     WREG32(FVTHROT_PWM_US_REG1, RS780_FVTHROTPWMUSREG1_DFLT);
0284     WREG32(FVTHROT_PWM_DS_REG0, RS780_FVTHROTPWMDSREG0_DFLT);
0285     WREG32(FVTHROT_PWM_DS_REG1, RS780_FVTHROTPWMDSREG1_DFLT);
0286 
0287     WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
0288          RANGE0_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[0]),
0289          ~RANGE0_PWM_FEEDBACK_DIV_MASK);
0290 
0291     WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG2,
0292            (RANGE1_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[1]) |
0293         RANGE2_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[2])));
0294 
0295     WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG3,
0296            (RANGE0_PWM(fv_throt_pwm_range[1]) |
0297         RANGE1_PWM(fv_throt_pwm_range[2])));
0298     WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG4,
0299            (RANGE2_PWM(fv_throt_pwm_range[1]) |
0300         RANGE3_PWM(fv_throt_pwm_range[2])));
0301 }
0302 
0303 static void rs780_clk_scaling_enable(struct radeon_device *rdev, bool enable)
0304 {
0305     if (enable)
0306         WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT | ENABLE_FV_UPDATE,
0307              ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE));
0308     else
0309         WREG32_P(FVTHROT_CNTRL_REG, 0,
0310              ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE));
0311 }
0312 
0313 static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable)
0314 {
0315     if (enable)
0316         WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT_IO, ~ENABLE_FV_THROT_IO);
0317     else
0318         WREG32_P(FVTHROT_CNTRL_REG, 0, ~ENABLE_FV_THROT_IO);
0319 }
0320 
0321 static void rs780_set_engine_clock_wfc(struct radeon_device *rdev)
0322 {
0323     WREG32(FVTHROT_UTC0, RS780_FVTHROTUTC0_DFLT);
0324     WREG32(FVTHROT_UTC1, RS780_FVTHROTUTC1_DFLT);
0325     WREG32(FVTHROT_UTC2, RS780_FVTHROTUTC2_DFLT);
0326     WREG32(FVTHROT_UTC3, RS780_FVTHROTUTC3_DFLT);
0327     WREG32(FVTHROT_UTC4, RS780_FVTHROTUTC4_DFLT);
0328 
0329     WREG32(FVTHROT_DTC0, RS780_FVTHROTDTC0_DFLT);
0330     WREG32(FVTHROT_DTC1, RS780_FVTHROTDTC1_DFLT);
0331     WREG32(FVTHROT_DTC2, RS780_FVTHROTDTC2_DFLT);
0332     WREG32(FVTHROT_DTC3, RS780_FVTHROTDTC3_DFLT);
0333     WREG32(FVTHROT_DTC4, RS780_FVTHROTDTC4_DFLT);
0334 }
0335 
0336 static void rs780_set_engine_clock_sc(struct radeon_device *rdev)
0337 {
0338     WREG32_P(FVTHROT_FBDIV_REG2,
0339          FB_DIV_TIMER_VAL(RS780_FBDIVTIMERVAL_DFLT),
0340          ~FB_DIV_TIMER_VAL_MASK);
0341 
0342     WREG32_P(FVTHROT_CNTRL_REG,
0343          REFRESH_RATE_DIVISOR(0) | MINIMUM_CIP(0xf),
0344          ~(REFRESH_RATE_DIVISOR_MASK | MINIMUM_CIP_MASK));
0345 }
0346 
0347 static void rs780_set_engine_clock_tdc(struct radeon_device *rdev)
0348 {
0349     WREG32_P(FVTHROT_CNTRL_REG, 0, ~(FORCE_TREND_SEL | TREND_SEL_MODE));
0350 }
0351 
0352 static void rs780_set_engine_clock_ssc(struct radeon_device *rdev)
0353 {
0354     WREG32(FVTHROT_FB_US_REG0, RS780_FVTHROTFBUSREG0_DFLT);
0355     WREG32(FVTHROT_FB_US_REG1, RS780_FVTHROTFBUSREG1_DFLT);
0356     WREG32(FVTHROT_FB_DS_REG0, RS780_FVTHROTFBDSREG0_DFLT);
0357     WREG32(FVTHROT_FB_DS_REG1, RS780_FVTHROTFBDSREG1_DFLT);
0358 
0359     WREG32_P(FVTHROT_FBDIV_REG1, MAX_FEEDBACK_STEP(1), ~MAX_FEEDBACK_STEP_MASK);
0360 }
0361 
0362 static void rs780_program_at(struct radeon_device *rdev)
0363 {
0364     struct igp_power_info *pi = rs780_get_pi(rdev);
0365 
0366     WREG32(FVTHROT_TARGET_REG, 30000000 / pi->refresh_rate);
0367     WREG32(FVTHROT_CB1, 1000000 * 5 / pi->refresh_rate);
0368     WREG32(FVTHROT_CB2, 1000000 * 10 / pi->refresh_rate);
0369     WREG32(FVTHROT_CB3, 1000000 * 30 / pi->refresh_rate);
0370     WREG32(FVTHROT_CB4, 1000000 * 50 / pi->refresh_rate);
0371 }
0372 
0373 static void rs780_disable_vbios_powersaving(struct radeon_device *rdev)
0374 {
0375     WREG32_P(CG_INTGFX_MISC, 0, ~0xFFF00000);
0376 }
0377 
0378 static void rs780_force_voltage(struct radeon_device *rdev, u16 voltage)
0379 {
0380     struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
0381 
0382     if ((current_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
0383         (current_state->min_voltage == RS780_VDDC_LEVEL_HIGH))
0384         return;
0385 
0386     WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
0387 
0388     udelay(1);
0389 
0390     WREG32_P(FVTHROT_PWM_CTRL_REG0,
0391          STARTING_PWM_HIGHTIME(voltage),
0392          ~STARTING_PWM_HIGHTIME_MASK);
0393 
0394     WREG32_P(FVTHROT_PWM_CTRL_REG0,
0395          FORCE_STARTING_PWM_HIGHTIME, ~FORCE_STARTING_PWM_HIGHTIME);
0396 
0397     WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 0,
0398         ~RANGE_PWM_FEEDBACK_DIV_EN);
0399 
0400     udelay(1);
0401 
0402     WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
0403 }
0404 
0405 static void rs780_force_fbdiv(struct radeon_device *rdev, u32 fb_div)
0406 {
0407     struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
0408 
0409     if (current_state->sclk_low == current_state->sclk_high)
0410         return;
0411 
0412     WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
0413 
0414     WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fb_div),
0415          ~FORCED_FEEDBACK_DIV_MASK);
0416     WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fb_div),
0417          ~STARTING_FEEDBACK_DIV_MASK);
0418     WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
0419 
0420     udelay(100);
0421 
0422     WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
0423 }
0424 
0425 static int rs780_set_engine_clock_scaling(struct radeon_device *rdev,
0426                       struct radeon_ps *new_ps,
0427                       struct radeon_ps *old_ps)
0428 {
0429     struct atom_clock_dividers min_dividers, max_dividers, current_max_dividers;
0430     struct igp_ps *new_state = rs780_get_ps(new_ps);
0431     struct igp_ps *old_state = rs780_get_ps(old_ps);
0432     int ret;
0433 
0434     if ((new_state->sclk_high == old_state->sclk_high) &&
0435         (new_state->sclk_low == old_state->sclk_low))
0436         return 0;
0437 
0438     ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
0439                          new_state->sclk_low, false, &min_dividers);
0440     if (ret)
0441         return ret;
0442 
0443     ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
0444                          new_state->sclk_high, false, &max_dividers);
0445     if (ret)
0446         return ret;
0447 
0448     ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
0449                          old_state->sclk_high, false, &current_max_dividers);
0450     if (ret)
0451         return ret;
0452 
0453     if ((min_dividers.ref_div != max_dividers.ref_div) ||
0454         (min_dividers.post_div != max_dividers.post_div) ||
0455         (max_dividers.ref_div != current_max_dividers.ref_div) ||
0456         (max_dividers.post_div != current_max_dividers.post_div))
0457         return -EINVAL;
0458 
0459     rs780_force_fbdiv(rdev, max_dividers.fb_div);
0460 
0461     if (max_dividers.fb_div > min_dividers.fb_div) {
0462         WREG32_P(FVTHROT_FBDIV_REG0,
0463              MIN_FEEDBACK_DIV(min_dividers.fb_div) |
0464              MAX_FEEDBACK_DIV(max_dividers.fb_div),
0465              ~(MIN_FEEDBACK_DIV_MASK | MAX_FEEDBACK_DIV_MASK));
0466 
0467         WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
0468     }
0469 
0470     return 0;
0471 }
0472 
0473 static void rs780_set_engine_clock_spc(struct radeon_device *rdev,
0474                        struct radeon_ps *new_ps,
0475                        struct radeon_ps *old_ps)
0476 {
0477     struct igp_ps *new_state = rs780_get_ps(new_ps);
0478     struct igp_ps *old_state = rs780_get_ps(old_ps);
0479     struct igp_power_info *pi = rs780_get_pi(rdev);
0480 
0481     if ((new_state->sclk_high == old_state->sclk_high) &&
0482         (new_state->sclk_low == old_state->sclk_low))
0483         return;
0484 
0485     if (pi->crtc_id == 0)
0486         WREG32_P(CG_INTGFX_MISC, 0, ~FVTHROT_VBLANK_SEL);
0487     else
0488         WREG32_P(CG_INTGFX_MISC, FVTHROT_VBLANK_SEL, ~FVTHROT_VBLANK_SEL);
0489 
0490 }
0491 
0492 static void rs780_activate_engine_clk_scaling(struct radeon_device *rdev,
0493                           struct radeon_ps *new_ps,
0494                           struct radeon_ps *old_ps)
0495 {
0496     struct igp_ps *new_state = rs780_get_ps(new_ps);
0497     struct igp_ps *old_state = rs780_get_ps(old_ps);
0498 
0499     if ((new_state->sclk_high == old_state->sclk_high) &&
0500         (new_state->sclk_low == old_state->sclk_low))
0501         return;
0502 
0503     if (new_state->sclk_high == new_state->sclk_low)
0504         return;
0505 
0506     rs780_clk_scaling_enable(rdev, true);
0507 }
0508 
0509 static u32 rs780_get_voltage_for_vddc_level(struct radeon_device *rdev,
0510                         enum rs780_vddc_level vddc)
0511 {
0512     struct igp_power_info *pi = rs780_get_pi(rdev);
0513 
0514     if (vddc == RS780_VDDC_LEVEL_HIGH)
0515         return pi->max_voltage;
0516     else if (vddc == RS780_VDDC_LEVEL_LOW)
0517         return pi->min_voltage;
0518     else
0519         return pi->max_voltage;
0520 }
0521 
0522 static void rs780_enable_voltage_scaling(struct radeon_device *rdev,
0523                      struct radeon_ps *new_ps)
0524 {
0525     struct igp_ps *new_state = rs780_get_ps(new_ps);
0526     struct igp_power_info *pi = rs780_get_pi(rdev);
0527     enum rs780_vddc_level vddc_high, vddc_low;
0528 
0529     udelay(100);
0530 
0531     if ((new_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
0532         (new_state->min_voltage == RS780_VDDC_LEVEL_HIGH))
0533         return;
0534 
0535     vddc_high = rs780_get_voltage_for_vddc_level(rdev,
0536                              new_state->max_voltage);
0537     vddc_low = rs780_get_voltage_for_vddc_level(rdev,
0538                             new_state->min_voltage);
0539 
0540     WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
0541 
0542     udelay(1);
0543     if (vddc_high > vddc_low) {
0544         WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
0545              RANGE_PWM_FEEDBACK_DIV_EN, ~RANGE_PWM_FEEDBACK_DIV_EN);
0546 
0547         WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~FORCE_STARTING_PWM_HIGHTIME);
0548     } else if (vddc_high == vddc_low) {
0549         if (pi->max_voltage != vddc_high) {
0550             WREG32_P(FVTHROT_PWM_CTRL_REG0,
0551                  STARTING_PWM_HIGHTIME(vddc_high),
0552                  ~STARTING_PWM_HIGHTIME_MASK);
0553 
0554             WREG32_P(FVTHROT_PWM_CTRL_REG0,
0555                  FORCE_STARTING_PWM_HIGHTIME,
0556                  ~FORCE_STARTING_PWM_HIGHTIME);
0557         }
0558     }
0559 
0560     WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
0561 }
0562 
0563 static void rs780_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
0564                              struct radeon_ps *new_ps,
0565                              struct radeon_ps *old_ps)
0566 {
0567     struct igp_ps *new_state = rs780_get_ps(new_ps);
0568     struct igp_ps *current_state = rs780_get_ps(old_ps);
0569 
0570     if ((new_ps->vclk == old_ps->vclk) &&
0571         (new_ps->dclk == old_ps->dclk))
0572         return;
0573 
0574     if (new_state->sclk_high >= current_state->sclk_high)
0575         return;
0576 
0577     radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
0578 }
0579 
0580 static void rs780_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
0581                             struct radeon_ps *new_ps,
0582                             struct radeon_ps *old_ps)
0583 {
0584     struct igp_ps *new_state = rs780_get_ps(new_ps);
0585     struct igp_ps *current_state = rs780_get_ps(old_ps);
0586 
0587     if ((new_ps->vclk == old_ps->vclk) &&
0588         (new_ps->dclk == old_ps->dclk))
0589         return;
0590 
0591     if (new_state->sclk_high < current_state->sclk_high)
0592         return;
0593 
0594     radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
0595 }
0596 
0597 int rs780_dpm_enable(struct radeon_device *rdev)
0598 {
0599     struct igp_power_info *pi = rs780_get_pi(rdev);
0600     struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
0601     int ret;
0602 
0603     rs780_get_pm_mode_parameters(rdev);
0604     rs780_disable_vbios_powersaving(rdev);
0605 
0606     if (r600_dynamicpm_enabled(rdev))
0607         return -EINVAL;
0608     ret = rs780_initialize_dpm_parameters(rdev, boot_ps);
0609     if (ret)
0610         return ret;
0611     rs780_start_dpm(rdev);
0612 
0613     rs780_preset_ranges_slow_clk_fbdiv_en(rdev);
0614     rs780_preset_starting_fbdiv(rdev);
0615     if (pi->voltage_control)
0616         rs780_voltage_scaling_init(rdev);
0617     rs780_clk_scaling_enable(rdev, true);
0618     rs780_set_engine_clock_sc(rdev);
0619     rs780_set_engine_clock_wfc(rdev);
0620     rs780_program_at(rdev);
0621     rs780_set_engine_clock_tdc(rdev);
0622     rs780_set_engine_clock_ssc(rdev);
0623 
0624     if (pi->gfx_clock_gating)
0625         r600_gfx_clockgating_enable(rdev, true);
0626 
0627     return 0;
0628 }
0629 
0630 void rs780_dpm_disable(struct radeon_device *rdev)
0631 {
0632     struct igp_power_info *pi = rs780_get_pi(rdev);
0633 
0634     r600_dynamicpm_enable(rdev, false);
0635 
0636     rs780_clk_scaling_enable(rdev, false);
0637     rs780_voltage_scaling_enable(rdev, false);
0638 
0639     if (pi->gfx_clock_gating)
0640         r600_gfx_clockgating_enable(rdev, false);
0641 
0642     if (rdev->irq.installed &&
0643         (rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) {
0644         rdev->irq.dpm_thermal = false;
0645         radeon_irq_set(rdev);
0646     }
0647 }
0648 
0649 int rs780_dpm_set_power_state(struct radeon_device *rdev)
0650 {
0651     struct igp_power_info *pi = rs780_get_pi(rdev);
0652     struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
0653     struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
0654     int ret;
0655 
0656     rs780_get_pm_mode_parameters(rdev);
0657 
0658     rs780_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
0659 
0660     if (pi->voltage_control) {
0661         rs780_force_voltage(rdev, pi->max_voltage);
0662         mdelay(5);
0663     }
0664 
0665     ret = rs780_set_engine_clock_scaling(rdev, new_ps, old_ps);
0666     if (ret)
0667         return ret;
0668     rs780_set_engine_clock_spc(rdev, new_ps, old_ps);
0669 
0670     rs780_activate_engine_clk_scaling(rdev, new_ps, old_ps);
0671 
0672     if (pi->voltage_control)
0673         rs780_enable_voltage_scaling(rdev, new_ps);
0674 
0675     rs780_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
0676 
0677     return 0;
0678 }
0679 
0680 void rs780_dpm_setup_asic(struct radeon_device *rdev)
0681 {
0682 
0683 }
0684 
0685 void rs780_dpm_display_configuration_changed(struct radeon_device *rdev)
0686 {
0687     rs780_get_pm_mode_parameters(rdev);
0688     rs780_program_at(rdev);
0689 }
0690 
0691 union igp_info {
0692     struct _ATOM_INTEGRATED_SYSTEM_INFO info;
0693     struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
0694 };
0695 
0696 union power_info {
0697     struct _ATOM_POWERPLAY_INFO info;
0698     struct _ATOM_POWERPLAY_INFO_V2 info_2;
0699     struct _ATOM_POWERPLAY_INFO_V3 info_3;
0700     struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
0701     struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
0702     struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
0703 };
0704 
0705 union pplib_clock_info {
0706     struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
0707     struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
0708     struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
0709     struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
0710 };
0711 
0712 union pplib_power_state {
0713     struct _ATOM_PPLIB_STATE v1;
0714     struct _ATOM_PPLIB_STATE_V2 v2;
0715 };
0716 
0717 static void rs780_parse_pplib_non_clock_info(struct radeon_device *rdev,
0718                          struct radeon_ps *rps,
0719                          struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
0720                          u8 table_rev)
0721 {
0722     rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
0723     rps->class = le16_to_cpu(non_clock_info->usClassification);
0724     rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
0725 
0726     if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
0727         rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
0728         rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
0729     } else {
0730         rps->vclk = 0;
0731         rps->dclk = 0;
0732     }
0733 
0734     if (r600_is_uvd_state(rps->class, rps->class2)) {
0735         if ((rps->vclk == 0) || (rps->dclk == 0)) {
0736             rps->vclk = RS780_DEFAULT_VCLK_FREQ;
0737             rps->dclk = RS780_DEFAULT_DCLK_FREQ;
0738         }
0739     }
0740 
0741     if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
0742         rdev->pm.dpm.boot_ps = rps;
0743     if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
0744         rdev->pm.dpm.uvd_ps = rps;
0745 }
0746 
0747 static void rs780_parse_pplib_clock_info(struct radeon_device *rdev,
0748                      struct radeon_ps *rps,
0749                      union pplib_clock_info *clock_info)
0750 {
0751     struct igp_ps *ps = rs780_get_ps(rps);
0752     u32 sclk;
0753 
0754     sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
0755     sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
0756     ps->sclk_low = sclk;
0757     sclk = le16_to_cpu(clock_info->rs780.usHighEngineClockLow);
0758     sclk |= clock_info->rs780.ucHighEngineClockHigh << 16;
0759     ps->sclk_high = sclk;
0760     switch (le16_to_cpu(clock_info->rs780.usVDDC)) {
0761     case ATOM_PPLIB_RS780_VOLTAGE_NONE:
0762     default:
0763         ps->min_voltage = RS780_VDDC_LEVEL_UNKNOWN;
0764         ps->max_voltage = RS780_VDDC_LEVEL_UNKNOWN;
0765         break;
0766     case ATOM_PPLIB_RS780_VOLTAGE_LOW:
0767         ps->min_voltage = RS780_VDDC_LEVEL_LOW;
0768         ps->max_voltage = RS780_VDDC_LEVEL_LOW;
0769         break;
0770     case ATOM_PPLIB_RS780_VOLTAGE_HIGH:
0771         ps->min_voltage = RS780_VDDC_LEVEL_HIGH;
0772         ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
0773         break;
0774     case ATOM_PPLIB_RS780_VOLTAGE_VARIABLE:
0775         ps->min_voltage = RS780_VDDC_LEVEL_LOW;
0776         ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
0777         break;
0778     }
0779     ps->flags = le32_to_cpu(clock_info->rs780.ulFlags);
0780 
0781     if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
0782         ps->sclk_low = rdev->clock.default_sclk;
0783         ps->sclk_high = rdev->clock.default_sclk;
0784         ps->min_voltage = RS780_VDDC_LEVEL_HIGH;
0785         ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
0786     }
0787 }
0788 
0789 static int rs780_parse_power_table(struct radeon_device *rdev)
0790 {
0791     struct radeon_mode_info *mode_info = &rdev->mode_info;
0792     struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
0793     union pplib_power_state *power_state;
0794     int i;
0795     union pplib_clock_info *clock_info;
0796     union power_info *power_info;
0797     int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
0798     u16 data_offset;
0799     u8 frev, crev;
0800     struct igp_ps *ps;
0801 
0802     if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
0803                    &frev, &crev, &data_offset))
0804         return -EINVAL;
0805     power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
0806 
0807     rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates,
0808                   sizeof(struct radeon_ps),
0809                   GFP_KERNEL);
0810     if (!rdev->pm.dpm.ps)
0811         return -ENOMEM;
0812 
0813     for (i = 0; i < power_info->pplib.ucNumStates; i++) {
0814         power_state = (union pplib_power_state *)
0815             (mode_info->atom_context->bios + data_offset +
0816              le16_to_cpu(power_info->pplib.usStateArrayOffset) +
0817              i * power_info->pplib.ucStateEntrySize);
0818         non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
0819             (mode_info->atom_context->bios + data_offset +
0820              le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
0821              (power_state->v1.ucNonClockStateIndex *
0822               power_info->pplib.ucNonClockSize));
0823         if (power_info->pplib.ucStateEntrySize - 1) {
0824             clock_info = (union pplib_clock_info *)
0825                 (mode_info->atom_context->bios + data_offset +
0826                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
0827                  (power_state->v1.ucClockStateIndices[0] *
0828                   power_info->pplib.ucClockInfoSize));
0829             ps = kzalloc(sizeof(struct igp_ps), GFP_KERNEL);
0830             if (ps == NULL) {
0831                 kfree(rdev->pm.dpm.ps);
0832                 return -ENOMEM;
0833             }
0834             rdev->pm.dpm.ps[i].ps_priv = ps;
0835             rs780_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
0836                              non_clock_info,
0837                              power_info->pplib.ucNonClockSize);
0838             rs780_parse_pplib_clock_info(rdev,
0839                              &rdev->pm.dpm.ps[i],
0840                              clock_info);
0841         }
0842     }
0843     rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
0844     return 0;
0845 }
0846 
0847 int rs780_dpm_init(struct radeon_device *rdev)
0848 {
0849     struct igp_power_info *pi;
0850     int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
0851     union igp_info *info;
0852     u16 data_offset;
0853     u8 frev, crev;
0854     int ret;
0855 
0856     pi = kzalloc(sizeof(struct igp_power_info), GFP_KERNEL);
0857     if (pi == NULL)
0858         return -ENOMEM;
0859     rdev->pm.dpm.priv = pi;
0860 
0861     ret = r600_get_platform_caps(rdev);
0862     if (ret)
0863         return ret;
0864 
0865     ret = rs780_parse_power_table(rdev);
0866     if (ret)
0867         return ret;
0868 
0869     pi->voltage_control = false;
0870     pi->gfx_clock_gating = true;
0871 
0872     if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
0873                    &frev, &crev, &data_offset)) {
0874         info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
0875 
0876         /* Get various system informations from bios */
0877         switch (crev) {
0878         case 1:
0879             pi->num_of_cycles_in_period =
0880                 info->info.ucNumberOfCyclesInPeriod;
0881             pi->num_of_cycles_in_period |=
0882                 info->info.ucNumberOfCyclesInPeriodHi << 8;
0883             pi->invert_pwm_required =
0884                 (pi->num_of_cycles_in_period & 0x8000) ? true : false;
0885             pi->boot_voltage = info->info.ucStartingPWM_HighTime;
0886             pi->max_voltage = info->info.ucMaxNBVoltage;
0887             pi->max_voltage |= info->info.ucMaxNBVoltageHigh << 8;
0888             pi->min_voltage = info->info.ucMinNBVoltage;
0889             pi->min_voltage |= info->info.ucMinNBVoltageHigh << 8;
0890             pi->inter_voltage_low =
0891                 le16_to_cpu(info->info.usInterNBVoltageLow);
0892             pi->inter_voltage_high =
0893                 le16_to_cpu(info->info.usInterNBVoltageHigh);
0894             pi->voltage_control = true;
0895             pi->bootup_uma_clk = info->info.usK8MemoryClock * 100;
0896             break;
0897         case 2:
0898             pi->num_of_cycles_in_period =
0899                 le16_to_cpu(info->info_2.usNumberOfCyclesInPeriod);
0900             pi->invert_pwm_required =
0901                 (pi->num_of_cycles_in_period & 0x8000) ? true : false;
0902             pi->boot_voltage =
0903                 le16_to_cpu(info->info_2.usBootUpNBVoltage);
0904             pi->max_voltage =
0905                 le16_to_cpu(info->info_2.usMaxNBVoltage);
0906             pi->min_voltage =
0907                 le16_to_cpu(info->info_2.usMinNBVoltage);
0908             pi->system_config =
0909                 le32_to_cpu(info->info_2.ulSystemConfig);
0910             pi->pwm_voltage_control =
0911                 (pi->system_config & 0x4) ? true : false;
0912             pi->voltage_control = true;
0913             pi->bootup_uma_clk = le32_to_cpu(info->info_2.ulBootUpUMAClock);
0914             break;
0915         default:
0916             DRM_ERROR("No integrated system info for your GPU\n");
0917             return -EINVAL;
0918         }
0919         if (pi->min_voltage > pi->max_voltage)
0920             pi->voltage_control = false;
0921         if (pi->pwm_voltage_control) {
0922             if ((pi->num_of_cycles_in_period == 0) ||
0923                 (pi->max_voltage == 0) ||
0924                 (pi->min_voltage == 0))
0925                 pi->voltage_control = false;
0926         } else {
0927             if ((pi->num_of_cycles_in_period == 0) ||
0928                 (pi->max_voltage == 0))
0929                 pi->voltage_control = false;
0930         }
0931 
0932         return 0;
0933     }
0934     radeon_dpm_fini(rdev);
0935     return -EINVAL;
0936 }
0937 
0938 void rs780_dpm_print_power_state(struct radeon_device *rdev,
0939                  struct radeon_ps *rps)
0940 {
0941     struct igp_ps *ps = rs780_get_ps(rps);
0942 
0943     r600_dpm_print_class_info(rps->class, rps->class2);
0944     r600_dpm_print_cap_info(rps->caps);
0945     printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
0946     printk("\t\tpower level 0    sclk: %u vddc_index: %d\n",
0947            ps->sclk_low, ps->min_voltage);
0948     printk("\t\tpower level 1    sclk: %u vddc_index: %d\n",
0949            ps->sclk_high, ps->max_voltage);
0950     r600_dpm_print_ps_status(rdev, rps);
0951 }
0952 
0953 void rs780_dpm_fini(struct radeon_device *rdev)
0954 {
0955     int i;
0956 
0957     for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
0958         kfree(rdev->pm.dpm.ps[i].ps_priv);
0959     }
0960     kfree(rdev->pm.dpm.ps);
0961     kfree(rdev->pm.dpm.priv);
0962 }
0963 
0964 u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low)
0965 {
0966     struct igp_ps *requested_state = rs780_get_ps(rdev->pm.dpm.requested_ps);
0967 
0968     if (low)
0969         return requested_state->sclk_low;
0970     else
0971         return requested_state->sclk_high;
0972 }
0973 
0974 u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low)
0975 {
0976     struct igp_power_info *pi = rs780_get_pi(rdev);
0977 
0978     return pi->bootup_uma_clk;
0979 }
0980 
0981 void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
0982                                struct seq_file *m)
0983 {
0984     struct radeon_ps *rps = rdev->pm.dpm.current_ps;
0985     struct igp_ps *ps = rs780_get_ps(rps);
0986     u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;
0987     u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
0988     u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1;
0989     u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 +
0990         ((func_cntl & SPLL_SW_LOLEN_MASK) >> SPLL_SW_LOLEN_SHIFT) + 1;
0991     u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /
0992         (post_div * ref_div);
0993 
0994     seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
0995 
0996     /* guess based on the current sclk */
0997     if (sclk < (ps->sclk_low + 500))
0998         seq_printf(m, "power level 0    sclk: %u vddc_index: %d\n",
0999                ps->sclk_low, ps->min_voltage);
1000     else
1001         seq_printf(m, "power level 1    sclk: %u vddc_index: %d\n",
1002                ps->sclk_high, ps->max_voltage);
1003 }
1004 
1005 /* get the current sclk in 10 khz units */
1006 u32 rs780_dpm_get_current_sclk(struct radeon_device *rdev)
1007 {
1008     u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;
1009     u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
1010     u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1;
1011     u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 +
1012         ((func_cntl & SPLL_SW_LOLEN_MASK) >> SPLL_SW_LOLEN_SHIFT) + 1;
1013     u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /
1014         (post_div * ref_div);
1015 
1016     return sclk;
1017 }
1018 
1019 /* get the current mclk in 10 khz units */
1020 u32 rs780_dpm_get_current_mclk(struct radeon_device *rdev)
1021 {
1022     struct igp_power_info *pi = rs780_get_pi(rdev);
1023 
1024     return pi->bootup_uma_clk;
1025 }
1026 
1027 int rs780_dpm_force_performance_level(struct radeon_device *rdev,
1028                       enum radeon_dpm_forced_level level)
1029 {
1030     struct igp_power_info *pi = rs780_get_pi(rdev);
1031     struct radeon_ps *rps = rdev->pm.dpm.current_ps;
1032     struct igp_ps *ps = rs780_get_ps(rps);
1033     struct atom_clock_dividers dividers;
1034     int ret;
1035 
1036     rs780_clk_scaling_enable(rdev, false);
1037     rs780_voltage_scaling_enable(rdev, false);
1038 
1039     if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1040         if (pi->voltage_control)
1041             rs780_force_voltage(rdev, pi->max_voltage);
1042 
1043         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1044                              ps->sclk_high, false, &dividers);
1045         if (ret)
1046             return ret;
1047 
1048         rs780_force_fbdiv(rdev, dividers.fb_div);
1049     } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1050         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1051                              ps->sclk_low, false, &dividers);
1052         if (ret)
1053             return ret;
1054 
1055         rs780_force_fbdiv(rdev, dividers.fb_div);
1056 
1057         if (pi->voltage_control)
1058             rs780_force_voltage(rdev, pi->min_voltage);
1059     } else {
1060         if (pi->voltage_control)
1061             rs780_force_voltage(rdev, pi->max_voltage);
1062 
1063         if (ps->sclk_high != ps->sclk_low) {
1064             WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
1065             rs780_clk_scaling_enable(rdev, true);
1066         }
1067 
1068         if (pi->voltage_control) {
1069             rs780_voltage_scaling_enable(rdev, true);
1070             rs780_enable_voltage_scaling(rdev, rps);
1071         }
1072     }
1073 
1074     rdev->pm.dpm.forced_level = level;
1075 
1076     return 0;
1077 }
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