Back to home page

OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  * Copyright 2009 Jerome Glisse.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors: Dave Airlie
0025  *          Alex Deucher
0026  *          Jerome Glisse
0027  */
0028 
0029 #include <linux/pci.h>
0030 
0031 #include "atom.h"
0032 #include "radeon.h"
0033 #include "radeon_asic.h"
0034 #include "radeon_audio.h"
0035 #include "rs690d.h"
0036 
0037 int rs690_mc_wait_for_idle(struct radeon_device *rdev)
0038 {
0039     unsigned i;
0040     uint32_t tmp;
0041 
0042     for (i = 0; i < rdev->usec_timeout; i++) {
0043         /* read MC_STATUS */
0044         tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
0045         if (G_000090_MC_SYSTEM_IDLE(tmp))
0046             return 0;
0047         udelay(1);
0048     }
0049     return -1;
0050 }
0051 
0052 static void rs690_gpu_init(struct radeon_device *rdev)
0053 {
0054     /* FIXME: is this correct ? */
0055     r420_pipes_init(rdev);
0056     if (rs690_mc_wait_for_idle(rdev)) {
0057         pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n");
0058     }
0059 }
0060 
0061 union igp_info {
0062     struct _ATOM_INTEGRATED_SYSTEM_INFO info;
0063     struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
0064 };
0065 
0066 void rs690_pm_info(struct radeon_device *rdev)
0067 {
0068     int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
0069     union igp_info *info;
0070     uint16_t data_offset;
0071     uint8_t frev, crev;
0072     fixed20_12 tmp;
0073 
0074     if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
0075                    &frev, &crev, &data_offset)) {
0076         info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
0077 
0078         /* Get various system informations from bios */
0079         switch (crev) {
0080         case 1:
0081             tmp.full = dfixed_const(100);
0082             rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock));
0083             rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
0084             if (le16_to_cpu(info->info.usK8MemoryClock))
0085                 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
0086             else if (rdev->clock.default_mclk) {
0087                 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
0088                 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
0089             } else
0090                 rdev->pm.igp_system_mclk.full = dfixed_const(400);
0091             rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
0092             rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
0093             break;
0094         case 2:
0095             tmp.full = dfixed_const(100);
0096             rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock));
0097             rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
0098             if (le32_to_cpu(info->info_v2.ulBootUpUMAClock))
0099                 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock));
0100             else if (rdev->clock.default_mclk)
0101                 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
0102             else
0103                 rdev->pm.igp_system_mclk.full = dfixed_const(66700);
0104             rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
0105             rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq));
0106             rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
0107             rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
0108             break;
0109         default:
0110             /* We assume the slower possible clock ie worst case */
0111             rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
0112             rdev->pm.igp_system_mclk.full = dfixed_const(200);
0113             rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
0114             rdev->pm.igp_ht_link_width.full = dfixed_const(8);
0115             DRM_ERROR("No integrated system info for your GPU, using safe default\n");
0116             break;
0117         }
0118     } else {
0119         /* We assume the slower possible clock ie worst case */
0120         rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
0121         rdev->pm.igp_system_mclk.full = dfixed_const(200);
0122         rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
0123         rdev->pm.igp_ht_link_width.full = dfixed_const(8);
0124         DRM_ERROR("No integrated system info for your GPU, using safe default\n");
0125     }
0126     /* Compute various bandwidth */
0127     /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4  */
0128     tmp.full = dfixed_const(4);
0129     rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
0130     /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
0131      *              = ht_clk * ht_width / 5
0132      */
0133     tmp.full = dfixed_const(5);
0134     rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
0135                         rdev->pm.igp_ht_link_width);
0136     rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
0137     if (tmp.full < rdev->pm.max_bandwidth.full) {
0138         /* HT link is a limiting factor */
0139         rdev->pm.max_bandwidth.full = tmp.full;
0140     }
0141     /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
0142      *                    = (sideport_clk * 14) / 10
0143      */
0144     tmp.full = dfixed_const(14);
0145     rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
0146     tmp.full = dfixed_const(10);
0147     rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
0148 }
0149 
0150 static void rs690_mc_init(struct radeon_device *rdev)
0151 {
0152     u64 base;
0153     uint32_t h_addr, l_addr;
0154     unsigned long long k8_addr;
0155 
0156     rs400_gart_adjust_size(rdev);
0157     rdev->mc.vram_is_ddr = true;
0158     rdev->mc.vram_width = 128;
0159     rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
0160     rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
0161     rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
0162     rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
0163     rdev->mc.visible_vram_size = rdev->mc.aper_size;
0164     base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
0165     base = G_000100_MC_FB_START(base) << 16;
0166     rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
0167     /* Some boards seem to be configured for 128MB of sideport memory,
0168      * but really only have 64MB.  Just skip the sideport and use
0169      * UMA memory.
0170      */
0171     if (rdev->mc.igp_sideport_enabled &&
0172         (rdev->mc.real_vram_size == (384 * 1024 * 1024))) {
0173         base += 128 * 1024 * 1024;
0174         rdev->mc.real_vram_size -= 128 * 1024 * 1024;
0175         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
0176     }
0177 
0178     /* Use K8 direct mapping for fast fb access. */ 
0179     rdev->fastfb_working = false;
0180     h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL));
0181     l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION);
0182     k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
0183 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
0184     if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)  
0185 #endif
0186     {
0187         /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport 
0188          * memory is present.
0189          */
0190         if (!rdev->mc.igp_sideport_enabled && radeon_fastfb == 1) {
0191             DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", 
0192                     (unsigned long long)rdev->mc.aper_base, k8_addr);
0193             rdev->mc.aper_base = (resource_size_t)k8_addr;
0194             rdev->fastfb_working = true;
0195         }
0196     }  
0197 
0198     rs690_pm_info(rdev);
0199     radeon_vram_location(rdev, &rdev->mc, base);
0200     rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
0201     radeon_gtt_location(rdev, &rdev->mc);
0202     radeon_update_bandwidth_info(rdev);
0203 }
0204 
0205 void rs690_line_buffer_adjust(struct radeon_device *rdev,
0206                   struct drm_display_mode *mode1,
0207                   struct drm_display_mode *mode2)
0208 {
0209     u32 tmp;
0210 
0211     /* Guess line buffer size to be 8192 pixels */
0212     u32 lb_size = 8192;
0213 
0214     /*
0215      * Line Buffer Setup
0216      * There is a single line buffer shared by both display controllers.
0217      * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
0218      * the display controllers.  The paritioning can either be done
0219      * manually or via one of four preset allocations specified in bits 1:0:
0220      *  0 - line buffer is divided in half and shared between crtc
0221      *  1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
0222      *  2 - D1 gets the whole buffer
0223      *  3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
0224      * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
0225      * allocation mode. In manual allocation mode, D1 always starts at 0,
0226      * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
0227      */
0228     tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
0229     tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
0230     /* auto */
0231     if (mode1 && mode2) {
0232         if (mode1->hdisplay > mode2->hdisplay) {
0233             if (mode1->hdisplay > 2560)
0234                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
0235             else
0236                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
0237         } else if (mode2->hdisplay > mode1->hdisplay) {
0238             if (mode2->hdisplay > 2560)
0239                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
0240             else
0241                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
0242         } else
0243             tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
0244     } else if (mode1) {
0245         tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
0246     } else if (mode2) {
0247         tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
0248     }
0249     WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
0250 
0251     /* Save number of lines the linebuffer leads before the scanout */
0252     if (mode1)
0253         rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
0254 
0255     if (mode2)
0256         rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
0257 }
0258 
0259 struct rs690_watermark {
0260     u32        lb_request_fifo_depth;
0261     fixed20_12 num_line_pair;
0262     fixed20_12 estimated_width;
0263     fixed20_12 worst_case_latency;
0264     fixed20_12 consumption_rate;
0265     fixed20_12 active_time;
0266     fixed20_12 dbpp;
0267     fixed20_12 priority_mark_max;
0268     fixed20_12 priority_mark;
0269     fixed20_12 sclk;
0270 };
0271 
0272 static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
0273                      struct radeon_crtc *crtc,
0274                      struct rs690_watermark *wm,
0275                      bool low)
0276 {
0277     struct drm_display_mode *mode = &crtc->base.mode;
0278     fixed20_12 a, b, c;
0279     fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
0280     fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
0281     fixed20_12 sclk, core_bandwidth, max_bandwidth;
0282     u32 selected_sclk;
0283 
0284     if (!crtc->base.enabled) {
0285         /* FIXME: wouldn't it better to set priority mark to maximum */
0286         wm->lb_request_fifo_depth = 4;
0287         return;
0288     }
0289 
0290     if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) &&
0291         (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
0292         selected_sclk = radeon_dpm_get_sclk(rdev, low);
0293     else
0294         selected_sclk = rdev->pm.current_sclk;
0295 
0296     /* sclk in Mhz */
0297     a.full = dfixed_const(100);
0298     sclk.full = dfixed_const(selected_sclk);
0299     sclk.full = dfixed_div(sclk, a);
0300 
0301     /* core_bandwidth = sclk(Mhz) * 16 */
0302     a.full = dfixed_const(16);
0303     core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
0304 
0305     if (crtc->vsc.full > dfixed_const(2))
0306         wm->num_line_pair.full = dfixed_const(2);
0307     else
0308         wm->num_line_pair.full = dfixed_const(1);
0309 
0310     b.full = dfixed_const(mode->crtc_hdisplay);
0311     c.full = dfixed_const(256);
0312     a.full = dfixed_div(b, c);
0313     request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
0314     request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
0315     if (a.full < dfixed_const(4)) {
0316         wm->lb_request_fifo_depth = 4;
0317     } else {
0318         wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
0319     }
0320 
0321     /* Determine consumption rate
0322      *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
0323      *  vtaps = number of vertical taps,
0324      *  vsc = vertical scaling ratio, defined as source/destination
0325      *  hsc = horizontal scaling ration, defined as source/destination
0326      */
0327     a.full = dfixed_const(mode->clock);
0328     b.full = dfixed_const(1000);
0329     a.full = dfixed_div(a, b);
0330     pclk.full = dfixed_div(b, a);
0331     if (crtc->rmx_type != RMX_OFF) {
0332         b.full = dfixed_const(2);
0333         if (crtc->vsc.full > b.full)
0334             b.full = crtc->vsc.full;
0335         b.full = dfixed_mul(b, crtc->hsc);
0336         c.full = dfixed_const(2);
0337         b.full = dfixed_div(b, c);
0338         consumption_time.full = dfixed_div(pclk, b);
0339     } else {
0340         consumption_time.full = pclk.full;
0341     }
0342     a.full = dfixed_const(1);
0343     wm->consumption_rate.full = dfixed_div(a, consumption_time);
0344 
0345 
0346     /* Determine line time
0347      *  LineTime = total time for one line of displayhtotal
0348      *  LineTime = total number of horizontal pixels
0349      *  pclk = pixel clock period(ns)
0350      */
0351     a.full = dfixed_const(crtc->base.mode.crtc_htotal);
0352     line_time.full = dfixed_mul(a, pclk);
0353 
0354     /* Determine active time
0355      *  ActiveTime = time of active region of display within one line,
0356      *  hactive = total number of horizontal active pixels
0357      *  htotal = total number of horizontal pixels
0358      */
0359     a.full = dfixed_const(crtc->base.mode.crtc_htotal);
0360     b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
0361     wm->active_time.full = dfixed_mul(line_time, b);
0362     wm->active_time.full = dfixed_div(wm->active_time, a);
0363 
0364     /* Maximun bandwidth is the minimun bandwidth of all component */
0365     max_bandwidth = core_bandwidth;
0366     if (rdev->mc.igp_sideport_enabled) {
0367         if (max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
0368             rdev->pm.sideport_bandwidth.full)
0369             max_bandwidth = rdev->pm.sideport_bandwidth;
0370         read_delay_latency.full = dfixed_const(370 * 800);
0371         a.full = dfixed_const(1000);
0372         b.full = dfixed_div(rdev->pm.igp_sideport_mclk, a);
0373         read_delay_latency.full = dfixed_div(read_delay_latency, b);
0374         read_delay_latency.full = dfixed_mul(read_delay_latency, a);
0375     } else {
0376         if (max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
0377             rdev->pm.k8_bandwidth.full)
0378             max_bandwidth = rdev->pm.k8_bandwidth;
0379         if (max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
0380             rdev->pm.ht_bandwidth.full)
0381             max_bandwidth = rdev->pm.ht_bandwidth;
0382         read_delay_latency.full = dfixed_const(5000);
0383     }
0384 
0385     /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
0386     a.full = dfixed_const(16);
0387     sclk.full = dfixed_mul(max_bandwidth, a);
0388     a.full = dfixed_const(1000);
0389     sclk.full = dfixed_div(a, sclk);
0390     /* Determine chunk time
0391      * ChunkTime = the time it takes the DCP to send one chunk of data
0392      * to the LB which consists of pipeline delay and inter chunk gap
0393      * sclk = system clock(ns)
0394      */
0395     a.full = dfixed_const(256 * 13);
0396     chunk_time.full = dfixed_mul(sclk, a);
0397     a.full = dfixed_const(10);
0398     chunk_time.full = dfixed_div(chunk_time, a);
0399 
0400     /* Determine the worst case latency
0401      * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
0402      * WorstCaseLatency = worst case time from urgent to when the MC starts
0403      *                    to return data
0404      * READ_DELAY_IDLE_MAX = constant of 1us
0405      * ChunkTime = time it takes the DCP to send one chunk of data to the LB
0406      *             which consists of pipeline delay and inter chunk gap
0407      */
0408     if (dfixed_trunc(wm->num_line_pair) > 1) {
0409         a.full = dfixed_const(3);
0410         wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
0411         wm->worst_case_latency.full += read_delay_latency.full;
0412     } else {
0413         a.full = dfixed_const(2);
0414         wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
0415         wm->worst_case_latency.full += read_delay_latency.full;
0416     }
0417 
0418     /* Determine the tolerable latency
0419      * TolerableLatency = Any given request has only 1 line time
0420      *                    for the data to be returned
0421      * LBRequestFifoDepth = Number of chunk requests the LB can
0422      *                      put into the request FIFO for a display
0423      *  LineTime = total time for one line of display
0424      *  ChunkTime = the time it takes the DCP to send one chunk
0425      *              of data to the LB which consists of
0426      *  pipeline delay and inter chunk gap
0427      */
0428     if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
0429         tolerable_latency.full = line_time.full;
0430     } else {
0431         tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
0432         tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
0433         tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
0434         tolerable_latency.full = line_time.full - tolerable_latency.full;
0435     }
0436     /* We assume worst case 32bits (4 bytes) */
0437     wm->dbpp.full = dfixed_const(4 * 8);
0438 
0439     /* Determine the maximum priority mark
0440      *  width = viewport width in pixels
0441      */
0442     a.full = dfixed_const(16);
0443     wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
0444     wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
0445     wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
0446 
0447     /* Determine estimated width */
0448     estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
0449     estimated_width.full = dfixed_div(estimated_width, consumption_time);
0450     if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
0451         wm->priority_mark.full = dfixed_const(10);
0452     } else {
0453         a.full = dfixed_const(16);
0454         wm->priority_mark.full = dfixed_div(estimated_width, a);
0455         wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
0456         wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
0457     }
0458 }
0459 
0460 static void rs690_compute_mode_priority(struct radeon_device *rdev,
0461                     struct rs690_watermark *wm0,
0462                     struct rs690_watermark *wm1,
0463                     struct drm_display_mode *mode0,
0464                     struct drm_display_mode *mode1,
0465                     u32 *d1mode_priority_a_cnt,
0466                     u32 *d2mode_priority_a_cnt)
0467 {
0468     fixed20_12 priority_mark02, priority_mark12, fill_rate;
0469     fixed20_12 a, b;
0470 
0471     *d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
0472     *d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
0473 
0474     if (mode0 && mode1) {
0475         if (dfixed_trunc(wm0->dbpp) > 64)
0476             a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair);
0477         else
0478             a.full = wm0->num_line_pair.full;
0479         if (dfixed_trunc(wm1->dbpp) > 64)
0480             b.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair);
0481         else
0482             b.full = wm1->num_line_pair.full;
0483         a.full += b.full;
0484         fill_rate.full = dfixed_div(wm0->sclk, a);
0485         if (wm0->consumption_rate.full > fill_rate.full) {
0486             b.full = wm0->consumption_rate.full - fill_rate.full;
0487             b.full = dfixed_mul(b, wm0->active_time);
0488             a.full = dfixed_mul(wm0->worst_case_latency,
0489                         wm0->consumption_rate);
0490             a.full = a.full + b.full;
0491             b.full = dfixed_const(16 * 1000);
0492             priority_mark02.full = dfixed_div(a, b);
0493         } else {
0494             a.full = dfixed_mul(wm0->worst_case_latency,
0495                         wm0->consumption_rate);
0496             b.full = dfixed_const(16 * 1000);
0497             priority_mark02.full = dfixed_div(a, b);
0498         }
0499         if (wm1->consumption_rate.full > fill_rate.full) {
0500             b.full = wm1->consumption_rate.full - fill_rate.full;
0501             b.full = dfixed_mul(b, wm1->active_time);
0502             a.full = dfixed_mul(wm1->worst_case_latency,
0503                         wm1->consumption_rate);
0504             a.full = a.full + b.full;
0505             b.full = dfixed_const(16 * 1000);
0506             priority_mark12.full = dfixed_div(a, b);
0507         } else {
0508             a.full = dfixed_mul(wm1->worst_case_latency,
0509                         wm1->consumption_rate);
0510             b.full = dfixed_const(16 * 1000);
0511             priority_mark12.full = dfixed_div(a, b);
0512         }
0513         if (wm0->priority_mark.full > priority_mark02.full)
0514             priority_mark02.full = wm0->priority_mark.full;
0515         if (wm0->priority_mark_max.full > priority_mark02.full)
0516             priority_mark02.full = wm0->priority_mark_max.full;
0517         if (wm1->priority_mark.full > priority_mark12.full)
0518             priority_mark12.full = wm1->priority_mark.full;
0519         if (wm1->priority_mark_max.full > priority_mark12.full)
0520             priority_mark12.full = wm1->priority_mark_max.full;
0521         *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
0522         *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
0523         if (rdev->disp_priority == 2) {
0524             *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
0525             *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
0526         }
0527     } else if (mode0) {
0528         if (dfixed_trunc(wm0->dbpp) > 64)
0529             a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair);
0530         else
0531             a.full = wm0->num_line_pair.full;
0532         fill_rate.full = dfixed_div(wm0->sclk, a);
0533         if (wm0->consumption_rate.full > fill_rate.full) {
0534             b.full = wm0->consumption_rate.full - fill_rate.full;
0535             b.full = dfixed_mul(b, wm0->active_time);
0536             a.full = dfixed_mul(wm0->worst_case_latency,
0537                         wm0->consumption_rate);
0538             a.full = a.full + b.full;
0539             b.full = dfixed_const(16 * 1000);
0540             priority_mark02.full = dfixed_div(a, b);
0541         } else {
0542             a.full = dfixed_mul(wm0->worst_case_latency,
0543                         wm0->consumption_rate);
0544             b.full = dfixed_const(16 * 1000);
0545             priority_mark02.full = dfixed_div(a, b);
0546         }
0547         if (wm0->priority_mark.full > priority_mark02.full)
0548             priority_mark02.full = wm0->priority_mark.full;
0549         if (wm0->priority_mark_max.full > priority_mark02.full)
0550             priority_mark02.full = wm0->priority_mark_max.full;
0551         *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
0552         if (rdev->disp_priority == 2)
0553             *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
0554     } else if (mode1) {
0555         if (dfixed_trunc(wm1->dbpp) > 64)
0556             a.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair);
0557         else
0558             a.full = wm1->num_line_pair.full;
0559         fill_rate.full = dfixed_div(wm1->sclk, a);
0560         if (wm1->consumption_rate.full > fill_rate.full) {
0561             b.full = wm1->consumption_rate.full - fill_rate.full;
0562             b.full = dfixed_mul(b, wm1->active_time);
0563             a.full = dfixed_mul(wm1->worst_case_latency,
0564                         wm1->consumption_rate);
0565             a.full = a.full + b.full;
0566             b.full = dfixed_const(16 * 1000);
0567             priority_mark12.full = dfixed_div(a, b);
0568         } else {
0569             a.full = dfixed_mul(wm1->worst_case_latency,
0570                         wm1->consumption_rate);
0571             b.full = dfixed_const(16 * 1000);
0572             priority_mark12.full = dfixed_div(a, b);
0573         }
0574         if (wm1->priority_mark.full > priority_mark12.full)
0575             priority_mark12.full = wm1->priority_mark.full;
0576         if (wm1->priority_mark_max.full > priority_mark12.full)
0577             priority_mark12.full = wm1->priority_mark_max.full;
0578         *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
0579         if (rdev->disp_priority == 2)
0580             *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
0581     }
0582 }
0583 
0584 void rs690_bandwidth_update(struct radeon_device *rdev)
0585 {
0586     struct drm_display_mode *mode0 = NULL;
0587     struct drm_display_mode *mode1 = NULL;
0588     struct rs690_watermark wm0_high, wm0_low;
0589     struct rs690_watermark wm1_high, wm1_low;
0590     u32 tmp;
0591     u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
0592     u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
0593 
0594     if (!rdev->mode_info.mode_config_initialized)
0595         return;
0596 
0597     radeon_update_display_priority(rdev);
0598 
0599     if (rdev->mode_info.crtcs[0]->base.enabled)
0600         mode0 = &rdev->mode_info.crtcs[0]->base.mode;
0601     if (rdev->mode_info.crtcs[1]->base.enabled)
0602         mode1 = &rdev->mode_info.crtcs[1]->base.mode;
0603     /*
0604      * Set display0/1 priority up in the memory controller for
0605      * modes if the user specifies HIGH for displaypriority
0606      * option.
0607      */
0608     if ((rdev->disp_priority == 2) &&
0609         ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
0610         tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
0611         tmp &= C_000104_MC_DISP0R_INIT_LAT;
0612         tmp &= C_000104_MC_DISP1R_INIT_LAT;
0613         if (mode0)
0614             tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
0615         if (mode1)
0616             tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
0617         WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
0618     }
0619     rs690_line_buffer_adjust(rdev, mode0, mode1);
0620 
0621     if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
0622         WREG32(R_006C9C_DCP_CONTROL, 0);
0623     if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
0624         WREG32(R_006C9C_DCP_CONTROL, 2);
0625 
0626     rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
0627     rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
0628 
0629     rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true);
0630     rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true);
0631 
0632     tmp = (wm0_high.lb_request_fifo_depth - 1);
0633     tmp |= (wm1_high.lb_request_fifo_depth - 1) << 16;
0634     WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
0635 
0636     rs690_compute_mode_priority(rdev,
0637                     &wm0_high, &wm1_high,
0638                     mode0, mode1,
0639                     &d1mode_priority_a_cnt, &d2mode_priority_a_cnt);
0640     rs690_compute_mode_priority(rdev,
0641                     &wm0_low, &wm1_low,
0642                     mode0, mode1,
0643                     &d1mode_priority_b_cnt, &d2mode_priority_b_cnt);
0644 
0645     WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
0646     WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
0647     WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
0648     WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);
0649 }
0650 
0651 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
0652 {
0653     unsigned long flags;
0654     uint32_t r;
0655 
0656     spin_lock_irqsave(&rdev->mc_idx_lock, flags);
0657     WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
0658     r = RREG32(R_00007C_MC_DATA);
0659     WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
0660     spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
0661     return r;
0662 }
0663 
0664 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
0665 {
0666     unsigned long flags;
0667 
0668     spin_lock_irqsave(&rdev->mc_idx_lock, flags);
0669     WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
0670         S_000078_MC_IND_WR_EN(1));
0671     WREG32(R_00007C_MC_DATA, v);
0672     WREG32(R_000078_MC_INDEX, 0x7F);
0673     spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
0674 }
0675 
0676 static void rs690_mc_program(struct radeon_device *rdev)
0677 {
0678     struct rv515_mc_save save;
0679 
0680     /* Stops all mc clients */
0681     rv515_mc_stop(rdev, &save);
0682 
0683     /* Wait for mc idle */
0684     if (rs690_mc_wait_for_idle(rdev))
0685         dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
0686     /* Program MC, should be a 32bits limited address space */
0687     WREG32_MC(R_000100_MCCFG_FB_LOCATION,
0688             S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
0689             S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
0690     WREG32(R_000134_HDP_FB_LOCATION,
0691         S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
0692 
0693     rv515_mc_resume(rdev, &save);
0694 }
0695 
0696 static int rs690_startup(struct radeon_device *rdev)
0697 {
0698     int r;
0699 
0700     rs690_mc_program(rdev);
0701     /* Resume clock */
0702     rv515_clock_startup(rdev);
0703     /* Initialize GPU configuration (# pipes, ...) */
0704     rs690_gpu_init(rdev);
0705     /* Initialize GART (initialize after TTM so we can allocate
0706      * memory through TTM but finalize after TTM) */
0707     r = rs400_gart_enable(rdev);
0708     if (r)
0709         return r;
0710 
0711     /* allocate wb buffer */
0712     r = radeon_wb_init(rdev);
0713     if (r)
0714         return r;
0715 
0716     r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
0717     if (r) {
0718         dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
0719         return r;
0720     }
0721 
0722     /* Enable IRQ */
0723     if (!rdev->irq.installed) {
0724         r = radeon_irq_kms_init(rdev);
0725         if (r)
0726             return r;
0727     }
0728 
0729     rs600_irq_set(rdev);
0730     rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
0731     /* 1M ring buffer */
0732     r = r100_cp_init(rdev, 1024 * 1024);
0733     if (r) {
0734         dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
0735         return r;
0736     }
0737 
0738     r = radeon_ib_pool_init(rdev);
0739     if (r) {
0740         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
0741         return r;
0742     }
0743 
0744     r = radeon_audio_init(rdev);
0745     if (r) {
0746         dev_err(rdev->dev, "failed initializing audio\n");
0747         return r;
0748     }
0749 
0750     return 0;
0751 }
0752 
0753 int rs690_resume(struct radeon_device *rdev)
0754 {
0755     int r;
0756 
0757     /* Make sur GART are not working */
0758     rs400_gart_disable(rdev);
0759     /* Resume clock before doing reset */
0760     rv515_clock_startup(rdev);
0761     /* Reset gpu before posting otherwise ATOM will enter infinite loop */
0762     if (radeon_asic_reset(rdev)) {
0763         dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
0764             RREG32(R_000E40_RBBM_STATUS),
0765             RREG32(R_0007C0_CP_STAT));
0766     }
0767     /* post */
0768     atom_asic_init(rdev->mode_info.atom_context);
0769     /* Resume clock after posting */
0770     rv515_clock_startup(rdev);
0771     /* Initialize surface registers */
0772     radeon_surface_init(rdev);
0773 
0774     rdev->accel_working = true;
0775     r = rs690_startup(rdev);
0776     if (r) {
0777         rdev->accel_working = false;
0778     }
0779     return r;
0780 }
0781 
0782 int rs690_suspend(struct radeon_device *rdev)
0783 {
0784     radeon_pm_suspend(rdev);
0785     radeon_audio_fini(rdev);
0786     r100_cp_disable(rdev);
0787     radeon_wb_disable(rdev);
0788     rs600_irq_disable(rdev);
0789     rs400_gart_disable(rdev);
0790     return 0;
0791 }
0792 
0793 void rs690_fini(struct radeon_device *rdev)
0794 {
0795     radeon_pm_fini(rdev);
0796     radeon_audio_fini(rdev);
0797     r100_cp_fini(rdev);
0798     radeon_wb_fini(rdev);
0799     radeon_ib_pool_fini(rdev);
0800     radeon_gem_fini(rdev);
0801     rs400_gart_fini(rdev);
0802     radeon_irq_kms_fini(rdev);
0803     radeon_fence_driver_fini(rdev);
0804     radeon_bo_fini(rdev);
0805     radeon_atombios_fini(rdev);
0806     kfree(rdev->bios);
0807     rdev->bios = NULL;
0808 }
0809 
0810 int rs690_init(struct radeon_device *rdev)
0811 {
0812     int r;
0813 
0814     /* Disable VGA */
0815     rv515_vga_render_disable(rdev);
0816     /* Initialize scratch registers */
0817     radeon_scratch_init(rdev);
0818     /* Initialize surface registers */
0819     radeon_surface_init(rdev);
0820     /* restore some register to sane defaults */
0821     r100_restore_sanity(rdev);
0822     /* TODO: disable VGA need to use VGA request */
0823     /* BIOS*/
0824     if (!radeon_get_bios(rdev)) {
0825         if (ASIC_IS_AVIVO(rdev))
0826             return -EINVAL;
0827     }
0828     if (rdev->is_atom_bios) {
0829         r = radeon_atombios_init(rdev);
0830         if (r)
0831             return r;
0832     } else {
0833         dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
0834         return -EINVAL;
0835     }
0836     /* Reset gpu before posting otherwise ATOM will enter infinite loop */
0837     if (radeon_asic_reset(rdev)) {
0838         dev_warn(rdev->dev,
0839             "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
0840             RREG32(R_000E40_RBBM_STATUS),
0841             RREG32(R_0007C0_CP_STAT));
0842     }
0843     /* check if cards are posted or not */
0844     if (radeon_boot_test_post_card(rdev) == false)
0845         return -EINVAL;
0846 
0847     /* Initialize clocks */
0848     radeon_get_clock_info(rdev->ddev);
0849     /* initialize memory controller */
0850     rs690_mc_init(rdev);
0851     rv515_debugfs(rdev);
0852     /* Fence driver */
0853     radeon_fence_driver_init(rdev);
0854     /* Memory manager */
0855     r = radeon_bo_init(rdev);
0856     if (r)
0857         return r;
0858     r = rs400_gart_init(rdev);
0859     if (r)
0860         return r;
0861     rs600_set_safe_registers(rdev);
0862 
0863     /* Initialize power management */
0864     radeon_pm_init(rdev);
0865 
0866     rdev->accel_working = true;
0867     r = rs690_startup(rdev);
0868     if (r) {
0869         /* Somethings want wront with the accel init stop accel */
0870         dev_err(rdev->dev, "Disabling GPU acceleration\n");
0871         r100_cp_fini(rdev);
0872         radeon_wb_fini(rdev);
0873         radeon_ib_pool_fini(rdev);
0874         rs400_gart_fini(rdev);
0875         radeon_irq_kms_fini(rdev);
0876         rdev->accel_working = false;
0877     }
0878     return 0;
0879 }
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!