Back to home page

OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  * Copyright 2009 Jerome Glisse.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors: Dave Airlie
0025  *          Alex Deucher
0026  *          Jerome Glisse
0027  */
0028 #ifndef __RS600D_H__
0029 #define __RS600D_H__
0030 
0031 /* Registers */
0032 #define R_000040_GEN_INT_CNTL                        0x000040
0033 #define   S_000040_SCRATCH_INT_MASK(x)                 (((x) & 0x1) << 18)
0034 #define   G_000040_SCRATCH_INT_MASK(x)                 (((x) >> 18) & 0x1)
0035 #define   C_000040_SCRATCH_INT_MASK                    0xFFFBFFFF
0036 #define   S_000040_GUI_IDLE_MASK(x)                    (((x) & 0x1) << 19)
0037 #define   G_000040_GUI_IDLE_MASK(x)                    (((x) >> 19) & 0x1)
0038 #define   C_000040_GUI_IDLE_MASK                       0xFFF7FFFF
0039 #define   S_000040_DMA_VIPH1_INT_EN(x)                 (((x) & 0x1) << 13)
0040 #define   G_000040_DMA_VIPH1_INT_EN(x)                 (((x) >> 13) & 0x1)
0041 #define   C_000040_DMA_VIPH1_INT_EN                    0xFFFFDFFF
0042 #define   S_000040_DMA_VIPH2_INT_EN(x)                 (((x) & 0x1) << 14)
0043 #define   G_000040_DMA_VIPH2_INT_EN(x)                 (((x) >> 14) & 0x1)
0044 #define   C_000040_DMA_VIPH2_INT_EN                    0xFFFFBFFF
0045 #define   S_000040_DMA_VIPH3_INT_EN(x)                 (((x) & 0x1) << 15)
0046 #define   G_000040_DMA_VIPH3_INT_EN(x)                 (((x) >> 15) & 0x1)
0047 #define   C_000040_DMA_VIPH3_INT_EN                    0xFFFF7FFF
0048 #define   S_000040_I2C_INT_EN(x)                       (((x) & 0x1) << 17)
0049 #define   G_000040_I2C_INT_EN(x)                       (((x) >> 17) & 0x1)
0050 #define   C_000040_I2C_INT_EN                          0xFFFDFFFF
0051 #define   S_000040_GUI_IDLE(x)                         (((x) & 0x1) << 19)
0052 #define   G_000040_GUI_IDLE(x)                         (((x) >> 19) & 0x1)
0053 #define   C_000040_GUI_IDLE                            0xFFF7FFFF
0054 #define   S_000040_VIPH_INT_EN(x)                      (((x) & 0x1) << 24)
0055 #define   G_000040_VIPH_INT_EN(x)                      (((x) >> 24) & 0x1)
0056 #define   C_000040_VIPH_INT_EN                         0xFEFFFFFF
0057 #define   S_000040_SW_INT_EN(x)                        (((x) & 0x1) << 25)
0058 #define   G_000040_SW_INT_EN(x)                        (((x) >> 25) & 0x1)
0059 #define   C_000040_SW_INT_EN                           0xFDFFFFFF
0060 #define   S_000040_GEYSERVILLE(x)                      (((x) & 0x1) << 27)
0061 #define   G_000040_GEYSERVILLE(x)                      (((x) >> 27) & 0x1)
0062 #define   C_000040_GEYSERVILLE                         0xF7FFFFFF
0063 #define   S_000040_HDCP_AUTHORIZED_INT(x)              (((x) & 0x1) << 28)
0064 #define   G_000040_HDCP_AUTHORIZED_INT(x)              (((x) >> 28) & 0x1)
0065 #define   C_000040_HDCP_AUTHORIZED_INT                 0xEFFFFFFF
0066 #define   S_000040_DVI_I2C_INT(x)                      (((x) & 0x1) << 29)
0067 #define   G_000040_DVI_I2C_INT(x)                      (((x) >> 29) & 0x1)
0068 #define   C_000040_DVI_I2C_INT                         0xDFFFFFFF
0069 #define   S_000040_GUIDMA(x)                           (((x) & 0x1) << 30)
0070 #define   G_000040_GUIDMA(x)                           (((x) >> 30) & 0x1)
0071 #define   C_000040_GUIDMA                              0xBFFFFFFF
0072 #define   S_000040_VIDDMA(x)                           (((x) & 0x1) << 31)
0073 #define   G_000040_VIDDMA(x)                           (((x) >> 31) & 0x1)
0074 #define   C_000040_VIDDMA                              0x7FFFFFFF
0075 #define R_000044_GEN_INT_STATUS                      0x000044
0076 #define   S_000044_DISPLAY_INT_STAT(x)                 (((x) & 0x1) << 0)
0077 #define   G_000044_DISPLAY_INT_STAT(x)                 (((x) >> 0) & 0x1)
0078 #define   C_000044_DISPLAY_INT_STAT                    0xFFFFFFFE
0079 #define   S_000044_VGA_INT_STAT(x)                     (((x) & 0x1) << 1)
0080 #define   G_000044_VGA_INT_STAT(x)                     (((x) >> 1) & 0x1)
0081 #define   C_000044_VGA_INT_STAT                        0xFFFFFFFD
0082 #define   S_000044_CAP0_INT_ACTIVE(x)                  (((x) & 0x1) << 8)
0083 #define   G_000044_CAP0_INT_ACTIVE(x)                  (((x) >> 8) & 0x1)
0084 #define   C_000044_CAP0_INT_ACTIVE                     0xFFFFFEFF
0085 #define   S_000044_DMA_VIPH0_INT(x)                    (((x) & 0x1) << 12)
0086 #define   G_000044_DMA_VIPH0_INT(x)                    (((x) >> 12) & 0x1)
0087 #define   C_000044_DMA_VIPH0_INT                       0xFFFFEFFF
0088 #define   S_000044_DMA_VIPH1_INT(x)                    (((x) & 0x1) << 13)
0089 #define   G_000044_DMA_VIPH1_INT(x)                    (((x) >> 13) & 0x1)
0090 #define   C_000044_DMA_VIPH1_INT                       0xFFFFDFFF
0091 #define   S_000044_DMA_VIPH2_INT(x)                    (((x) & 0x1) << 14)
0092 #define   G_000044_DMA_VIPH2_INT(x)                    (((x) >> 14) & 0x1)
0093 #define   C_000044_DMA_VIPH2_INT                       0xFFFFBFFF
0094 #define   S_000044_DMA_VIPH3_INT(x)                    (((x) & 0x1) << 15)
0095 #define   G_000044_DMA_VIPH3_INT(x)                    (((x) >> 15) & 0x1)
0096 #define   C_000044_DMA_VIPH3_INT                       0xFFFF7FFF
0097 #define   S_000044_MC_PROBE_FAULT_STAT(x)              (((x) & 0x1) << 16)
0098 #define   G_000044_MC_PROBE_FAULT_STAT(x)              (((x) >> 16) & 0x1)
0099 #define   C_000044_MC_PROBE_FAULT_STAT                 0xFFFEFFFF
0100 #define   S_000044_I2C_INT(x)                          (((x) & 0x1) << 17)
0101 #define   G_000044_I2C_INT(x)                          (((x) >> 17) & 0x1)
0102 #define   C_000044_I2C_INT                             0xFFFDFFFF
0103 #define   S_000044_SCRATCH_INT_STAT(x)                 (((x) & 0x1) << 18)
0104 #define   G_000044_SCRATCH_INT_STAT(x)                 (((x) >> 18) & 0x1)
0105 #define   C_000044_SCRATCH_INT_STAT                    0xFFFBFFFF
0106 #define   S_000044_GUI_IDLE_STAT(x)                    (((x) & 0x1) << 19)
0107 #define   G_000044_GUI_IDLE_STAT(x)                    (((x) >> 19) & 0x1)
0108 #define   C_000044_GUI_IDLE_STAT                       0xFFF7FFFF
0109 #define   S_000044_ATI_OVERDRIVE_INT_STAT(x)           (((x) & 0x1) << 20)
0110 #define   G_000044_ATI_OVERDRIVE_INT_STAT(x)           (((x) >> 20) & 0x1)
0111 #define   C_000044_ATI_OVERDRIVE_INT_STAT              0xFFEFFFFF
0112 #define   S_000044_MC_PROTECTION_FAULT_STAT(x)         (((x) & 0x1) << 21)
0113 #define   G_000044_MC_PROTECTION_FAULT_STAT(x)         (((x) >> 21) & 0x1)
0114 #define   C_000044_MC_PROTECTION_FAULT_STAT            0xFFDFFFFF
0115 #define   S_000044_RBBM_READ_INT_STAT(x)               (((x) & 0x1) << 22)
0116 #define   G_000044_RBBM_READ_INT_STAT(x)               (((x) >> 22) & 0x1)
0117 #define   C_000044_RBBM_READ_INT_STAT                  0xFFBFFFFF
0118 #define   S_000044_CB_CONTEXT_SWITCH_STAT(x)           (((x) & 0x1) << 23)
0119 #define   G_000044_CB_CONTEXT_SWITCH_STAT(x)           (((x) >> 23) & 0x1)
0120 #define   C_000044_CB_CONTEXT_SWITCH_STAT              0xFF7FFFFF
0121 #define   S_000044_VIPH_INT(x)                         (((x) & 0x1) << 24)
0122 #define   G_000044_VIPH_INT(x)                         (((x) >> 24) & 0x1)
0123 #define   C_000044_VIPH_INT                            0xFEFFFFFF
0124 #define   S_000044_SW_INT(x)                           (((x) & 0x1) << 25)
0125 #define   G_000044_SW_INT(x)                           (((x) >> 25) & 0x1)
0126 #define   C_000044_SW_INT                              0xFDFFFFFF
0127 #define   S_000044_SW_INT_SET(x)                       (((x) & 0x1) << 26)
0128 #define   G_000044_SW_INT_SET(x)                       (((x) >> 26) & 0x1)
0129 #define   C_000044_SW_INT_SET                          0xFBFFFFFF
0130 #define   S_000044_IDCT_INT_STAT(x)                    (((x) & 0x1) << 27)
0131 #define   G_000044_IDCT_INT_STAT(x)                    (((x) >> 27) & 0x1)
0132 #define   C_000044_IDCT_INT_STAT                       0xF7FFFFFF
0133 #define   S_000044_GUIDMA_STAT(x)                      (((x) & 0x1) << 30)
0134 #define   G_000044_GUIDMA_STAT(x)                      (((x) >> 30) & 0x1)
0135 #define   C_000044_GUIDMA_STAT                         0xBFFFFFFF
0136 #define   S_000044_VIDDMA_STAT(x)                      (((x) & 0x1) << 31)
0137 #define   G_000044_VIDDMA_STAT(x)                      (((x) >> 31) & 0x1)
0138 #define   C_000044_VIDDMA_STAT                         0x7FFFFFFF
0139 #define R_00004C_BUS_CNTL                            0x00004C
0140 #define   S_00004C_BUS_MASTER_DIS(x)                   (((x) & 0x1) << 14)
0141 #define   G_00004C_BUS_MASTER_DIS(x)                   (((x) >> 14) & 0x1)
0142 #define   C_00004C_BUS_MASTER_DIS                      0xFFFFBFFF
0143 #define   S_00004C_BUS_MSI_REARM(x)                    (((x) & 0x1) << 20)
0144 #define   G_00004C_BUS_MSI_REARM(x)                    (((x) >> 20) & 0x1)
0145 #define   C_00004C_BUS_MSI_REARM                       0xFFEFFFFF
0146 #define R_000070_MC_IND_INDEX                        0x000070
0147 #define   S_000070_MC_IND_ADDR(x)                      (((x) & 0xFFFF) << 0)
0148 #define   G_000070_MC_IND_ADDR(x)                      (((x) >> 0) & 0xFFFF)
0149 #define   C_000070_MC_IND_ADDR                         0xFFFF0000
0150 #define   S_000070_MC_IND_SEQ_RBS_0(x)                 (((x) & 0x1) << 16)
0151 #define   G_000070_MC_IND_SEQ_RBS_0(x)                 (((x) >> 16) & 0x1)
0152 #define   C_000070_MC_IND_SEQ_RBS_0                    0xFFFEFFFF
0153 #define   S_000070_MC_IND_SEQ_RBS_1(x)                 (((x) & 0x1) << 17)
0154 #define   G_000070_MC_IND_SEQ_RBS_1(x)                 (((x) >> 17) & 0x1)
0155 #define   C_000070_MC_IND_SEQ_RBS_1                    0xFFFDFFFF
0156 #define   S_000070_MC_IND_SEQ_RBS_2(x)                 (((x) & 0x1) << 18)
0157 #define   G_000070_MC_IND_SEQ_RBS_2(x)                 (((x) >> 18) & 0x1)
0158 #define   C_000070_MC_IND_SEQ_RBS_2                    0xFFFBFFFF
0159 #define   S_000070_MC_IND_SEQ_RBS_3(x)                 (((x) & 0x1) << 19)
0160 #define   G_000070_MC_IND_SEQ_RBS_3(x)                 (((x) >> 19) & 0x1)
0161 #define   C_000070_MC_IND_SEQ_RBS_3                    0xFFF7FFFF
0162 #define   S_000070_MC_IND_AIC_RBS(x)                   (((x) & 0x1) << 20)
0163 #define   G_000070_MC_IND_AIC_RBS(x)                   (((x) >> 20) & 0x1)
0164 #define   C_000070_MC_IND_AIC_RBS                      0xFFEFFFFF
0165 #define   S_000070_MC_IND_CITF_ARB0(x)                 (((x) & 0x1) << 21)
0166 #define   G_000070_MC_IND_CITF_ARB0(x)                 (((x) >> 21) & 0x1)
0167 #define   C_000070_MC_IND_CITF_ARB0                    0xFFDFFFFF
0168 #define   S_000070_MC_IND_CITF_ARB1(x)                 (((x) & 0x1) << 22)
0169 #define   G_000070_MC_IND_CITF_ARB1(x)                 (((x) >> 22) & 0x1)
0170 #define   C_000070_MC_IND_CITF_ARB1                    0xFFBFFFFF
0171 #define   S_000070_MC_IND_WR_EN(x)                     (((x) & 0x1) << 23)
0172 #define   G_000070_MC_IND_WR_EN(x)                     (((x) >> 23) & 0x1)
0173 #define   C_000070_MC_IND_WR_EN                        0xFF7FFFFF
0174 #define   S_000070_MC_IND_RD_INV(x)                    (((x) & 0x1) << 24)
0175 #define   G_000070_MC_IND_RD_INV(x)                    (((x) >> 24) & 0x1)
0176 #define   C_000070_MC_IND_RD_INV                       0xFEFFFFFF
0177 #define R_000074_MC_IND_DATA                         0x000074
0178 #define   S_000074_MC_IND_DATA(x)                      (((x) & 0xFFFFFFFF) << 0)
0179 #define   G_000074_MC_IND_DATA(x)                      (((x) >> 0) & 0xFFFFFFFF)
0180 #define   C_000074_MC_IND_DATA                         0x00000000
0181 #define R_0000F0_RBBM_SOFT_RESET                     0x0000F0
0182 #define   S_0000F0_SOFT_RESET_CP(x)                    (((x) & 0x1) << 0)
0183 #define   G_0000F0_SOFT_RESET_CP(x)                    (((x) >> 0) & 0x1)
0184 #define   C_0000F0_SOFT_RESET_CP                       0xFFFFFFFE
0185 #define   S_0000F0_SOFT_RESET_HI(x)                    (((x) & 0x1) << 1)
0186 #define   G_0000F0_SOFT_RESET_HI(x)                    (((x) >> 1) & 0x1)
0187 #define   C_0000F0_SOFT_RESET_HI                       0xFFFFFFFD
0188 #define   S_0000F0_SOFT_RESET_VAP(x)                   (((x) & 0x1) << 2)
0189 #define   G_0000F0_SOFT_RESET_VAP(x)                   (((x) >> 2) & 0x1)
0190 #define   C_0000F0_SOFT_RESET_VAP                      0xFFFFFFFB
0191 #define   S_0000F0_SOFT_RESET_RE(x)                    (((x) & 0x1) << 3)
0192 #define   G_0000F0_SOFT_RESET_RE(x)                    (((x) >> 3) & 0x1)
0193 #define   C_0000F0_SOFT_RESET_RE                       0xFFFFFFF7
0194 #define   S_0000F0_SOFT_RESET_PP(x)                    (((x) & 0x1) << 4)
0195 #define   G_0000F0_SOFT_RESET_PP(x)                    (((x) >> 4) & 0x1)
0196 #define   C_0000F0_SOFT_RESET_PP                       0xFFFFFFEF
0197 #define   S_0000F0_SOFT_RESET_E2(x)                    (((x) & 0x1) << 5)
0198 #define   G_0000F0_SOFT_RESET_E2(x)                    (((x) >> 5) & 0x1)
0199 #define   C_0000F0_SOFT_RESET_E2                       0xFFFFFFDF
0200 #define   S_0000F0_SOFT_RESET_RB(x)                    (((x) & 0x1) << 6)
0201 #define   G_0000F0_SOFT_RESET_RB(x)                    (((x) >> 6) & 0x1)
0202 #define   C_0000F0_SOFT_RESET_RB                       0xFFFFFFBF
0203 #define   S_0000F0_SOFT_RESET_HDP(x)                   (((x) & 0x1) << 7)
0204 #define   G_0000F0_SOFT_RESET_HDP(x)                   (((x) >> 7) & 0x1)
0205 #define   C_0000F0_SOFT_RESET_HDP                      0xFFFFFF7F
0206 #define   S_0000F0_SOFT_RESET_MC(x)                    (((x) & 0x1) << 8)
0207 #define   G_0000F0_SOFT_RESET_MC(x)                    (((x) >> 8) & 0x1)
0208 #define   C_0000F0_SOFT_RESET_MC                       0xFFFFFEFF
0209 #define   S_0000F0_SOFT_RESET_AIC(x)                   (((x) & 0x1) << 9)
0210 #define   G_0000F0_SOFT_RESET_AIC(x)                   (((x) >> 9) & 0x1)
0211 #define   C_0000F0_SOFT_RESET_AIC                      0xFFFFFDFF
0212 #define   S_0000F0_SOFT_RESET_VIP(x)                   (((x) & 0x1) << 10)
0213 #define   G_0000F0_SOFT_RESET_VIP(x)                   (((x) >> 10) & 0x1)
0214 #define   C_0000F0_SOFT_RESET_VIP                      0xFFFFFBFF
0215 #define   S_0000F0_SOFT_RESET_DISP(x)                  (((x) & 0x1) << 11)
0216 #define   G_0000F0_SOFT_RESET_DISP(x)                  (((x) >> 11) & 0x1)
0217 #define   C_0000F0_SOFT_RESET_DISP                     0xFFFFF7FF
0218 #define   S_0000F0_SOFT_RESET_CG(x)                    (((x) & 0x1) << 12)
0219 #define   G_0000F0_SOFT_RESET_CG(x)                    (((x) >> 12) & 0x1)
0220 #define   C_0000F0_SOFT_RESET_CG                       0xFFFFEFFF
0221 #define   S_0000F0_SOFT_RESET_GA(x)                    (((x) & 0x1) << 13)
0222 #define   G_0000F0_SOFT_RESET_GA(x)                    (((x) >> 13) & 0x1)
0223 #define   C_0000F0_SOFT_RESET_GA                       0xFFFFDFFF
0224 #define   S_0000F0_SOFT_RESET_IDCT(x)                  (((x) & 0x1) << 14)
0225 #define   G_0000F0_SOFT_RESET_IDCT(x)                  (((x) >> 14) & 0x1)
0226 #define   C_0000F0_SOFT_RESET_IDCT                     0xFFFFBFFF
0227 #define R_000134_HDP_FB_LOCATION                     0x000134
0228 #define   S_000134_HDP_FB_START(x)                     (((x) & 0xFFFF) << 0)
0229 #define   G_000134_HDP_FB_START(x)                     (((x) >> 0) & 0xFFFF)
0230 #define   C_000134_HDP_FB_START                        0xFFFF0000
0231 #define R_0007C0_CP_STAT                             0x0007C0
0232 #define   S_0007C0_MRU_BUSY(x)                         (((x) & 0x1) << 0)
0233 #define   G_0007C0_MRU_BUSY(x)                         (((x) >> 0) & 0x1)
0234 #define   C_0007C0_MRU_BUSY                            0xFFFFFFFE
0235 #define   S_0007C0_MWU_BUSY(x)                         (((x) & 0x1) << 1)
0236 #define   G_0007C0_MWU_BUSY(x)                         (((x) >> 1) & 0x1)
0237 #define   C_0007C0_MWU_BUSY                            0xFFFFFFFD
0238 #define   S_0007C0_RSIU_BUSY(x)                        (((x) & 0x1) << 2)
0239 #define   G_0007C0_RSIU_BUSY(x)                        (((x) >> 2) & 0x1)
0240 #define   C_0007C0_RSIU_BUSY                           0xFFFFFFFB
0241 #define   S_0007C0_RCIU_BUSY(x)                        (((x) & 0x1) << 3)
0242 #define   G_0007C0_RCIU_BUSY(x)                        (((x) >> 3) & 0x1)
0243 #define   C_0007C0_RCIU_BUSY                           0xFFFFFFF7
0244 #define   S_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) & 0x1) << 9)
0245 #define   G_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) >> 9) & 0x1)
0246 #define   C_0007C0_CSF_PRIMARY_BUSY                    0xFFFFFDFF
0247 #define   S_0007C0_CSF_INDIRECT_BUSY(x)                (((x) & 0x1) << 10)
0248 #define   G_0007C0_CSF_INDIRECT_BUSY(x)                (((x) >> 10) & 0x1)
0249 #define   C_0007C0_CSF_INDIRECT_BUSY                   0xFFFFFBFF
0250 #define   S_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) & 0x1) << 11)
0251 #define   G_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) >> 11) & 0x1)
0252 #define   C_0007C0_CSQ_PRIMARY_BUSY                    0xFFFFF7FF
0253 #define   S_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) & 0x1) << 12)
0254 #define   G_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) >> 12) & 0x1)
0255 #define   C_0007C0_CSQ_INDIRECT_BUSY                   0xFFFFEFFF
0256 #define   S_0007C0_CSI_BUSY(x)                         (((x) & 0x1) << 13)
0257 #define   G_0007C0_CSI_BUSY(x)                         (((x) >> 13) & 0x1)
0258 #define   C_0007C0_CSI_BUSY                            0xFFFFDFFF
0259 #define   S_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) & 0x1) << 14)
0260 #define   G_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) >> 14) & 0x1)
0261 #define   C_0007C0_CSF_INDIRECT2_BUSY                  0xFFFFBFFF
0262 #define   S_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) & 0x1) << 15)
0263 #define   G_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) >> 15) & 0x1)
0264 #define   C_0007C0_CSQ_INDIRECT2_BUSY                  0xFFFF7FFF
0265 #define   S_0007C0_GUIDMA_BUSY(x)                      (((x) & 0x1) << 28)
0266 #define   G_0007C0_GUIDMA_BUSY(x)                      (((x) >> 28) & 0x1)
0267 #define   C_0007C0_GUIDMA_BUSY                         0xEFFFFFFF
0268 #define   S_0007C0_VIDDMA_BUSY(x)                      (((x) & 0x1) << 29)
0269 #define   G_0007C0_VIDDMA_BUSY(x)                      (((x) >> 29) & 0x1)
0270 #define   C_0007C0_VIDDMA_BUSY                         0xDFFFFFFF
0271 #define   S_0007C0_CMDSTRM_BUSY(x)                     (((x) & 0x1) << 30)
0272 #define   G_0007C0_CMDSTRM_BUSY(x)                     (((x) >> 30) & 0x1)
0273 #define   C_0007C0_CMDSTRM_BUSY                        0xBFFFFFFF
0274 #define   S_0007C0_CP_BUSY(x)                          (((x) & 0x1) << 31)
0275 #define   G_0007C0_CP_BUSY(x)                          (((x) >> 31) & 0x1)
0276 #define   C_0007C0_CP_BUSY                             0x7FFFFFFF
0277 #define R_000E40_RBBM_STATUS                         0x000E40
0278 #define   S_000E40_CMDFIFO_AVAIL(x)                    (((x) & 0x7F) << 0)
0279 #define   G_000E40_CMDFIFO_AVAIL(x)                    (((x) >> 0) & 0x7F)
0280 #define   C_000E40_CMDFIFO_AVAIL                       0xFFFFFF80
0281 #define   S_000E40_HIRQ_ON_RBB(x)                      (((x) & 0x1) << 8)
0282 #define   G_000E40_HIRQ_ON_RBB(x)                      (((x) >> 8) & 0x1)
0283 #define   C_000E40_HIRQ_ON_RBB                         0xFFFFFEFF
0284 #define   S_000E40_CPRQ_ON_RBB(x)                      (((x) & 0x1) << 9)
0285 #define   G_000E40_CPRQ_ON_RBB(x)                      (((x) >> 9) & 0x1)
0286 #define   C_000E40_CPRQ_ON_RBB                         0xFFFFFDFF
0287 #define   S_000E40_CFRQ_ON_RBB(x)                      (((x) & 0x1) << 10)
0288 #define   G_000E40_CFRQ_ON_RBB(x)                      (((x) >> 10) & 0x1)
0289 #define   C_000E40_CFRQ_ON_RBB                         0xFFFFFBFF
0290 #define   S_000E40_HIRQ_IN_RTBUF(x)                    (((x) & 0x1) << 11)
0291 #define   G_000E40_HIRQ_IN_RTBUF(x)                    (((x) >> 11) & 0x1)
0292 #define   C_000E40_HIRQ_IN_RTBUF                       0xFFFFF7FF
0293 #define   S_000E40_CPRQ_IN_RTBUF(x)                    (((x) & 0x1) << 12)
0294 #define   G_000E40_CPRQ_IN_RTBUF(x)                    (((x) >> 12) & 0x1)
0295 #define   C_000E40_CPRQ_IN_RTBUF                       0xFFFFEFFF
0296 #define   S_000E40_CFRQ_IN_RTBUF(x)                    (((x) & 0x1) << 13)
0297 #define   G_000E40_CFRQ_IN_RTBUF(x)                    (((x) >> 13) & 0x1)
0298 #define   C_000E40_CFRQ_IN_RTBUF                       0xFFFFDFFF
0299 #define   S_000E40_CF_PIPE_BUSY(x)                     (((x) & 0x1) << 14)
0300 #define   G_000E40_CF_PIPE_BUSY(x)                     (((x) >> 14) & 0x1)
0301 #define   C_000E40_CF_PIPE_BUSY                        0xFFFFBFFF
0302 #define   S_000E40_ENG_EV_BUSY(x)                      (((x) & 0x1) << 15)
0303 #define   G_000E40_ENG_EV_BUSY(x)                      (((x) >> 15) & 0x1)
0304 #define   C_000E40_ENG_EV_BUSY                         0xFFFF7FFF
0305 #define   S_000E40_CP_CMDSTRM_BUSY(x)                  (((x) & 0x1) << 16)
0306 #define   G_000E40_CP_CMDSTRM_BUSY(x)                  (((x) >> 16) & 0x1)
0307 #define   C_000E40_CP_CMDSTRM_BUSY                     0xFFFEFFFF
0308 #define   S_000E40_E2_BUSY(x)                          (((x) & 0x1) << 17)
0309 #define   G_000E40_E2_BUSY(x)                          (((x) >> 17) & 0x1)
0310 #define   C_000E40_E2_BUSY                             0xFFFDFFFF
0311 #define   S_000E40_RB2D_BUSY(x)                        (((x) & 0x1) << 18)
0312 #define   G_000E40_RB2D_BUSY(x)                        (((x) >> 18) & 0x1)
0313 #define   C_000E40_RB2D_BUSY                           0xFFFBFFFF
0314 #define   S_000E40_RB3D_BUSY(x)                        (((x) & 0x1) << 19)
0315 #define   G_000E40_RB3D_BUSY(x)                        (((x) >> 19) & 0x1)
0316 #define   C_000E40_RB3D_BUSY                           0xFFF7FFFF
0317 #define   S_000E40_VAP_BUSY(x)                         (((x) & 0x1) << 20)
0318 #define   G_000E40_VAP_BUSY(x)                         (((x) >> 20) & 0x1)
0319 #define   C_000E40_VAP_BUSY                            0xFFEFFFFF
0320 #define   S_000E40_RE_BUSY(x)                          (((x) & 0x1) << 21)
0321 #define   G_000E40_RE_BUSY(x)                          (((x) >> 21) & 0x1)
0322 #define   C_000E40_RE_BUSY                             0xFFDFFFFF
0323 #define   S_000E40_TAM_BUSY(x)                         (((x) & 0x1) << 22)
0324 #define   G_000E40_TAM_BUSY(x)                         (((x) >> 22) & 0x1)
0325 #define   C_000E40_TAM_BUSY                            0xFFBFFFFF
0326 #define   S_000E40_TDM_BUSY(x)                         (((x) & 0x1) << 23)
0327 #define   G_000E40_TDM_BUSY(x)                         (((x) >> 23) & 0x1)
0328 #define   C_000E40_TDM_BUSY                            0xFF7FFFFF
0329 #define   S_000E40_PB_BUSY(x)                          (((x) & 0x1) << 24)
0330 #define   G_000E40_PB_BUSY(x)                          (((x) >> 24) & 0x1)
0331 #define   C_000E40_PB_BUSY                             0xFEFFFFFF
0332 #define   S_000E40_TIM_BUSY(x)                         (((x) & 0x1) << 25)
0333 #define   G_000E40_TIM_BUSY(x)                         (((x) >> 25) & 0x1)
0334 #define   C_000E40_TIM_BUSY                            0xFDFFFFFF
0335 #define   S_000E40_GA_BUSY(x)                          (((x) & 0x1) << 26)
0336 #define   G_000E40_GA_BUSY(x)                          (((x) >> 26) & 0x1)
0337 #define   C_000E40_GA_BUSY                             0xFBFFFFFF
0338 #define   S_000E40_CBA2D_BUSY(x)                       (((x) & 0x1) << 27)
0339 #define   G_000E40_CBA2D_BUSY(x)                       (((x) >> 27) & 0x1)
0340 #define   C_000E40_CBA2D_BUSY                          0xF7FFFFFF
0341 #define   S_000E40_GUI_ACTIVE(x)                       (((x) & 0x1) << 31)
0342 #define   G_000E40_GUI_ACTIVE(x)                       (((x) >> 31) & 0x1)
0343 #define   C_000E40_GUI_ACTIVE                          0x7FFFFFFF
0344 #define R_0060A4_D1CRTC_STATUS_FRAME_COUNT           0x0060A4
0345 #define   S_0060A4_D1CRTC_FRAME_COUNT(x)               (((x) & 0xFFFFFF) << 0)
0346 #define   G_0060A4_D1CRTC_FRAME_COUNT(x)               (((x) >> 0) & 0xFFFFFF)
0347 #define   C_0060A4_D1CRTC_FRAME_COUNT                  0xFF000000
0348 #define R_006534_D1MODE_VBLANK_STATUS                0x006534
0349 #define   S_006534_D1MODE_VBLANK_OCCURRED(x)           (((x) & 0x1) << 0)
0350 #define   G_006534_D1MODE_VBLANK_OCCURRED(x)           (((x) >> 0) & 0x1)
0351 #define   C_006534_D1MODE_VBLANK_OCCURRED              0xFFFFFFFE
0352 #define   S_006534_D1MODE_VBLANK_ACK(x)                (((x) & 0x1) << 4)
0353 #define   G_006534_D1MODE_VBLANK_ACK(x)                (((x) >> 4) & 0x1)
0354 #define   C_006534_D1MODE_VBLANK_ACK                   0xFFFFFFEF
0355 #define   S_006534_D1MODE_VBLANK_STAT(x)               (((x) & 0x1) << 12)
0356 #define   G_006534_D1MODE_VBLANK_STAT(x)               (((x) >> 12) & 0x1)
0357 #define   C_006534_D1MODE_VBLANK_STAT                  0xFFFFEFFF
0358 #define   S_006534_D1MODE_VBLANK_INTERRUPT(x)          (((x) & 0x1) << 16)
0359 #define   G_006534_D1MODE_VBLANK_INTERRUPT(x)          (((x) >> 16) & 0x1)
0360 #define   C_006534_D1MODE_VBLANK_INTERRUPT             0xFFFEFFFF
0361 #define R_006540_DxMODE_INT_MASK                     0x006540
0362 #define   S_006540_D1MODE_VBLANK_INT_MASK(x)           (((x) & 0x1) << 0)
0363 #define   G_006540_D1MODE_VBLANK_INT_MASK(x)           (((x) >> 0) & 0x1)
0364 #define   C_006540_D1MODE_VBLANK_INT_MASK              0xFFFFFFFE
0365 #define   S_006540_D1MODE_VLINE_INT_MASK(x)            (((x) & 0x1) << 4)
0366 #define   G_006540_D1MODE_VLINE_INT_MASK(x)            (((x) >> 4) & 0x1)
0367 #define   C_006540_D1MODE_VLINE_INT_MASK               0xFFFFFFEF
0368 #define   S_006540_D2MODE_VBLANK_INT_MASK(x)           (((x) & 0x1) << 8)
0369 #define   G_006540_D2MODE_VBLANK_INT_MASK(x)           (((x) >> 8) & 0x1)
0370 #define   C_006540_D2MODE_VBLANK_INT_MASK              0xFFFFFEFF
0371 #define   S_006540_D2MODE_VLINE_INT_MASK(x)            (((x) & 0x1) << 12)
0372 #define   G_006540_D2MODE_VLINE_INT_MASK(x)            (((x) >> 12) & 0x1)
0373 #define   C_006540_D2MODE_VLINE_INT_MASK               0xFFFFEFFF
0374 #define   S_006540_D1MODE_VBLANK_CP_SEL(x)             (((x) & 0x1) << 30)
0375 #define   G_006540_D1MODE_VBLANK_CP_SEL(x)             (((x) >> 30) & 0x1)
0376 #define   C_006540_D1MODE_VBLANK_CP_SEL                0xBFFFFFFF
0377 #define   S_006540_D2MODE_VBLANK_CP_SEL(x)             (((x) & 0x1) << 31)
0378 #define   G_006540_D2MODE_VBLANK_CP_SEL(x)             (((x) >> 31) & 0x1)
0379 #define   C_006540_D2MODE_VBLANK_CP_SEL                0x7FFFFFFF
0380 #define R_0068A4_D2CRTC_STATUS_FRAME_COUNT           0x0068A4
0381 #define   S_0068A4_D2CRTC_FRAME_COUNT(x)               (((x) & 0xFFFFFF) << 0)
0382 #define   G_0068A4_D2CRTC_FRAME_COUNT(x)               (((x) >> 0) & 0xFFFFFF)
0383 #define   C_0068A4_D2CRTC_FRAME_COUNT                  0xFF000000
0384 #define R_006D34_D2MODE_VBLANK_STATUS                0x006D34
0385 #define   S_006D34_D2MODE_VBLANK_OCCURRED(x)           (((x) & 0x1) << 0)
0386 #define   G_006D34_D2MODE_VBLANK_OCCURRED(x)           (((x) >> 0) & 0x1)
0387 #define   C_006D34_D2MODE_VBLANK_OCCURRED              0xFFFFFFFE
0388 #define   S_006D34_D2MODE_VBLANK_ACK(x)                (((x) & 0x1) << 4)
0389 #define   G_006D34_D2MODE_VBLANK_ACK(x)                (((x) >> 4) & 0x1)
0390 #define   C_006D34_D2MODE_VBLANK_ACK                   0xFFFFFFEF
0391 #define   S_006D34_D2MODE_VBLANK_STAT(x)               (((x) & 0x1) << 12)
0392 #define   G_006D34_D2MODE_VBLANK_STAT(x)               (((x) >> 12) & 0x1)
0393 #define   C_006D34_D2MODE_VBLANK_STAT                  0xFFFFEFFF
0394 #define   S_006D34_D2MODE_VBLANK_INTERRUPT(x)          (((x) & 0x1) << 16)
0395 #define   G_006D34_D2MODE_VBLANK_INTERRUPT(x)          (((x) >> 16) & 0x1)
0396 #define   C_006D34_D2MODE_VBLANK_INTERRUPT             0xFFFEFFFF
0397 #define R_007EDC_DISP_INTERRUPT_STATUS               0x007EDC
0398 #define   S_007EDC_LB_D1_VBLANK_INTERRUPT(x)           (((x) & 0x1) << 4)
0399 #define   G_007EDC_LB_D1_VBLANK_INTERRUPT(x)           (((x) >> 4) & 0x1)
0400 #define   C_007EDC_LB_D1_VBLANK_INTERRUPT              0xFFFFFFEF
0401 #define   S_007EDC_LB_D2_VBLANK_INTERRUPT(x)           (((x) & 0x1) << 5)
0402 #define   G_007EDC_LB_D2_VBLANK_INTERRUPT(x)           (((x) >> 5) & 0x1)
0403 #define   C_007EDC_LB_D2_VBLANK_INTERRUPT              0xFFFFFFDF
0404 #define   S_007EDC_DACA_AUTODETECT_INTERRUPT(x)        (((x) & 0x1) << 16)
0405 #define   G_007EDC_DACA_AUTODETECT_INTERRUPT(x)        (((x) >> 16) & 0x1)
0406 #define   C_007EDC_DACA_AUTODETECT_INTERRUPT           0xFFFEFFFF
0407 #define   S_007EDC_DACB_AUTODETECT_INTERRUPT(x)        (((x) & 0x1) << 17)
0408 #define   G_007EDC_DACB_AUTODETECT_INTERRUPT(x)        (((x) >> 17) & 0x1)
0409 #define   C_007EDC_DACB_AUTODETECT_INTERRUPT           0xFFFDFFFF
0410 #define   S_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x)    (((x) & 0x1) << 18)
0411 #define   G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x)    (((x) >> 18) & 0x1)
0412 #define   C_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT       0xFFFBFFFF
0413 #define   S_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x)    (((x) & 0x1) << 19)
0414 #define   G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x)    (((x) >> 19) & 0x1)
0415 #define   C_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT       0xFFF7FFFF
0416 #define R_007828_DACA_AUTODETECT_CONTROL               0x007828
0417 #define   S_007828_DACA_AUTODETECT_MODE(x)             (((x) & 0x3) << 0)
0418 #define   G_007828_DACA_AUTODETECT_MODE(x)             (((x) >> 0) & 0x3)
0419 #define   C_007828_DACA_AUTODETECT_MODE                0xFFFFFFFC
0420 #define   S_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8)
0421 #define   G_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff)
0422 #define   C_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER  0xFFFF00FF
0423 #define   S_007828_DACA_AUTODETECT_CHECK_MASK(x)       (((x) & 0x3) << 16)
0424 #define   G_007828_DACA_AUTODETECT_CHECK_MASK(x)       (((x) >> 16) & 0x3)
0425 #define   C_007828_DACA_AUTODETECT_CHECK_MASK          0xFFFCFFFF
0426 #define R_007838_DACA_AUTODETECT_INT_CONTROL           0x007838
0427 #define   S_007838_DACA_AUTODETECT_ACK(x)              (((x) & 0x1) << 0)
0428 #define   C_007838_DACA_DACA_AUTODETECT_ACK            0xFFFFFFFE
0429 #define   S_007838_DACA_AUTODETECT_INT_ENABLE(x)       (((x) & 0x1) << 16)
0430 #define   G_007838_DACA_AUTODETECT_INT_ENABLE(x)       (((x) >> 16) & 0x1)
0431 #define   C_007838_DACA_AUTODETECT_INT_ENABLE          0xFFFCFFFF
0432 #define R_007A28_DACB_AUTODETECT_CONTROL               0x007A28
0433 #define   S_007A28_DACB_AUTODETECT_MODE(x)             (((x) & 0x3) << 0)
0434 #define   G_007A28_DACB_AUTODETECT_MODE(x)             (((x) >> 0) & 0x3)
0435 #define   C_007A28_DACB_AUTODETECT_MODE                0xFFFFFFFC
0436 #define   S_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8)
0437 #define   G_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff)
0438 #define   C_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER  0xFFFF00FF
0439 #define   S_007A28_DACB_AUTODETECT_CHECK_MASK(x)       (((x) & 0x3) << 16)
0440 #define   G_007A28_DACB_AUTODETECT_CHECK_MASK(x)       (((x) >> 16) & 0x3)
0441 #define   C_007A28_DACB_AUTODETECT_CHECK_MASK          0xFFFCFFFF
0442 #define R_007A38_DACB_AUTODETECT_INT_CONTROL           0x007A38
0443 #define   S_007A38_DACB_AUTODETECT_ACK(x)              (((x) & 0x1) << 0)
0444 #define   C_007A38_DACB_DACA_AUTODETECT_ACK            0xFFFFFFFE
0445 #define   S_007A38_DACB_AUTODETECT_INT_ENABLE(x)       (((x) & 0x1) << 16)
0446 #define   G_007A38_DACB_AUTODETECT_INT_ENABLE(x)       (((x) >> 16) & 0x1)
0447 #define   C_007A38_DACB_AUTODETECT_INT_ENABLE          0xFFFCFFFF
0448 #define R_007D00_DC_HOT_PLUG_DETECT1_CONTROL           0x007D00
0449 #define   S_007D00_DC_HOT_PLUG_DETECT1_EN(x)           (((x) & 0x1) << 0)
0450 #define   G_007D00_DC_HOT_PLUG_DETECT1_EN(x)           (((x) >> 0) & 0x1)
0451 #define   C_007D00_DC_HOT_PLUG_DETECT1_EN              0xFFFFFFFE
0452 #define R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS        0x007D04
0453 #define   S_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x)   (((x) & 0x1) << 0)
0454 #define   G_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x)   (((x) >> 0) & 0x1)
0455 #define   C_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS      0xFFFFFFFE
0456 #define   S_007D04_DC_HOT_PLUG_DETECT1_SENSE(x)        (((x) & 0x1) << 1)
0457 #define   G_007D04_DC_HOT_PLUG_DETECT1_SENSE(x)        (((x) >> 1) & 0x1)
0458 #define   C_007D04_DC_HOT_PLUG_DETECT1_SENSE           0xFFFFFFFD
0459 #define R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL       0x007D08
0460 #define   S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(x)      (((x) & 0x1) << 0)
0461 #define   C_007D08_DC_HOT_PLUG_DETECT1_INT_ACK         0xFFFFFFFE
0462 #define   S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) & 0x1) << 8)
0463 #define   G_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) >> 8) & 0x1)
0464 #define   C_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY    0xFFFFFEFF
0465 #define   S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x)       (((x) & 0x1) << 16)
0466 #define   G_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x)       (((x) >> 16) & 0x1)
0467 #define   C_007D08_DC_HOT_PLUG_DETECT1_INT_EN          0xFFFEFFFF
0468 #define R_007D10_DC_HOT_PLUG_DETECT2_CONTROL           0x007D10
0469 #define   S_007D10_DC_HOT_PLUG_DETECT2_EN(x)           (((x) & 0x1) << 0)
0470 #define   G_007D10_DC_HOT_PLUG_DETECT2_EN(x)           (((x) >> 0) & 0x1)
0471 #define   C_007D10_DC_HOT_PLUG_DETECT2_EN              0xFFFFFFFE
0472 #define R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS        0x007D14
0473 #define   S_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x)   (((x) & 0x1) << 0)
0474 #define   G_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x)   (((x) >> 0) & 0x1)
0475 #define   C_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS      0xFFFFFFFE
0476 #define   S_007D14_DC_HOT_PLUG_DETECT2_SENSE(x)        (((x) & 0x1) << 1)
0477 #define   G_007D14_DC_HOT_PLUG_DETECT2_SENSE(x)        (((x) >> 1) & 0x1)
0478 #define   C_007D14_DC_HOT_PLUG_DETECT2_SENSE           0xFFFFFFFD
0479 #define R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL       0x007D18
0480 #define   S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(x)      (((x) & 0x1) << 0)
0481 #define   C_007D18_DC_HOT_PLUG_DETECT2_INT_ACK         0xFFFFFFFE
0482 #define   S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) & 0x1) << 8)
0483 #define   G_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) >> 8) & 0x1)
0484 #define   C_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY    0xFFFFFEFF
0485 #define   S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x)       (((x) & 0x1) << 16)
0486 #define   G_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x)       (((x) >> 16) & 0x1)
0487 #define   C_007D18_DC_HOT_PLUG_DETECT2_INT_EN          0xFFFEFFFF
0488 #define R_007404_HDMI0_STATUS                          0x007404
0489 #define   S_007404_HDMI0_AZ_FORMAT_WTRIG(x)            (((x) & 0x1) << 28)
0490 #define   G_007404_HDMI0_AZ_FORMAT_WTRIG(x)            (((x) >> 28) & 0x1)
0491 #define   C_007404_HDMI0_AZ_FORMAT_WTRIG               0xEFFFFFFF
0492 #define   S_007404_HDMI0_AZ_FORMAT_WTRIG_INT(x)        (((x) & 0x1) << 29)
0493 #define   G_007404_HDMI0_AZ_FORMAT_WTRIG_INT(x)        (((x) >> 29) & 0x1)
0494 #define   C_007404_HDMI0_AZ_FORMAT_WTRIG_INT           0xDFFFFFFF
0495 #define R_007408_HDMI0_AUDIO_PACKET_CONTROL            0x007408
0496 #define   S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(x)       (((x) & 0x1) << 28)
0497 #define   G_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(x)       (((x) >> 28) & 0x1)
0498 #define   C_007408_HDMI0_AZ_FORMAT_WTRIG_MASK          0xEFFFFFFF
0499 #define   S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(x)        (((x) & 0x1) << 29)
0500 #define   G_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(x)        (((x) >> 29) & 0x1)
0501 #define   C_007408_HDMI0_AZ_FORMAT_WTRIG_ACK           0xDFFFFFFF
0502 
0503 /* MC registers */
0504 #define R_000000_MC_STATUS                           0x000000
0505 #define   S_000000_MC_IDLE(x)                          (((x) & 0x1) << 0)
0506 #define   G_000000_MC_IDLE(x)                          (((x) >> 0) & 0x1)
0507 #define   C_000000_MC_IDLE                             0xFFFFFFFE
0508 #define R_000004_MC_FB_LOCATION                      0x000004
0509 #define   S_000004_MC_FB_START(x)                      (((x) & 0xFFFF) << 0)
0510 #define   G_000004_MC_FB_START(x)                      (((x) >> 0) & 0xFFFF)
0511 #define   C_000004_MC_FB_START                         0xFFFF0000
0512 #define   S_000004_MC_FB_TOP(x)                        (((x) & 0xFFFF) << 16)
0513 #define   G_000004_MC_FB_TOP(x)                        (((x) >> 16) & 0xFFFF)
0514 #define   C_000004_MC_FB_TOP                           0x0000FFFF
0515 #define R_000005_MC_AGP_LOCATION                     0x000005
0516 #define   S_000005_MC_AGP_START(x)                     (((x) & 0xFFFF) << 0)
0517 #define   G_000005_MC_AGP_START(x)                     (((x) >> 0) & 0xFFFF)
0518 #define   C_000005_MC_AGP_START                        0xFFFF0000
0519 #define   S_000005_MC_AGP_TOP(x)                       (((x) & 0xFFFF) << 16)
0520 #define   G_000005_MC_AGP_TOP(x)                       (((x) >> 16) & 0xFFFF)
0521 #define   C_000005_MC_AGP_TOP                          0x0000FFFF
0522 #define R_000006_AGP_BASE                            0x000006
0523 #define   S_000006_AGP_BASE_ADDR(x)                    (((x) & 0xFFFFFFFF) << 0)
0524 #define   G_000006_AGP_BASE_ADDR(x)                    (((x) >> 0) & 0xFFFFFFFF)
0525 #define   C_000006_AGP_BASE_ADDR                       0x00000000
0526 #define R_000007_AGP_BASE_2                          0x000007
0527 #define   S_000007_AGP_BASE_ADDR_2(x)                  (((x) & 0xF) << 0)
0528 #define   G_000007_AGP_BASE_ADDR_2(x)                  (((x) >> 0) & 0xF)
0529 #define   C_000007_AGP_BASE_ADDR_2                     0xFFFFFFF0
0530 #define R_000009_MC_CNTL1                            0x000009
0531 #define   S_000009_ENABLE_PAGE_TABLES(x)               (((x) & 0x1) << 26)
0532 #define   G_000009_ENABLE_PAGE_TABLES(x)               (((x) >> 26) & 0x1)
0533 #define   C_000009_ENABLE_PAGE_TABLES                  0xFBFFFFFF
0534 /* FIXME don't know the various field size need feedback from AMD */
0535 #define R_000100_MC_PT0_CNTL                         0x000100
0536 #define   S_000100_ENABLE_PT(x)                        (((x) & 0x1) << 0)
0537 #define   G_000100_ENABLE_PT(x)                        (((x) >> 0) & 0x1)
0538 #define   C_000100_ENABLE_PT                           0xFFFFFFFE
0539 #define   S_000100_EFFECTIVE_L2_CACHE_SIZE(x)          (((x) & 0x7) << 15)
0540 #define   G_000100_EFFECTIVE_L2_CACHE_SIZE(x)          (((x) >> 15) & 0x7)
0541 #define   C_000100_EFFECTIVE_L2_CACHE_SIZE             0xFFFC7FFF
0542 #define   S_000100_EFFECTIVE_L2_QUEUE_SIZE(x)          (((x) & 0x7) << 21)
0543 #define   G_000100_EFFECTIVE_L2_QUEUE_SIZE(x)          (((x) >> 21) & 0x7)
0544 #define   C_000100_EFFECTIVE_L2_QUEUE_SIZE             0xFF1FFFFF
0545 #define   S_000100_INVALIDATE_ALL_L1_TLBS(x)           (((x) & 0x1) << 28)
0546 #define   G_000100_INVALIDATE_ALL_L1_TLBS(x)           (((x) >> 28) & 0x1)
0547 #define   C_000100_INVALIDATE_ALL_L1_TLBS              0xEFFFFFFF
0548 #define   S_000100_INVALIDATE_L2_CACHE(x)              (((x) & 0x1) << 29)
0549 #define   G_000100_INVALIDATE_L2_CACHE(x)              (((x) >> 29) & 0x1)
0550 #define   C_000100_INVALIDATE_L2_CACHE                 0xDFFFFFFF
0551 #define R_000102_MC_PT0_CONTEXT0_CNTL                0x000102
0552 #define   S_000102_ENABLE_PAGE_TABLE(x)                (((x) & 0x1) << 0)
0553 #define   G_000102_ENABLE_PAGE_TABLE(x)                (((x) >> 0) & 0x1)
0554 #define   C_000102_ENABLE_PAGE_TABLE                   0xFFFFFFFE
0555 #define   S_000102_PAGE_TABLE_DEPTH(x)                 (((x) & 0x3) << 1)
0556 #define   G_000102_PAGE_TABLE_DEPTH(x)                 (((x) >> 1) & 0x3)
0557 #define   C_000102_PAGE_TABLE_DEPTH                    0xFFFFFFF9
0558 #define   V_000102_PAGE_TABLE_FLAT                     0
0559 /* R600 documentation suggest that this should be a number of pages */
0560 #define R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR     0x000112
0561 #define R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR    0x000114
0562 #define R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR   0x00011C
0563 #define R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR      0x00012C
0564 #define R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR     0x00013C
0565 #define R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR       0x00014C
0566 #define R_00016C_MC_PT0_CLIENT0_CNTL                 0x00016C
0567 #define   S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) & 0x1) << 0)
0568 #define   G_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) >> 0) & 0x1)
0569 #define   C_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE    0xFFFFFFFE
0570 #define   S_00016C_TRANSLATION_MODE_OVERRIDE(x)        (((x) & 0x1) << 1)
0571 #define   G_00016C_TRANSLATION_MODE_OVERRIDE(x)        (((x) >> 1) & 0x1)
0572 #define   C_00016C_TRANSLATION_MODE_OVERRIDE           0xFFFFFFFD
0573 #define   S_00016C_SYSTEM_ACCESS_MODE_MASK(x)          (((x) & 0x3) << 8)
0574 #define   G_00016C_SYSTEM_ACCESS_MODE_MASK(x)          (((x) >> 8) & 0x3)
0575 #define   C_00016C_SYSTEM_ACCESS_MODE_MASK             0xFFFFFCFF
0576 #define   V_00016C_SYSTEM_ACCESS_MODE_PA_ONLY          0
0577 #define   V_00016C_SYSTEM_ACCESS_MODE_USE_SYS_MAP      1
0578 #define   V_00016C_SYSTEM_ACCESS_MODE_IN_SYS           2
0579 #define   V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS       3
0580 #define   S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x)  (((x) & 0x1) << 10)
0581 #define   G_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x)  (((x) >> 10) & 0x1)
0582 #define   C_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS     0xFFFFFBFF
0583 #define   V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH  0
0584 #define   V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE 1
0585 #define   S_00016C_EFFECTIVE_L1_CACHE_SIZE(x)          (((x) & 0x7) << 11)
0586 #define   G_00016C_EFFECTIVE_L1_CACHE_SIZE(x)          (((x) >> 11) & 0x7)
0587 #define   C_00016C_EFFECTIVE_L1_CACHE_SIZE             0xFFFFC7FF
0588 #define   S_00016C_ENABLE_FRAGMENT_PROCESSING(x)       (((x) & 0x1) << 14)
0589 #define   G_00016C_ENABLE_FRAGMENT_PROCESSING(x)       (((x) >> 14) & 0x1)
0590 #define   C_00016C_ENABLE_FRAGMENT_PROCESSING          0xFFFFBFFF
0591 #define   S_00016C_EFFECTIVE_L1_QUEUE_SIZE(x)          (((x) & 0x7) << 15)
0592 #define   G_00016C_EFFECTIVE_L1_QUEUE_SIZE(x)          (((x) >> 15) & 0x7)
0593 #define   C_00016C_EFFECTIVE_L1_QUEUE_SIZE             0xFFFC7FFF
0594 #define   S_00016C_INVALIDATE_L1_TLB(x)                (((x) & 0x1) << 20)
0595 #define   G_00016C_INVALIDATE_L1_TLB(x)                (((x) >> 20) & 0x1)
0596 #define   C_00016C_INVALIDATE_L1_TLB                   0xFFEFFFFF
0597 
0598 #define R_006548_D1MODE_PRIORITY_A_CNT               0x006548
0599 #define   S_006548_D1MODE_PRIORITY_MARK_A(x)           (((x) & 0x7FFF) << 0)
0600 #define   G_006548_D1MODE_PRIORITY_MARK_A(x)           (((x) >> 0) & 0x7FFF)
0601 #define   C_006548_D1MODE_PRIORITY_MARK_A              0xFFFF8000
0602 #define   S_006548_D1MODE_PRIORITY_A_OFF(x)            (((x) & 0x1) << 16)
0603 #define   G_006548_D1MODE_PRIORITY_A_OFF(x)            (((x) >> 16) & 0x1)
0604 #define   C_006548_D1MODE_PRIORITY_A_OFF               0xFFFEFFFF
0605 #define   S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x)      (((x) & 0x1) << 20)
0606 #define   G_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x)      (((x) >> 20) & 0x1)
0607 #define   C_006548_D1MODE_PRIORITY_A_ALWAYS_ON         0xFFEFFFFF
0608 #define   S_006548_D1MODE_PRIORITY_A_FORCE_MASK(x)     (((x) & 0x1) << 24)
0609 #define   G_006548_D1MODE_PRIORITY_A_FORCE_MASK(x)     (((x) >> 24) & 0x1)
0610 #define   C_006548_D1MODE_PRIORITY_A_FORCE_MASK        0xFEFFFFFF
0611 #define R_00654C_D1MODE_PRIORITY_B_CNT               0x00654C
0612 #define   S_00654C_D1MODE_PRIORITY_MARK_B(x)           (((x) & 0x7FFF) << 0)
0613 #define   G_00654C_D1MODE_PRIORITY_MARK_B(x)           (((x) >> 0) & 0x7FFF)
0614 #define   C_00654C_D1MODE_PRIORITY_MARK_B              0xFFFF8000
0615 #define   S_00654C_D1MODE_PRIORITY_B_OFF(x)            (((x) & 0x1) << 16)
0616 #define   G_00654C_D1MODE_PRIORITY_B_OFF(x)            (((x) >> 16) & 0x1)
0617 #define   C_00654C_D1MODE_PRIORITY_B_OFF               0xFFFEFFFF
0618 #define   S_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x)      (((x) & 0x1) << 20)
0619 #define   G_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x)      (((x) >> 20) & 0x1)
0620 #define   C_00654C_D1MODE_PRIORITY_B_ALWAYS_ON         0xFFEFFFFF
0621 #define   S_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x)     (((x) & 0x1) << 24)
0622 #define   G_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x)     (((x) >> 24) & 0x1)
0623 #define   C_00654C_D1MODE_PRIORITY_B_FORCE_MASK        0xFEFFFFFF
0624 #define R_006D48_D2MODE_PRIORITY_A_CNT               0x006D48
0625 #define   S_006D48_D2MODE_PRIORITY_MARK_A(x)           (((x) & 0x7FFF) << 0)
0626 #define   G_006D48_D2MODE_PRIORITY_MARK_A(x)           (((x) >> 0) & 0x7FFF)
0627 #define   C_006D48_D2MODE_PRIORITY_MARK_A              0xFFFF8000
0628 #define   S_006D48_D2MODE_PRIORITY_A_OFF(x)            (((x) & 0x1) << 16)
0629 #define   G_006D48_D2MODE_PRIORITY_A_OFF(x)            (((x) >> 16) & 0x1)
0630 #define   C_006D48_D2MODE_PRIORITY_A_OFF               0xFFFEFFFF
0631 #define   S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x)      (((x) & 0x1) << 20)
0632 #define   G_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x)      (((x) >> 20) & 0x1)
0633 #define   C_006D48_D2MODE_PRIORITY_A_ALWAYS_ON         0xFFEFFFFF
0634 #define   S_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x)     (((x) & 0x1) << 24)
0635 #define   G_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x)     (((x) >> 24) & 0x1)
0636 #define   C_006D48_D2MODE_PRIORITY_A_FORCE_MASK        0xFEFFFFFF
0637 #define R_006D4C_D2MODE_PRIORITY_B_CNT               0x006D4C
0638 #define   S_006D4C_D2MODE_PRIORITY_MARK_B(x)           (((x) & 0x7FFF) << 0)
0639 #define   G_006D4C_D2MODE_PRIORITY_MARK_B(x)           (((x) >> 0) & 0x7FFF)
0640 #define   C_006D4C_D2MODE_PRIORITY_MARK_B              0xFFFF8000
0641 #define   S_006D4C_D2MODE_PRIORITY_B_OFF(x)            (((x) & 0x1) << 16)
0642 #define   G_006D4C_D2MODE_PRIORITY_B_OFF(x)            (((x) >> 16) & 0x1)
0643 #define   C_006D4C_D2MODE_PRIORITY_B_OFF               0xFFFEFFFF
0644 #define   S_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x)      (((x) & 0x1) << 20)
0645 #define   G_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x)      (((x) >> 20) & 0x1)
0646 #define   C_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON         0xFFEFFFFF
0647 #define   S_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x)     (((x) & 0x1) << 24)
0648 #define   G_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x)     (((x) >> 24) & 0x1)
0649 #define   C_006D4C_D2MODE_PRIORITY_B_FORCE_MASK        0xFEFFFFFF
0650 
0651 /* PLL regs */
0652 #define GENERAL_PWRMGT                                 0x8
0653 #define   GLOBAL_PWRMGT_EN                             (1 << 0)
0654 #define   MOBILE_SU                                    (1 << 2)
0655 #define DYN_PWRMGT_SCLK_LENGTH                         0xc
0656 #define   NORMAL_POWER_SCLK_HILEN(x)                   ((x) << 0)
0657 #define   NORMAL_POWER_SCLK_LOLEN(x)                   ((x) << 4)
0658 #define   REDUCED_POWER_SCLK_HILEN(x)                  ((x) << 8)
0659 #define   REDUCED_POWER_SCLK_LOLEN(x)                  ((x) << 12)
0660 #define   POWER_D1_SCLK_HILEN(x)                       ((x) << 16)
0661 #define   POWER_D1_SCLK_LOLEN(x)                       ((x) << 20)
0662 #define   STATIC_SCREEN_HILEN(x)                       ((x) << 24)
0663 #define   STATIC_SCREEN_LOLEN(x)                       ((x) << 28)
0664 #define DYN_SCLK_VOL_CNTL                              0xe
0665 #define   IO_CG_VOLTAGE_DROP                           (1 << 0)
0666 #define   VOLTAGE_DROP_SYNC                            (1 << 2)
0667 #define   VOLTAGE_DELAY_SEL(x)                         ((x) << 3)
0668 #define HDP_DYN_CNTL                                   0x10
0669 #define   HDP_FORCEON                                  (1 << 0)
0670 #define MC_HOST_DYN_CNTL                               0x1e
0671 #define   MC_HOST_FORCEON                              (1 << 0)
0672 #define DYN_BACKBIAS_CNTL                              0x29
0673 #define   IO_CG_BACKBIAS_EN                            (1 << 0)
0674 
0675 /* mmreg */
0676 #define DOUT_POWER_MANAGEMENT_CNTL                     0x7ee0
0677 #define   PWRDN_WAIT_BUSY_OFF                          (1 << 0)
0678 #define   PWRDN_WAIT_PWRSEQ_OFF                        (1 << 4)
0679 #define   PWRDN_WAIT_PPLL_OFF                          (1 << 8)
0680 #define   PWRUP_WAIT_PPLL_ON                           (1 << 12)
0681 #define   PWRUP_WAIT_MEM_INIT_DONE                     (1 << 16)
0682 #define   PM_ASSERT_RESET                              (1 << 20)
0683 #define   PM_PWRDN_PPLL                                (1 << 24)
0684 
0685 #endif
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!