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0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  * Copyright 2009 Jerome Glisse.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors: Dave Airlie
0025  *          Alex Deucher
0026  *          Jerome Glisse
0027  */
0028 /* RS600 / Radeon X1250/X1270 integrated GPU
0029  *
0030  * This file gather function specific to RS600 which is the IGP of
0031  * the X1250/X1270 family supporting intel CPU (while RS690/RS740
0032  * is the X1250/X1270 supporting AMD CPU). The display engine are
0033  * the avivo one, bios is an atombios, 3D block are the one of the
0034  * R4XX family. The GART is different from the RS400 one and is very
0035  * close to the one of the R600 family (R600 likely being an evolution
0036  * of the RS600 GART block).
0037  */
0038 
0039 #include <linux/io-64-nonatomic-lo-hi.h>
0040 #include <linux/pci.h>
0041 
0042 #include <drm/drm_device.h>
0043 #include <drm/drm_vblank.h>
0044 #include <drm/drm_fourcc.h>
0045 #include <drm/drm_framebuffer.h>
0046 
0047 #include "atom.h"
0048 #include "radeon.h"
0049 #include "radeon_asic.h"
0050 #include "radeon_audio.h"
0051 #include "rs600_reg_safe.h"
0052 #include "rs600d.h"
0053 
0054 static void rs600_gpu_init(struct radeon_device *rdev);
0055 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
0056 
0057 static const u32 crtc_offsets[2] =
0058 {
0059     0,
0060     AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
0061 };
0062 
0063 static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
0064 {
0065     if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
0066         return true;
0067     else
0068         return false;
0069 }
0070 
0071 static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
0072 {
0073     u32 pos1, pos2;
0074 
0075     pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
0076     pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
0077 
0078     if (pos1 != pos2)
0079         return true;
0080     else
0081         return false;
0082 }
0083 
0084 /**
0085  * avivo_wait_for_vblank - vblank wait asic callback.
0086  *
0087  * @rdev: radeon_device pointer
0088  * @crtc: crtc to wait for vblank on
0089  *
0090  * Wait for vblank on the requested crtc (r5xx-r7xx).
0091  */
0092 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
0093 {
0094     unsigned i = 0;
0095 
0096     if (crtc >= rdev->num_crtc)
0097         return;
0098 
0099     if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
0100         return;
0101 
0102     /* depending on when we hit vblank, we may be close to active; if so,
0103      * wait for another frame.
0104      */
0105     while (avivo_is_in_vblank(rdev, crtc)) {
0106         if (i++ % 100 == 0) {
0107             if (!avivo_is_counter_moving(rdev, crtc))
0108                 break;
0109         }
0110     }
0111 
0112     while (!avivo_is_in_vblank(rdev, crtc)) {
0113         if (i++ % 100 == 0) {
0114             if (!avivo_is_counter_moving(rdev, crtc))
0115                 break;
0116         }
0117     }
0118 }
0119 
0120 void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
0121 {
0122     struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
0123     struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;
0124     u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
0125     int i;
0126 
0127     /* Lock the graphics update lock */
0128     tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
0129     WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
0130 
0131     /* flip at hsync for async, default is vsync */
0132     WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,
0133            async ? AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0);
0134     /* update pitch */
0135     WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
0136            fb->pitches[0] / fb->format->cpp[0]);
0137     /* update the scanout addresses */
0138     WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
0139            (u32)crtc_base);
0140     WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
0141            (u32)crtc_base);
0142 
0143     /* Wait for update_pending to go high. */
0144     for (i = 0; i < rdev->usec_timeout; i++) {
0145         if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
0146             break;
0147         udelay(1);
0148     }
0149     DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
0150 
0151     /* Unlock the lock, so double-buffering can take place inside vblank */
0152     tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
0153     WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
0154 }
0155 
0156 bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc_id)
0157 {
0158     struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
0159 
0160     /* Return current update_pending status: */
0161     return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
0162         AVIVO_D1GRPH_SURFACE_UPDATE_PENDING);
0163 }
0164 
0165 void avivo_program_fmt(struct drm_encoder *encoder)
0166 {
0167     struct drm_device *dev = encoder->dev;
0168     struct radeon_device *rdev = dev->dev_private;
0169     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0170     struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
0171     int bpc = 0;
0172     u32 tmp = 0;
0173     enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
0174 
0175     if (connector) {
0176         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
0177         bpc = radeon_get_monitor_bpc(connector);
0178         dither = radeon_connector->dither;
0179     }
0180 
0181     /* LVDS FMT is set up by atom */
0182     if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
0183         return;
0184 
0185     if (bpc == 0)
0186         return;
0187 
0188     switch (bpc) {
0189     case 6:
0190         if (dither == RADEON_FMT_DITHER_ENABLE)
0191             /* XXX sort out optimal dither settings */
0192             tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
0193         else
0194             tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN;
0195         break;
0196     case 8:
0197         if (dither == RADEON_FMT_DITHER_ENABLE)
0198             /* XXX sort out optimal dither settings */
0199             tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN |
0200                 AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH);
0201         else
0202             tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN |
0203                 AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH);
0204         break;
0205     case 10:
0206     default:
0207         /* not needed */
0208         break;
0209     }
0210 
0211     switch (radeon_encoder->encoder_id) {
0212     case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
0213         WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp);
0214         break;
0215     case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
0216         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp);
0217         break;
0218     case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
0219         WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp);
0220         break;
0221     case ENCODER_OBJECT_ID_INTERNAL_DDI:
0222         WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp);
0223         break;
0224     default:
0225         break;
0226     }
0227 }
0228 
0229 void rs600_pm_misc(struct radeon_device *rdev)
0230 {
0231     int requested_index = rdev->pm.requested_power_state_index;
0232     struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
0233     struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
0234     u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
0235     u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
0236 
0237     if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
0238         if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
0239             tmp = RREG32(voltage->gpio.reg);
0240             if (voltage->active_high)
0241                 tmp |= voltage->gpio.mask;
0242             else
0243                 tmp &= ~(voltage->gpio.mask);
0244             WREG32(voltage->gpio.reg, tmp);
0245             if (voltage->delay)
0246                 udelay(voltage->delay);
0247         } else {
0248             tmp = RREG32(voltage->gpio.reg);
0249             if (voltage->active_high)
0250                 tmp &= ~voltage->gpio.mask;
0251             else
0252                 tmp |= voltage->gpio.mask;
0253             WREG32(voltage->gpio.reg, tmp);
0254             if (voltage->delay)
0255                 udelay(voltage->delay);
0256         }
0257     } else if (voltage->type == VOLTAGE_VDDC)
0258         radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
0259 
0260     dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
0261     dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
0262     dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
0263     if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
0264         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
0265             dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
0266             dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
0267         } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
0268             dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
0269             dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
0270         }
0271     } else {
0272         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
0273         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
0274     }
0275     WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
0276 
0277     dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
0278     if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
0279         dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
0280         if (voltage->delay) {
0281             dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
0282             dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
0283         } else
0284             dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
0285     } else
0286         dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
0287     WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
0288 
0289     hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
0290     if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
0291         hdp_dyn_cntl &= ~HDP_FORCEON;
0292     else
0293         hdp_dyn_cntl |= HDP_FORCEON;
0294     WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
0295 #if 0
0296     /* mc_host_dyn seems to cause hangs from time to time */
0297     mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
0298     if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
0299         mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
0300     else
0301         mc_host_dyn_cntl |= MC_HOST_FORCEON;
0302     WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
0303 #endif
0304     dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
0305     if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
0306         dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
0307     else
0308         dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
0309     WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
0310 
0311     /* set pcie lanes */
0312     if ((rdev->flags & RADEON_IS_PCIE) &&
0313         !(rdev->flags & RADEON_IS_IGP) &&
0314         rdev->asic->pm.set_pcie_lanes &&
0315         (ps->pcie_lanes !=
0316          rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
0317         radeon_set_pcie_lanes(rdev,
0318                       ps->pcie_lanes);
0319         DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
0320     }
0321 }
0322 
0323 void rs600_pm_prepare(struct radeon_device *rdev)
0324 {
0325     struct drm_device *ddev = rdev->ddev;
0326     struct drm_crtc *crtc;
0327     struct radeon_crtc *radeon_crtc;
0328     u32 tmp;
0329 
0330     /* disable any active CRTCs */
0331     list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
0332         radeon_crtc = to_radeon_crtc(crtc);
0333         if (radeon_crtc->enabled) {
0334             tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
0335             tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
0336             WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
0337         }
0338     }
0339 }
0340 
0341 void rs600_pm_finish(struct radeon_device *rdev)
0342 {
0343     struct drm_device *ddev = rdev->ddev;
0344     struct drm_crtc *crtc;
0345     struct radeon_crtc *radeon_crtc;
0346     u32 tmp;
0347 
0348     /* enable any active CRTCs */
0349     list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
0350         radeon_crtc = to_radeon_crtc(crtc);
0351         if (radeon_crtc->enabled) {
0352             tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
0353             tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
0354             WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
0355         }
0356     }
0357 }
0358 
0359 /* hpd for digital panel detect/disconnect */
0360 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
0361 {
0362     u32 tmp;
0363     bool connected = false;
0364 
0365     switch (hpd) {
0366     case RADEON_HPD_1:
0367         tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
0368         if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
0369             connected = true;
0370         break;
0371     case RADEON_HPD_2:
0372         tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
0373         if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
0374             connected = true;
0375         break;
0376     default:
0377         break;
0378     }
0379     return connected;
0380 }
0381 
0382 void rs600_hpd_set_polarity(struct radeon_device *rdev,
0383                 enum radeon_hpd_id hpd)
0384 {
0385     u32 tmp;
0386     bool connected = rs600_hpd_sense(rdev, hpd);
0387 
0388     switch (hpd) {
0389     case RADEON_HPD_1:
0390         tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
0391         if (connected)
0392             tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
0393         else
0394             tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
0395         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
0396         break;
0397     case RADEON_HPD_2:
0398         tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
0399         if (connected)
0400             tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
0401         else
0402             tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
0403         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
0404         break;
0405     default:
0406         break;
0407     }
0408 }
0409 
0410 void rs600_hpd_init(struct radeon_device *rdev)
0411 {
0412     struct drm_device *dev = rdev->ddev;
0413     struct drm_connector *connector;
0414     unsigned enable = 0;
0415 
0416     list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
0417         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
0418         switch (radeon_connector->hpd.hpd) {
0419         case RADEON_HPD_1:
0420             WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
0421                    S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
0422             break;
0423         case RADEON_HPD_2:
0424             WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
0425                    S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
0426             break;
0427         default:
0428             break;
0429         }
0430         if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
0431             enable |= 1 << radeon_connector->hpd.hpd;
0432         radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
0433     }
0434     radeon_irq_kms_enable_hpd(rdev, enable);
0435 }
0436 
0437 void rs600_hpd_fini(struct radeon_device *rdev)
0438 {
0439     struct drm_device *dev = rdev->ddev;
0440     struct drm_connector *connector;
0441     unsigned disable = 0;
0442 
0443     list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
0444         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
0445         switch (radeon_connector->hpd.hpd) {
0446         case RADEON_HPD_1:
0447             WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
0448                    S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
0449             break;
0450         case RADEON_HPD_2:
0451             WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
0452                    S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
0453             break;
0454         default:
0455             break;
0456         }
0457         if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
0458             disable |= 1 << radeon_connector->hpd.hpd;
0459     }
0460     radeon_irq_kms_disable_hpd(rdev, disable);
0461 }
0462 
0463 int rs600_asic_reset(struct radeon_device *rdev, bool hard)
0464 {
0465     struct rv515_mc_save save;
0466     u32 status, tmp;
0467     int ret = 0;
0468 
0469     status = RREG32(R_000E40_RBBM_STATUS);
0470     if (!G_000E40_GUI_ACTIVE(status)) {
0471         return 0;
0472     }
0473     /* Stops all mc clients */
0474     rv515_mc_stop(rdev, &save);
0475     status = RREG32(R_000E40_RBBM_STATUS);
0476     dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
0477     /* stop CP */
0478     WREG32(RADEON_CP_CSQ_CNTL, 0);
0479     tmp = RREG32(RADEON_CP_RB_CNTL);
0480     WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
0481     WREG32(RADEON_CP_RB_RPTR_WR, 0);
0482     WREG32(RADEON_CP_RB_WPTR, 0);
0483     WREG32(RADEON_CP_RB_CNTL, tmp);
0484     pci_save_state(rdev->pdev);
0485     /* disable bus mastering */
0486     pci_clear_master(rdev->pdev);
0487     mdelay(1);
0488     /* reset GA+VAP */
0489     WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
0490                     S_0000F0_SOFT_RESET_GA(1));
0491     RREG32(R_0000F0_RBBM_SOFT_RESET);
0492     mdelay(500);
0493     WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
0494     mdelay(1);
0495     status = RREG32(R_000E40_RBBM_STATUS);
0496     dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
0497     /* reset CP */
0498     WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
0499     RREG32(R_0000F0_RBBM_SOFT_RESET);
0500     mdelay(500);
0501     WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
0502     mdelay(1);
0503     status = RREG32(R_000E40_RBBM_STATUS);
0504     dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
0505     /* reset MC */
0506     WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
0507     RREG32(R_0000F0_RBBM_SOFT_RESET);
0508     mdelay(500);
0509     WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
0510     mdelay(1);
0511     status = RREG32(R_000E40_RBBM_STATUS);
0512     dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
0513     /* restore PCI & busmastering */
0514     pci_restore_state(rdev->pdev);
0515     /* Check if GPU is idle */
0516     if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
0517         dev_err(rdev->dev, "failed to reset GPU\n");
0518         ret = -1;
0519     } else
0520         dev_info(rdev->dev, "GPU reset succeed\n");
0521     rv515_mc_resume(rdev, &save);
0522     return ret;
0523 }
0524 
0525 /*
0526  * GART.
0527  */
0528 void rs600_gart_tlb_flush(struct radeon_device *rdev)
0529 {
0530     uint32_t tmp;
0531 
0532     tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
0533     tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
0534     WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
0535 
0536     tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
0537     tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
0538     WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
0539 
0540     tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
0541     tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
0542     WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
0543     tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
0544 }
0545 
0546 static int rs600_gart_init(struct radeon_device *rdev)
0547 {
0548     int r;
0549 
0550     if (rdev->gart.robj) {
0551         WARN(1, "RS600 GART already initialized\n");
0552         return 0;
0553     }
0554     /* Initialize common gart structure */
0555     r = radeon_gart_init(rdev);
0556     if (r) {
0557         return r;
0558     }
0559     rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
0560     return radeon_gart_table_vram_alloc(rdev);
0561 }
0562 
0563 static int rs600_gart_enable(struct radeon_device *rdev)
0564 {
0565     u32 tmp;
0566     int r, i;
0567 
0568     if (rdev->gart.robj == NULL) {
0569         dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
0570         return -EINVAL;
0571     }
0572     r = radeon_gart_table_vram_pin(rdev);
0573     if (r)
0574         return r;
0575     /* Enable bus master */
0576     tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
0577     WREG32(RADEON_BUS_CNTL, tmp);
0578     /* FIXME: setup default page */
0579     WREG32_MC(R_000100_MC_PT0_CNTL,
0580           (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
0581            S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
0582 
0583     for (i = 0; i < 19; i++) {
0584         WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
0585               S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
0586               S_00016C_SYSTEM_ACCESS_MODE_MASK(
0587                   V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
0588               S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
0589                   V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
0590               S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
0591               S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
0592               S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
0593     }
0594     /* enable first context */
0595     WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
0596           S_000102_ENABLE_PAGE_TABLE(1) |
0597           S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
0598 
0599     /* disable all other contexts */
0600     for (i = 1; i < 8; i++)
0601         WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
0602 
0603     /* setup the page table */
0604     WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
0605           rdev->gart.table_addr);
0606     WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
0607     WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
0608     WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
0609 
0610     /* System context maps to VRAM space */
0611     WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
0612     WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
0613 
0614     /* enable page tables */
0615     tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
0616     WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
0617     tmp = RREG32_MC(R_000009_MC_CNTL1);
0618     WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
0619     rs600_gart_tlb_flush(rdev);
0620     DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
0621          (unsigned)(rdev->mc.gtt_size >> 20),
0622          (unsigned long long)rdev->gart.table_addr);
0623     rdev->gart.ready = true;
0624     return 0;
0625 }
0626 
0627 static void rs600_gart_disable(struct radeon_device *rdev)
0628 {
0629     u32 tmp;
0630 
0631     /* FIXME: disable out of gart access */
0632     WREG32_MC(R_000100_MC_PT0_CNTL, 0);
0633     tmp = RREG32_MC(R_000009_MC_CNTL1);
0634     WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
0635     radeon_gart_table_vram_unpin(rdev);
0636 }
0637 
0638 static void rs600_gart_fini(struct radeon_device *rdev)
0639 {
0640     radeon_gart_fini(rdev);
0641     rs600_gart_disable(rdev);
0642     radeon_gart_table_vram_free(rdev);
0643 }
0644 
0645 uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags)
0646 {
0647     addr = addr & 0xFFFFFFFFFFFFF000ULL;
0648     addr |= R600_PTE_SYSTEM;
0649     if (flags & RADEON_GART_PAGE_VALID)
0650         addr |= R600_PTE_VALID;
0651     if (flags & RADEON_GART_PAGE_READ)
0652         addr |= R600_PTE_READABLE;
0653     if (flags & RADEON_GART_PAGE_WRITE)
0654         addr |= R600_PTE_WRITEABLE;
0655     if (flags & RADEON_GART_PAGE_SNOOP)
0656         addr |= R600_PTE_SNOOPED;
0657     return addr;
0658 }
0659 
0660 void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
0661              uint64_t entry)
0662 {
0663     void __iomem *ptr = (void *)rdev->gart.ptr;
0664     writeq(entry, ptr + (i * 8));
0665 }
0666 
0667 int rs600_irq_set(struct radeon_device *rdev)
0668 {
0669     uint32_t tmp = 0;
0670     uint32_t mode_int = 0;
0671     u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
0672         ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
0673     u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
0674         ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
0675     u32 hdmi0;
0676     if (ASIC_IS_DCE2(rdev))
0677         hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
0678             ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
0679     else
0680         hdmi0 = 0;
0681 
0682     if (!rdev->irq.installed) {
0683         WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
0684         WREG32(R_000040_GEN_INT_CNTL, 0);
0685         return -EINVAL;
0686     }
0687     if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
0688         tmp |= S_000040_SW_INT_EN(1);
0689     }
0690     if (rdev->irq.crtc_vblank_int[0] ||
0691         atomic_read(&rdev->irq.pflip[0])) {
0692         mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
0693     }
0694     if (rdev->irq.crtc_vblank_int[1] ||
0695         atomic_read(&rdev->irq.pflip[1])) {
0696         mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
0697     }
0698     if (rdev->irq.hpd[0]) {
0699         hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
0700     }
0701     if (rdev->irq.hpd[1]) {
0702         hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
0703     }
0704     if (rdev->irq.afmt[0]) {
0705         hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
0706     }
0707     WREG32(R_000040_GEN_INT_CNTL, tmp);
0708     WREG32(R_006540_DxMODE_INT_MASK, mode_int);
0709     WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
0710     WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
0711     if (ASIC_IS_DCE2(rdev))
0712         WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
0713 
0714     /* posting read */
0715     RREG32(R_000040_GEN_INT_CNTL);
0716 
0717     return 0;
0718 }
0719 
0720 static inline u32 rs600_irq_ack(struct radeon_device *rdev)
0721 {
0722     uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
0723     uint32_t irq_mask = S_000044_SW_INT(1);
0724     u32 tmp;
0725 
0726     if (G_000044_DISPLAY_INT_STAT(irqs)) {
0727         rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
0728         if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
0729             WREG32(R_006534_D1MODE_VBLANK_STATUS,
0730                 S_006534_D1MODE_VBLANK_ACK(1));
0731         }
0732         if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
0733             WREG32(R_006D34_D2MODE_VBLANK_STATUS,
0734                 S_006D34_D2MODE_VBLANK_ACK(1));
0735         }
0736         if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
0737             tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
0738             tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
0739             WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
0740         }
0741         if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
0742             tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
0743             tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
0744             WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
0745         }
0746     } else {
0747         rdev->irq.stat_regs.r500.disp_int = 0;
0748     }
0749 
0750     if (ASIC_IS_DCE2(rdev)) {
0751         rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
0752             S_007404_HDMI0_AZ_FORMAT_WTRIG(1);
0753         if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
0754             tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
0755             tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
0756             WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
0757         }
0758     } else
0759         rdev->irq.stat_regs.r500.hdmi0_status = 0;
0760 
0761     if (irqs) {
0762         WREG32(R_000044_GEN_INT_STATUS, irqs);
0763     }
0764     return irqs & irq_mask;
0765 }
0766 
0767 void rs600_irq_disable(struct radeon_device *rdev)
0768 {
0769     u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
0770         ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
0771     WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
0772     WREG32(R_000040_GEN_INT_CNTL, 0);
0773     WREG32(R_006540_DxMODE_INT_MASK, 0);
0774     /* Wait and acknowledge irq */
0775     mdelay(1);
0776     rs600_irq_ack(rdev);
0777 }
0778 
0779 int rs600_irq_process(struct radeon_device *rdev)
0780 {
0781     u32 status, msi_rearm;
0782     bool queue_hotplug = false;
0783     bool queue_hdmi = false;
0784 
0785     status = rs600_irq_ack(rdev);
0786     if (!status &&
0787         !rdev->irq.stat_regs.r500.disp_int &&
0788         !rdev->irq.stat_regs.r500.hdmi0_status) {
0789         return IRQ_NONE;
0790     }
0791     while (status ||
0792            rdev->irq.stat_regs.r500.disp_int ||
0793            rdev->irq.stat_regs.r500.hdmi0_status) {
0794         /* SW interrupt */
0795         if (G_000044_SW_INT(status)) {
0796             radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
0797         }
0798         /* Vertical blank interrupts */
0799         if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
0800             if (rdev->irq.crtc_vblank_int[0]) {
0801                 drm_handle_vblank(rdev->ddev, 0);
0802                 rdev->pm.vblank_sync = true;
0803                 wake_up(&rdev->irq.vblank_queue);
0804             }
0805             if (atomic_read(&rdev->irq.pflip[0]))
0806                 radeon_crtc_handle_vblank(rdev, 0);
0807         }
0808         if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
0809             if (rdev->irq.crtc_vblank_int[1]) {
0810                 drm_handle_vblank(rdev->ddev, 1);
0811                 rdev->pm.vblank_sync = true;
0812                 wake_up(&rdev->irq.vblank_queue);
0813             }
0814             if (atomic_read(&rdev->irq.pflip[1]))
0815                 radeon_crtc_handle_vblank(rdev, 1);
0816         }
0817         if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
0818             queue_hotplug = true;
0819             DRM_DEBUG("HPD1\n");
0820         }
0821         if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
0822             queue_hotplug = true;
0823             DRM_DEBUG("HPD2\n");
0824         }
0825         if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
0826             queue_hdmi = true;
0827             DRM_DEBUG("HDMI0\n");
0828         }
0829         status = rs600_irq_ack(rdev);
0830     }
0831     if (queue_hotplug)
0832         schedule_delayed_work(&rdev->hotplug_work, 0);
0833     if (queue_hdmi)
0834         schedule_work(&rdev->audio_work);
0835     if (rdev->msi_enabled) {
0836         switch (rdev->family) {
0837         case CHIP_RS600:
0838         case CHIP_RS690:
0839         case CHIP_RS740:
0840             msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
0841             WREG32(RADEON_BUS_CNTL, msi_rearm);
0842             WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
0843             break;
0844         default:
0845             WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
0846             break;
0847         }
0848     }
0849     return IRQ_HANDLED;
0850 }
0851 
0852 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
0853 {
0854     if (crtc == 0)
0855         return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
0856     else
0857         return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
0858 }
0859 
0860 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
0861 {
0862     unsigned i;
0863 
0864     for (i = 0; i < rdev->usec_timeout; i++) {
0865         if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
0866             return 0;
0867         udelay(1);
0868     }
0869     return -1;
0870 }
0871 
0872 static void rs600_gpu_init(struct radeon_device *rdev)
0873 {
0874     r420_pipes_init(rdev);
0875     /* Wait for mc idle */
0876     if (rs600_mc_wait_for_idle(rdev))
0877         dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
0878 }
0879 
0880 static void rs600_mc_init(struct radeon_device *rdev)
0881 {
0882     u64 base;
0883 
0884     rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
0885     rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
0886     rdev->mc.vram_is_ddr = true;
0887     rdev->mc.vram_width = 128;
0888     rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
0889     rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
0890     rdev->mc.visible_vram_size = rdev->mc.aper_size;
0891     rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
0892     base = RREG32_MC(R_000004_MC_FB_LOCATION);
0893     base = G_000004_MC_FB_START(base) << 16;
0894     radeon_vram_location(rdev, &rdev->mc, base);
0895     rdev->mc.gtt_base_align = 0;
0896     radeon_gtt_location(rdev, &rdev->mc);
0897     radeon_update_bandwidth_info(rdev);
0898 }
0899 
0900 void rs600_bandwidth_update(struct radeon_device *rdev)
0901 {
0902     struct drm_display_mode *mode0 = NULL;
0903     struct drm_display_mode *mode1 = NULL;
0904     u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
0905     /* FIXME: implement full support */
0906 
0907     if (!rdev->mode_info.mode_config_initialized)
0908         return;
0909 
0910     radeon_update_display_priority(rdev);
0911 
0912     if (rdev->mode_info.crtcs[0]->base.enabled)
0913         mode0 = &rdev->mode_info.crtcs[0]->base.mode;
0914     if (rdev->mode_info.crtcs[1]->base.enabled)
0915         mode1 = &rdev->mode_info.crtcs[1]->base.mode;
0916 
0917     rs690_line_buffer_adjust(rdev, mode0, mode1);
0918 
0919     if (rdev->disp_priority == 2) {
0920         d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
0921         d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
0922         d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
0923         d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
0924         WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
0925         WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
0926         WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
0927         WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
0928     }
0929 }
0930 
0931 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
0932 {
0933     unsigned long flags;
0934     u32 r;
0935 
0936     spin_lock_irqsave(&rdev->mc_idx_lock, flags);
0937     WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
0938         S_000070_MC_IND_CITF_ARB0(1));
0939     r = RREG32(R_000074_MC_IND_DATA);
0940     spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
0941     return r;
0942 }
0943 
0944 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
0945 {
0946     unsigned long flags;
0947 
0948     spin_lock_irqsave(&rdev->mc_idx_lock, flags);
0949     WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
0950         S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
0951     WREG32(R_000074_MC_IND_DATA, v);
0952     spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
0953 }
0954 
0955 void rs600_set_safe_registers(struct radeon_device *rdev)
0956 {
0957     rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
0958     rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
0959 }
0960 
0961 static void rs600_mc_program(struct radeon_device *rdev)
0962 {
0963     struct rv515_mc_save save;
0964 
0965     /* Stops all mc clients */
0966     rv515_mc_stop(rdev, &save);
0967 
0968     /* Wait for mc idle */
0969     if (rs600_mc_wait_for_idle(rdev))
0970         dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
0971 
0972     /* FIXME: What does AGP means for such chipset ? */
0973     WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
0974     WREG32_MC(R_000006_AGP_BASE, 0);
0975     WREG32_MC(R_000007_AGP_BASE_2, 0);
0976     /* Program MC */
0977     WREG32_MC(R_000004_MC_FB_LOCATION,
0978             S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
0979             S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
0980     WREG32(R_000134_HDP_FB_LOCATION,
0981         S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
0982 
0983     rv515_mc_resume(rdev, &save);
0984 }
0985 
0986 static int rs600_startup(struct radeon_device *rdev)
0987 {
0988     int r;
0989 
0990     rs600_mc_program(rdev);
0991     /* Resume clock */
0992     rv515_clock_startup(rdev);
0993     /* Initialize GPU configuration (# pipes, ...) */
0994     rs600_gpu_init(rdev);
0995     /* Initialize GART (initialize after TTM so we can allocate
0996      * memory through TTM but finalize after TTM) */
0997     r = rs600_gart_enable(rdev);
0998     if (r)
0999         return r;
1000 
1001     /* allocate wb buffer */
1002     r = radeon_wb_init(rdev);
1003     if (r)
1004         return r;
1005 
1006     r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1007     if (r) {
1008         dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1009         return r;
1010     }
1011 
1012     /* Enable IRQ */
1013     if (!rdev->irq.installed) {
1014         r = radeon_irq_kms_init(rdev);
1015         if (r)
1016             return r;
1017     }
1018 
1019     rs600_irq_set(rdev);
1020     rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1021     /* 1M ring buffer */
1022     r = r100_cp_init(rdev, 1024 * 1024);
1023     if (r) {
1024         dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1025         return r;
1026     }
1027 
1028     r = radeon_ib_pool_init(rdev);
1029     if (r) {
1030         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1031         return r;
1032     }
1033 
1034     r = radeon_audio_init(rdev);
1035     if (r) {
1036         dev_err(rdev->dev, "failed initializing audio\n");
1037         return r;
1038     }
1039 
1040     return 0;
1041 }
1042 
1043 int rs600_resume(struct radeon_device *rdev)
1044 {
1045     int r;
1046 
1047     /* Make sur GART are not working */
1048     rs600_gart_disable(rdev);
1049     /* Resume clock before doing reset */
1050     rv515_clock_startup(rdev);
1051     /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1052     if (radeon_asic_reset(rdev)) {
1053         dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1054             RREG32(R_000E40_RBBM_STATUS),
1055             RREG32(R_0007C0_CP_STAT));
1056     }
1057     /* post */
1058     atom_asic_init(rdev->mode_info.atom_context);
1059     /* Resume clock after posting */
1060     rv515_clock_startup(rdev);
1061     /* Initialize surface registers */
1062     radeon_surface_init(rdev);
1063 
1064     rdev->accel_working = true;
1065     r = rs600_startup(rdev);
1066     if (r) {
1067         rdev->accel_working = false;
1068     }
1069     return r;
1070 }
1071 
1072 int rs600_suspend(struct radeon_device *rdev)
1073 {
1074     radeon_pm_suspend(rdev);
1075     radeon_audio_fini(rdev);
1076     r100_cp_disable(rdev);
1077     radeon_wb_disable(rdev);
1078     rs600_irq_disable(rdev);
1079     rs600_gart_disable(rdev);
1080     return 0;
1081 }
1082 
1083 void rs600_fini(struct radeon_device *rdev)
1084 {
1085     radeon_pm_fini(rdev);
1086     radeon_audio_fini(rdev);
1087     r100_cp_fini(rdev);
1088     radeon_wb_fini(rdev);
1089     radeon_ib_pool_fini(rdev);
1090     radeon_gem_fini(rdev);
1091     rs600_gart_fini(rdev);
1092     radeon_irq_kms_fini(rdev);
1093     radeon_fence_driver_fini(rdev);
1094     radeon_bo_fini(rdev);
1095     radeon_atombios_fini(rdev);
1096     kfree(rdev->bios);
1097     rdev->bios = NULL;
1098 }
1099 
1100 int rs600_init(struct radeon_device *rdev)
1101 {
1102     int r;
1103 
1104     /* Disable VGA */
1105     rv515_vga_render_disable(rdev);
1106     /* Initialize scratch registers */
1107     radeon_scratch_init(rdev);
1108     /* Initialize surface registers */
1109     radeon_surface_init(rdev);
1110     /* restore some register to sane defaults */
1111     r100_restore_sanity(rdev);
1112     /* BIOS */
1113     if (!radeon_get_bios(rdev)) {
1114         if (ASIC_IS_AVIVO(rdev))
1115             return -EINVAL;
1116     }
1117     if (rdev->is_atom_bios) {
1118         r = radeon_atombios_init(rdev);
1119         if (r)
1120             return r;
1121     } else {
1122         dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
1123         return -EINVAL;
1124     }
1125     /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1126     if (radeon_asic_reset(rdev)) {
1127         dev_warn(rdev->dev,
1128             "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1129             RREG32(R_000E40_RBBM_STATUS),
1130             RREG32(R_0007C0_CP_STAT));
1131     }
1132     /* check if cards are posted or not */
1133     if (radeon_boot_test_post_card(rdev) == false)
1134         return -EINVAL;
1135 
1136     /* Initialize clocks */
1137     radeon_get_clock_info(rdev->ddev);
1138     /* initialize memory controller */
1139     rs600_mc_init(rdev);
1140     r100_debugfs_rbbm_init(rdev);
1141     /* Fence driver */
1142     radeon_fence_driver_init(rdev);
1143     /* Memory manager */
1144     r = radeon_bo_init(rdev);
1145     if (r)
1146         return r;
1147     r = rs600_gart_init(rdev);
1148     if (r)
1149         return r;
1150     rs600_set_safe_registers(rdev);
1151 
1152     /* Initialize power management */
1153     radeon_pm_init(rdev);
1154 
1155     rdev->accel_working = true;
1156     r = rs600_startup(rdev);
1157     if (r) {
1158         /* Somethings want wront with the accel init stop accel */
1159         dev_err(rdev->dev, "Disabling GPU acceleration\n");
1160         r100_cp_fini(rdev);
1161         radeon_wb_fini(rdev);
1162         radeon_ib_pool_fini(rdev);
1163         rs600_gart_fini(rdev);
1164         radeon_irq_kms_fini(rdev);
1165         rdev->accel_working = false;
1166     }
1167     return 0;
1168 }
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