Back to home page

OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  * Copyright 2009 Jerome Glisse.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors: Dave Airlie
0025  *          Alex Deucher
0026  *          Jerome Glisse
0027  */
0028 
0029 #include <linux/seq_file.h>
0030 #include <linux/slab.h>
0031 
0032 #include <drm/drm_device.h>
0033 #include <drm/drm_file.h>
0034 
0035 #include "radeon.h"
0036 #include "radeon_asic.h"
0037 #include "rs400d.h"
0038 
0039 /* This files gather functions specifics to : rs400,rs480 */
0040 static void rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
0041 
0042 void rs400_gart_adjust_size(struct radeon_device *rdev)
0043 {
0044     /* Check gart size */
0045     switch (rdev->mc.gtt_size/(1024*1024)) {
0046     case 32:
0047     case 64:
0048     case 128:
0049     case 256:
0050     case 512:
0051     case 1024:
0052     case 2048:
0053         break;
0054     default:
0055         DRM_ERROR("Unable to use IGP GART size %uM\n",
0056               (unsigned)(rdev->mc.gtt_size >> 20));
0057         DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
0058         DRM_ERROR("Forcing to 32M GART size\n");
0059         rdev->mc.gtt_size = 32 * 1024 * 1024;
0060         return;
0061     }
0062 }
0063 
0064 void rs400_gart_tlb_flush(struct radeon_device *rdev)
0065 {
0066     uint32_t tmp;
0067     unsigned int timeout = rdev->usec_timeout;
0068 
0069     WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
0070     do {
0071         tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
0072         if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
0073             break;
0074         udelay(1);
0075         timeout--;
0076     } while (timeout > 0);
0077     WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
0078 }
0079 
0080 int rs400_gart_init(struct radeon_device *rdev)
0081 {
0082     int r;
0083 
0084     if (rdev->gart.ptr) {
0085         WARN(1, "RS400 GART already initialized\n");
0086         return 0;
0087     }
0088     /* Check gart size */
0089     switch(rdev->mc.gtt_size / (1024 * 1024)) {
0090     case 32:
0091     case 64:
0092     case 128:
0093     case 256:
0094     case 512:
0095     case 1024:
0096     case 2048:
0097         break;
0098     default:
0099         return -EINVAL;
0100     }
0101     /* Initialize common gart structure */
0102     r = radeon_gart_init(rdev);
0103     if (r)
0104         return r;
0105     rs400_debugfs_pcie_gart_info_init(rdev);
0106     rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
0107     return radeon_gart_table_ram_alloc(rdev);
0108 }
0109 
0110 int rs400_gart_enable(struct radeon_device *rdev)
0111 {
0112     uint32_t size_reg;
0113     uint32_t tmp;
0114 
0115     tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
0116     tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
0117     WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
0118     /* Check gart size */
0119     switch(rdev->mc.gtt_size / (1024 * 1024)) {
0120     case 32:
0121         size_reg = RS480_VA_SIZE_32MB;
0122         break;
0123     case 64:
0124         size_reg = RS480_VA_SIZE_64MB;
0125         break;
0126     case 128:
0127         size_reg = RS480_VA_SIZE_128MB;
0128         break;
0129     case 256:
0130         size_reg = RS480_VA_SIZE_256MB;
0131         break;
0132     case 512:
0133         size_reg = RS480_VA_SIZE_512MB;
0134         break;
0135     case 1024:
0136         size_reg = RS480_VA_SIZE_1GB;
0137         break;
0138     case 2048:
0139         size_reg = RS480_VA_SIZE_2GB;
0140         break;
0141     default:
0142         return -EINVAL;
0143     }
0144     /* It should be fine to program it to max value */
0145     if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
0146         WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
0147         WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
0148     } else {
0149         WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
0150         WREG32(RS480_AGP_BASE_2, 0);
0151     }
0152     tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
0153     tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
0154     if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
0155         WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
0156         tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
0157         WREG32(RADEON_BUS_CNTL, tmp);
0158     } else {
0159         WREG32(RADEON_MC_AGP_LOCATION, tmp);
0160         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
0161         WREG32(RADEON_BUS_CNTL, tmp);
0162     }
0163     /* Table should be in 32bits address space so ignore bits above. */
0164     tmp = (u32)rdev->gart.table_addr & 0xfffff000;
0165     tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
0166 
0167     WREG32_MC(RS480_GART_BASE, tmp);
0168     /* TODO: more tweaking here */
0169     WREG32_MC(RS480_GART_FEATURE_ID,
0170           (RS480_TLB_ENABLE |
0171            RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
0172     /* Disable snooping */
0173     WREG32_MC(RS480_AGP_MODE_CNTL,
0174           (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
0175     /* Disable AGP mode */
0176     /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
0177      * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
0178     if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
0179         tmp = RREG32_MC(RS480_MC_MISC_CNTL);
0180         tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN;
0181         WREG32_MC(RS480_MC_MISC_CNTL, tmp);
0182     } else {
0183         tmp = RREG32_MC(RS480_MC_MISC_CNTL);
0184         tmp |= RS480_GART_INDEX_REG_EN;
0185         WREG32_MC(RS480_MC_MISC_CNTL, tmp);
0186     }
0187     /* Enable gart */
0188     WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
0189     rs400_gart_tlb_flush(rdev);
0190     DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
0191          (unsigned)(rdev->mc.gtt_size >> 20),
0192          (unsigned long long)rdev->gart.table_addr);
0193     rdev->gart.ready = true;
0194     return 0;
0195 }
0196 
0197 void rs400_gart_disable(struct radeon_device *rdev)
0198 {
0199     uint32_t tmp;
0200 
0201     tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
0202     tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
0203     WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
0204     WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
0205 }
0206 
0207 void rs400_gart_fini(struct radeon_device *rdev)
0208 {
0209     radeon_gart_fini(rdev);
0210     rs400_gart_disable(rdev);
0211     radeon_gart_table_ram_free(rdev);
0212 }
0213 
0214 #define RS400_PTE_UNSNOOPED (1 << 0)
0215 #define RS400_PTE_WRITEABLE (1 << 2)
0216 #define RS400_PTE_READABLE  (1 << 3)
0217 
0218 uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags)
0219 {
0220     uint32_t entry;
0221 
0222     entry = (lower_32_bits(addr) & PAGE_MASK) |
0223         ((upper_32_bits(addr) & 0xff) << 4);
0224     if (flags & RADEON_GART_PAGE_READ)
0225         entry |= RS400_PTE_READABLE;
0226     if (flags & RADEON_GART_PAGE_WRITE)
0227         entry |= RS400_PTE_WRITEABLE;
0228     if (!(flags & RADEON_GART_PAGE_SNOOP))
0229         entry |= RS400_PTE_UNSNOOPED;
0230     return entry;
0231 }
0232 
0233 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
0234              uint64_t entry)
0235 {
0236     u32 *gtt = rdev->gart.ptr;
0237     gtt[i] = cpu_to_le32(lower_32_bits(entry));
0238 }
0239 
0240 int rs400_mc_wait_for_idle(struct radeon_device *rdev)
0241 {
0242     unsigned i;
0243     uint32_t tmp;
0244 
0245     for (i = 0; i < rdev->usec_timeout; i++) {
0246         /* read MC_STATUS */
0247         tmp = RREG32(RADEON_MC_STATUS);
0248         if (tmp & RADEON_MC_IDLE) {
0249             return 0;
0250         }
0251         udelay(1);
0252     }
0253     return -1;
0254 }
0255 
0256 static void rs400_gpu_init(struct radeon_device *rdev)
0257 {
0258     /* FIXME: is this correct ? */
0259     r420_pipes_init(rdev);
0260     if (rs400_mc_wait_for_idle(rdev)) {
0261         pr_warn("rs400: Failed to wait MC idle while programming pipes. Bad things might happen. %08x\n",
0262             RREG32(RADEON_MC_STATUS));
0263     }
0264 }
0265 
0266 static void rs400_mc_init(struct radeon_device *rdev)
0267 {
0268     u64 base;
0269 
0270     rs400_gart_adjust_size(rdev);
0271     rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
0272     /* DDR for all card after R300 & IGP */
0273     rdev->mc.vram_is_ddr = true;
0274     rdev->mc.vram_width = 128;
0275     r100_vram_init_sizes(rdev);
0276     base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
0277     radeon_vram_location(rdev, &rdev->mc, base);
0278     rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
0279     radeon_gtt_location(rdev, &rdev->mc);
0280     radeon_update_bandwidth_info(rdev);
0281 }
0282 
0283 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
0284 {
0285     unsigned long flags;
0286     uint32_t r;
0287 
0288     spin_lock_irqsave(&rdev->mc_idx_lock, flags);
0289     WREG32(RS480_NB_MC_INDEX, reg & 0xff);
0290     r = RREG32(RS480_NB_MC_DATA);
0291     WREG32(RS480_NB_MC_INDEX, 0xff);
0292     spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
0293     return r;
0294 }
0295 
0296 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
0297 {
0298     unsigned long flags;
0299 
0300     spin_lock_irqsave(&rdev->mc_idx_lock, flags);
0301     WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
0302     WREG32(RS480_NB_MC_DATA, (v));
0303     WREG32(RS480_NB_MC_INDEX, 0xff);
0304     spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
0305 }
0306 
0307 #if defined(CONFIG_DEBUG_FS)
0308 static int rs400_debugfs_gart_info_show(struct seq_file *m, void *unused)
0309 {
0310     struct radeon_device *rdev = (struct radeon_device *)m->private;
0311     uint32_t tmp;
0312 
0313     tmp = RREG32(RADEON_HOST_PATH_CNTL);
0314     seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
0315     tmp = RREG32(RADEON_BUS_CNTL);
0316     seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
0317     tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
0318     seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
0319     if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
0320         tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
0321         seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
0322         tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
0323         seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
0324         tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
0325         seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
0326         tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
0327         seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
0328         tmp = RREG32(RS690_HDP_FB_LOCATION);
0329         seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
0330     } else {
0331         tmp = RREG32(RADEON_AGP_BASE);
0332         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
0333         tmp = RREG32(RS480_AGP_BASE_2);
0334         seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
0335         tmp = RREG32(RADEON_MC_AGP_LOCATION);
0336         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
0337     }
0338     tmp = RREG32_MC(RS480_GART_BASE);
0339     seq_printf(m, "GART_BASE 0x%08x\n", tmp);
0340     tmp = RREG32_MC(RS480_GART_FEATURE_ID);
0341     seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
0342     tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
0343     seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
0344     tmp = RREG32_MC(RS480_MC_MISC_CNTL);
0345     seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
0346     tmp = RREG32_MC(0x5F);
0347     seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
0348     tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
0349     seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
0350     tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
0351     seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
0352     tmp = RREG32_MC(0x3B);
0353     seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
0354     tmp = RREG32_MC(0x3C);
0355     seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
0356     tmp = RREG32_MC(0x30);
0357     seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
0358     tmp = RREG32_MC(0x31);
0359     seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
0360     tmp = RREG32_MC(0x32);
0361     seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
0362     tmp = RREG32_MC(0x33);
0363     seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
0364     tmp = RREG32_MC(0x34);
0365     seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
0366     tmp = RREG32_MC(0x35);
0367     seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
0368     tmp = RREG32_MC(0x36);
0369     seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
0370     tmp = RREG32_MC(0x37);
0371     seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
0372     return 0;
0373 }
0374 
0375 DEFINE_SHOW_ATTRIBUTE(rs400_debugfs_gart_info);
0376 #endif
0377 
0378 static void rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
0379 {
0380 #if defined(CONFIG_DEBUG_FS)
0381     struct dentry *root = rdev->ddev->primary->debugfs_root;
0382 
0383     debugfs_create_file("rs400_gart_info", 0444, root, rdev,
0384                 &rs400_debugfs_gart_info_fops);
0385 #endif
0386 }
0387 
0388 static void rs400_mc_program(struct radeon_device *rdev)
0389 {
0390     struct r100_mc_save save;
0391 
0392     /* Stops all mc clients */
0393     r100_mc_stop(rdev, &save);
0394 
0395     /* Wait for mc idle */
0396     if (rs400_mc_wait_for_idle(rdev))
0397         dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
0398     WREG32(R_000148_MC_FB_LOCATION,
0399         S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
0400         S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
0401 
0402     r100_mc_resume(rdev, &save);
0403 }
0404 
0405 static int rs400_startup(struct radeon_device *rdev)
0406 {
0407     int r;
0408 
0409     r100_set_common_regs(rdev);
0410 
0411     rs400_mc_program(rdev);
0412     /* Resume clock */
0413     r300_clock_startup(rdev);
0414     /* Initialize GPU configuration (# pipes, ...) */
0415     rs400_gpu_init(rdev);
0416     r100_enable_bm(rdev);
0417     /* Initialize GART (initialize after TTM so we can allocate
0418      * memory through TTM but finalize after TTM) */
0419     r = rs400_gart_enable(rdev);
0420     if (r)
0421         return r;
0422 
0423     /* allocate wb buffer */
0424     r = radeon_wb_init(rdev);
0425     if (r)
0426         return r;
0427 
0428     r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
0429     if (r) {
0430         dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
0431         return r;
0432     }
0433 
0434     /* Enable IRQ */
0435     if (!rdev->irq.installed) {
0436         r = radeon_irq_kms_init(rdev);
0437         if (r)
0438             return r;
0439     }
0440 
0441     r100_irq_set(rdev);
0442     rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
0443     /* 1M ring buffer */
0444     r = r100_cp_init(rdev, 1024 * 1024);
0445     if (r) {
0446         dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
0447         return r;
0448     }
0449 
0450     r = radeon_ib_pool_init(rdev);
0451     if (r) {
0452         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
0453         return r;
0454     }
0455 
0456     return 0;
0457 }
0458 
0459 int rs400_resume(struct radeon_device *rdev)
0460 {
0461     int r;
0462 
0463     /* Make sur GART are not working */
0464     rs400_gart_disable(rdev);
0465     /* Resume clock before doing reset */
0466     r300_clock_startup(rdev);
0467     /* setup MC before calling post tables */
0468     rs400_mc_program(rdev);
0469     /* Reset gpu before posting otherwise ATOM will enter infinite loop */
0470     if (radeon_asic_reset(rdev)) {
0471         dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
0472             RREG32(R_000E40_RBBM_STATUS),
0473             RREG32(R_0007C0_CP_STAT));
0474     }
0475     /* post */
0476     radeon_combios_asic_init(rdev->ddev);
0477     /* Resume clock after posting */
0478     r300_clock_startup(rdev);
0479     /* Initialize surface registers */
0480     radeon_surface_init(rdev);
0481 
0482     rdev->accel_working = true;
0483     r = rs400_startup(rdev);
0484     if (r) {
0485         rdev->accel_working = false;
0486     }
0487     return r;
0488 }
0489 
0490 int rs400_suspend(struct radeon_device *rdev)
0491 {
0492     radeon_pm_suspend(rdev);
0493     r100_cp_disable(rdev);
0494     radeon_wb_disable(rdev);
0495     r100_irq_disable(rdev);
0496     rs400_gart_disable(rdev);
0497     return 0;
0498 }
0499 
0500 void rs400_fini(struct radeon_device *rdev)
0501 {
0502     radeon_pm_fini(rdev);
0503     r100_cp_fini(rdev);
0504     radeon_wb_fini(rdev);
0505     radeon_ib_pool_fini(rdev);
0506     radeon_gem_fini(rdev);
0507     rs400_gart_fini(rdev);
0508     radeon_irq_kms_fini(rdev);
0509     radeon_fence_driver_fini(rdev);
0510     radeon_bo_fini(rdev);
0511     radeon_atombios_fini(rdev);
0512     kfree(rdev->bios);
0513     rdev->bios = NULL;
0514 }
0515 
0516 int rs400_init(struct radeon_device *rdev)
0517 {
0518     int r;
0519 
0520     /* Disable VGA */
0521     r100_vga_render_disable(rdev);
0522     /* Initialize scratch registers */
0523     radeon_scratch_init(rdev);
0524     /* Initialize surface registers */
0525     radeon_surface_init(rdev);
0526     /* TODO: disable VGA need to use VGA request */
0527     /* restore some register to sane defaults */
0528     r100_restore_sanity(rdev);
0529     /* BIOS*/
0530     if (!radeon_get_bios(rdev)) {
0531         if (ASIC_IS_AVIVO(rdev))
0532             return -EINVAL;
0533     }
0534     if (rdev->is_atom_bios) {
0535         dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
0536         return -EINVAL;
0537     } else {
0538         r = radeon_combios_init(rdev);
0539         if (r)
0540             return r;
0541     }
0542     /* Reset gpu before posting otherwise ATOM will enter infinite loop */
0543     if (radeon_asic_reset(rdev)) {
0544         dev_warn(rdev->dev,
0545             "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
0546             RREG32(R_000E40_RBBM_STATUS),
0547             RREG32(R_0007C0_CP_STAT));
0548     }
0549     /* check if cards are posted or not */
0550     if (radeon_boot_test_post_card(rdev) == false)
0551         return -EINVAL;
0552 
0553     /* Initialize clocks */
0554     radeon_get_clock_info(rdev->ddev);
0555     /* initialize memory controller */
0556     rs400_mc_init(rdev);
0557     /* Fence driver */
0558     radeon_fence_driver_init(rdev);
0559     /* Memory manager */
0560     r = radeon_bo_init(rdev);
0561     if (r)
0562         return r;
0563     r = rs400_gart_init(rdev);
0564     if (r)
0565         return r;
0566     r300_set_reg_safe(rdev);
0567 
0568     /* Initialize power management */
0569     radeon_pm_init(rdev);
0570 
0571     rdev->accel_working = true;
0572     r = rs400_startup(rdev);
0573     if (r) {
0574         /* Somethings want wront with the accel init stop accel */
0575         dev_err(rdev->dev, "Disabling GPU acceleration\n");
0576         r100_cp_fini(rdev);
0577         radeon_wb_fini(rdev);
0578         radeon_ib_pool_fini(rdev);
0579         rs400_gart_fini(rdev);
0580         radeon_irq_kms_fini(rdev);
0581         rdev->accel_working = false;
0582     }
0583     return 0;
0584 }
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!