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0001 /*
0002  * Permission is hereby granted, free of charge, to any person obtaining a
0003  * copy of this software and associated documentation files (the "Software"),
0004  * to deal in the Software without restriction, including without limitation
0005  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0006  * and/or sell copies of the Software, and to permit persons to whom the
0007  * Software is furnished to do so, subject to the following conditions:
0008  *
0009  * The above copyright notice and this permission notice shall be included in
0010  * all copies or substantial portions of the Software.
0011  *
0012  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0013  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0014  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0015  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0016  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0017  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0018  * OTHER DEALINGS IN THE SOFTWARE.
0019  *
0020  * Authors: Rafał Miłecki <zajec5@gmail.com>
0021  *          Alex Deucher <alexdeucher@gmail.com>
0022  */
0023 
0024 #include <linux/hwmon-sysfs.h>
0025 #include <linux/hwmon.h>
0026 #include <linux/pci.h>
0027 #include <linux/power_supply.h>
0028 
0029 #include <drm/drm_vblank.h>
0030 
0031 #include "atom.h"
0032 #include "avivod.h"
0033 #include "r600_dpm.h"
0034 #include "radeon.h"
0035 #include "radeon_pm.h"
0036 
0037 #define RADEON_IDLE_LOOP_MS 100
0038 #define RADEON_RECLOCK_DELAY_MS 200
0039 #define RADEON_WAIT_VBLANK_TIMEOUT 200
0040 
0041 static const char *radeon_pm_state_type_name[5] = {
0042     "",
0043     "Powersave",
0044     "Battery",
0045     "Balanced",
0046     "Performance",
0047 };
0048 
0049 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
0050 static void radeon_debugfs_pm_init(struct radeon_device *rdev);
0051 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
0052 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
0053 static void radeon_pm_update_profile(struct radeon_device *rdev);
0054 static void radeon_pm_set_clocks(struct radeon_device *rdev);
0055 
0056 int radeon_pm_get_type_index(struct radeon_device *rdev,
0057                  enum radeon_pm_state_type ps_type,
0058                  int instance)
0059 {
0060     int i;
0061     int found_instance = -1;
0062 
0063     for (i = 0; i < rdev->pm.num_power_states; i++) {
0064         if (rdev->pm.power_state[i].type == ps_type) {
0065             found_instance++;
0066             if (found_instance == instance)
0067                 return i;
0068         }
0069     }
0070     /* return default if no match */
0071     return rdev->pm.default_power_state_index;
0072 }
0073 
0074 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
0075 {
0076     if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
0077         mutex_lock(&rdev->pm.mutex);
0078         if (power_supply_is_system_supplied() > 0)
0079             rdev->pm.dpm.ac_power = true;
0080         else
0081             rdev->pm.dpm.ac_power = false;
0082         if (rdev->family == CHIP_ARUBA) {
0083             if (rdev->asic->dpm.enable_bapm)
0084                 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
0085         }
0086         mutex_unlock(&rdev->pm.mutex);
0087     } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
0088         if (rdev->pm.profile == PM_PROFILE_AUTO) {
0089             mutex_lock(&rdev->pm.mutex);
0090             radeon_pm_update_profile(rdev);
0091             radeon_pm_set_clocks(rdev);
0092             mutex_unlock(&rdev->pm.mutex);
0093         }
0094     }
0095 }
0096 
0097 static void radeon_pm_update_profile(struct radeon_device *rdev)
0098 {
0099     switch (rdev->pm.profile) {
0100     case PM_PROFILE_DEFAULT:
0101         rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
0102         break;
0103     case PM_PROFILE_AUTO:
0104         if (power_supply_is_system_supplied() > 0) {
0105             if (rdev->pm.active_crtc_count > 1)
0106                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
0107             else
0108                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
0109         } else {
0110             if (rdev->pm.active_crtc_count > 1)
0111                 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
0112             else
0113                 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
0114         }
0115         break;
0116     case PM_PROFILE_LOW:
0117         if (rdev->pm.active_crtc_count > 1)
0118             rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
0119         else
0120             rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
0121         break;
0122     case PM_PROFILE_MID:
0123         if (rdev->pm.active_crtc_count > 1)
0124             rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
0125         else
0126             rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
0127         break;
0128     case PM_PROFILE_HIGH:
0129         if (rdev->pm.active_crtc_count > 1)
0130             rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
0131         else
0132             rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
0133         break;
0134     }
0135 
0136     if (rdev->pm.active_crtc_count == 0) {
0137         rdev->pm.requested_power_state_index =
0138             rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
0139         rdev->pm.requested_clock_mode_index =
0140             rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
0141     } else {
0142         rdev->pm.requested_power_state_index =
0143             rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
0144         rdev->pm.requested_clock_mode_index =
0145             rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
0146     }
0147 }
0148 
0149 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
0150 {
0151     struct radeon_bo *bo, *n;
0152 
0153     if (list_empty(&rdev->gem.objects))
0154         return;
0155 
0156     list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
0157         if (bo->tbo.resource->mem_type == TTM_PL_VRAM)
0158             ttm_bo_unmap_virtual(&bo->tbo);
0159     }
0160 }
0161 
0162 static void radeon_sync_with_vblank(struct radeon_device *rdev)
0163 {
0164     if (rdev->pm.active_crtcs) {
0165         rdev->pm.vblank_sync = false;
0166         wait_event_timeout(
0167             rdev->irq.vblank_queue, rdev->pm.vblank_sync,
0168             msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
0169     }
0170 }
0171 
0172 static void radeon_set_power_state(struct radeon_device *rdev)
0173 {
0174     u32 sclk, mclk;
0175     bool misc_after = false;
0176 
0177     if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
0178         (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
0179         return;
0180 
0181     if (radeon_gui_idle(rdev)) {
0182         sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
0183             clock_info[rdev->pm.requested_clock_mode_index].sclk;
0184         if (sclk > rdev->pm.default_sclk)
0185             sclk = rdev->pm.default_sclk;
0186 
0187         /* starting with BTC, there is one state that is used for both
0188          * MH and SH.  Difference is that we always use the high clock index for
0189          * mclk and vddci.
0190          */
0191         if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
0192             (rdev->family >= CHIP_BARTS) &&
0193             rdev->pm.active_crtc_count &&
0194             ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
0195              (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
0196             mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
0197                 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
0198         else
0199             mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
0200                 clock_info[rdev->pm.requested_clock_mode_index].mclk;
0201 
0202         if (mclk > rdev->pm.default_mclk)
0203             mclk = rdev->pm.default_mclk;
0204 
0205         /* upvolt before raising clocks, downvolt after lowering clocks */
0206         if (sclk < rdev->pm.current_sclk)
0207             misc_after = true;
0208 
0209         radeon_sync_with_vblank(rdev);
0210 
0211         if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
0212             if (!radeon_pm_in_vbl(rdev))
0213                 return;
0214         }
0215 
0216         radeon_pm_prepare(rdev);
0217 
0218         if (!misc_after)
0219             /* voltage, pcie lanes, etc.*/
0220             radeon_pm_misc(rdev);
0221 
0222         /* set engine clock */
0223         if (sclk != rdev->pm.current_sclk) {
0224             radeon_pm_debug_check_in_vbl(rdev, false);
0225             radeon_set_engine_clock(rdev, sclk);
0226             radeon_pm_debug_check_in_vbl(rdev, true);
0227             rdev->pm.current_sclk = sclk;
0228             DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
0229         }
0230 
0231         /* set memory clock */
0232         if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
0233             radeon_pm_debug_check_in_vbl(rdev, false);
0234             radeon_set_memory_clock(rdev, mclk);
0235             radeon_pm_debug_check_in_vbl(rdev, true);
0236             rdev->pm.current_mclk = mclk;
0237             DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
0238         }
0239 
0240         if (misc_after)
0241             /* voltage, pcie lanes, etc.*/
0242             radeon_pm_misc(rdev);
0243 
0244         radeon_pm_finish(rdev);
0245 
0246         rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
0247         rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
0248     } else
0249         DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
0250 }
0251 
0252 static void radeon_pm_set_clocks(struct radeon_device *rdev)
0253 {
0254     struct drm_crtc *crtc;
0255     int i, r;
0256 
0257     /* no need to take locks, etc. if nothing's going to change */
0258     if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
0259         (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
0260         return;
0261 
0262     down_write(&rdev->pm.mclk_lock);
0263     mutex_lock(&rdev->ring_lock);
0264 
0265     /* wait for the rings to drain */
0266     for (i = 0; i < RADEON_NUM_RINGS; i++) {
0267         struct radeon_ring *ring = &rdev->ring[i];
0268         if (!ring->ready) {
0269             continue;
0270         }
0271         r = radeon_fence_wait_empty(rdev, i);
0272         if (r) {
0273             /* needs a GPU reset dont reset here */
0274             mutex_unlock(&rdev->ring_lock);
0275             up_write(&rdev->pm.mclk_lock);
0276             return;
0277         }
0278     }
0279 
0280     radeon_unmap_vram_bos(rdev);
0281 
0282     if (rdev->irq.installed) {
0283         i = 0;
0284         drm_for_each_crtc(crtc, rdev->ddev) {
0285             if (rdev->pm.active_crtcs & (1 << i)) {
0286                 /* This can fail if a modeset is in progress */
0287                 if (drm_crtc_vblank_get(crtc) == 0)
0288                     rdev->pm.req_vblank |= (1 << i);
0289                 else
0290                     DRM_DEBUG_DRIVER("crtc %d no vblank, can glitch\n",
0291                              i);
0292             }
0293             i++;
0294         }
0295     }
0296 
0297     radeon_set_power_state(rdev);
0298 
0299     if (rdev->irq.installed) {
0300         i = 0;
0301         drm_for_each_crtc(crtc, rdev->ddev) {
0302             if (rdev->pm.req_vblank & (1 << i)) {
0303                 rdev->pm.req_vblank &= ~(1 << i);
0304                 drm_crtc_vblank_put(crtc);
0305             }
0306             i++;
0307         }
0308     }
0309 
0310     /* update display watermarks based on new power state */
0311     radeon_update_bandwidth_info(rdev);
0312     if (rdev->pm.active_crtc_count)
0313         radeon_bandwidth_update(rdev);
0314 
0315     rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
0316 
0317     mutex_unlock(&rdev->ring_lock);
0318     up_write(&rdev->pm.mclk_lock);
0319 }
0320 
0321 static void radeon_pm_print_states(struct radeon_device *rdev)
0322 {
0323     int i, j;
0324     struct radeon_power_state *power_state;
0325     struct radeon_pm_clock_info *clock_info;
0326 
0327     DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
0328     for (i = 0; i < rdev->pm.num_power_states; i++) {
0329         power_state = &rdev->pm.power_state[i];
0330         DRM_DEBUG_DRIVER("State %d: %s\n", i,
0331             radeon_pm_state_type_name[power_state->type]);
0332         if (i == rdev->pm.default_power_state_index)
0333             DRM_DEBUG_DRIVER("\tDefault");
0334         if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
0335             DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
0336         if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
0337             DRM_DEBUG_DRIVER("\tSingle display only\n");
0338         DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
0339         for (j = 0; j < power_state->num_clock_modes; j++) {
0340             clock_info = &(power_state->clock_info[j]);
0341             if (rdev->flags & RADEON_IS_IGP)
0342                 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
0343                          j,
0344                          clock_info->sclk * 10);
0345             else
0346                 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
0347                          j,
0348                          clock_info->sclk * 10,
0349                          clock_info->mclk * 10,
0350                          clock_info->voltage.voltage);
0351         }
0352     }
0353 }
0354 
0355 static ssize_t radeon_get_pm_profile(struct device *dev,
0356                      struct device_attribute *attr,
0357                      char *buf)
0358 {
0359     struct drm_device *ddev = dev_get_drvdata(dev);
0360     struct radeon_device *rdev = ddev->dev_private;
0361     int cp = rdev->pm.profile;
0362 
0363     return sysfs_emit(buf, "%s\n", (cp == PM_PROFILE_AUTO) ? "auto" :
0364               (cp == PM_PROFILE_LOW) ? "low" :
0365               (cp == PM_PROFILE_MID) ? "mid" :
0366               (cp == PM_PROFILE_HIGH) ? "high" : "default");
0367 }
0368 
0369 static ssize_t radeon_set_pm_profile(struct device *dev,
0370                      struct device_attribute *attr,
0371                      const char *buf,
0372                      size_t count)
0373 {
0374     struct drm_device *ddev = dev_get_drvdata(dev);
0375     struct radeon_device *rdev = ddev->dev_private;
0376 
0377     /* Can't set profile when the card is off */
0378     if  ((rdev->flags & RADEON_IS_PX) &&
0379          (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
0380         return -EINVAL;
0381 
0382     mutex_lock(&rdev->pm.mutex);
0383     if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
0384         if (strncmp("default", buf, strlen("default")) == 0)
0385             rdev->pm.profile = PM_PROFILE_DEFAULT;
0386         else if (strncmp("auto", buf, strlen("auto")) == 0)
0387             rdev->pm.profile = PM_PROFILE_AUTO;
0388         else if (strncmp("low", buf, strlen("low")) == 0)
0389             rdev->pm.profile = PM_PROFILE_LOW;
0390         else if (strncmp("mid", buf, strlen("mid")) == 0)
0391             rdev->pm.profile = PM_PROFILE_MID;
0392         else if (strncmp("high", buf, strlen("high")) == 0)
0393             rdev->pm.profile = PM_PROFILE_HIGH;
0394         else {
0395             count = -EINVAL;
0396             goto fail;
0397         }
0398         radeon_pm_update_profile(rdev);
0399         radeon_pm_set_clocks(rdev);
0400     } else
0401         count = -EINVAL;
0402 
0403 fail:
0404     mutex_unlock(&rdev->pm.mutex);
0405 
0406     return count;
0407 }
0408 
0409 static ssize_t radeon_get_pm_method(struct device *dev,
0410                     struct device_attribute *attr,
0411                     char *buf)
0412 {
0413     struct drm_device *ddev = dev_get_drvdata(dev);
0414     struct radeon_device *rdev = ddev->dev_private;
0415     int pm = rdev->pm.pm_method;
0416 
0417     return sysfs_emit(buf, "%s\n", (pm == PM_METHOD_DYNPM) ? "dynpm" :
0418               (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
0419 }
0420 
0421 static ssize_t radeon_set_pm_method(struct device *dev,
0422                     struct device_attribute *attr,
0423                     const char *buf,
0424                     size_t count)
0425 {
0426     struct drm_device *ddev = dev_get_drvdata(dev);
0427     struct radeon_device *rdev = ddev->dev_private;
0428 
0429     /* Can't set method when the card is off */
0430     if  ((rdev->flags & RADEON_IS_PX) &&
0431          (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
0432         count = -EINVAL;
0433         goto fail;
0434     }
0435 
0436     /* we don't support the legacy modes with dpm */
0437     if (rdev->pm.pm_method == PM_METHOD_DPM) {
0438         count = -EINVAL;
0439         goto fail;
0440     }
0441 
0442     if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
0443         mutex_lock(&rdev->pm.mutex);
0444         rdev->pm.pm_method = PM_METHOD_DYNPM;
0445         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
0446         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
0447         mutex_unlock(&rdev->pm.mutex);
0448     } else if (strncmp("profile", buf, strlen("profile")) == 0) {
0449         mutex_lock(&rdev->pm.mutex);
0450         /* disable dynpm */
0451         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
0452         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
0453         rdev->pm.pm_method = PM_METHOD_PROFILE;
0454         mutex_unlock(&rdev->pm.mutex);
0455         cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
0456     } else {
0457         count = -EINVAL;
0458         goto fail;
0459     }
0460     radeon_pm_compute_clocks(rdev);
0461 fail:
0462     return count;
0463 }
0464 
0465 static ssize_t radeon_get_dpm_state(struct device *dev,
0466                     struct device_attribute *attr,
0467                     char *buf)
0468 {
0469     struct drm_device *ddev = dev_get_drvdata(dev);
0470     struct radeon_device *rdev = ddev->dev_private;
0471     enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
0472 
0473     return sysfs_emit(buf, "%s\n",
0474               (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
0475               (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
0476 }
0477 
0478 static ssize_t radeon_set_dpm_state(struct device *dev,
0479                     struct device_attribute *attr,
0480                     const char *buf,
0481                     size_t count)
0482 {
0483     struct drm_device *ddev = dev_get_drvdata(dev);
0484     struct radeon_device *rdev = ddev->dev_private;
0485 
0486     mutex_lock(&rdev->pm.mutex);
0487     if (strncmp("battery", buf, strlen("battery")) == 0)
0488         rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
0489     else if (strncmp("balanced", buf, strlen("balanced")) == 0)
0490         rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
0491     else if (strncmp("performance", buf, strlen("performance")) == 0)
0492         rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
0493     else {
0494         mutex_unlock(&rdev->pm.mutex);
0495         count = -EINVAL;
0496         goto fail;
0497     }
0498     mutex_unlock(&rdev->pm.mutex);
0499 
0500     /* Can't set dpm state when the card is off */
0501     if (!(rdev->flags & RADEON_IS_PX) ||
0502         (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
0503         radeon_pm_compute_clocks(rdev);
0504 
0505 fail:
0506     return count;
0507 }
0508 
0509 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
0510                                struct device_attribute *attr,
0511                                char *buf)
0512 {
0513     struct drm_device *ddev = dev_get_drvdata(dev);
0514     struct radeon_device *rdev = ddev->dev_private;
0515     enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
0516 
0517     if  ((rdev->flags & RADEON_IS_PX) &&
0518          (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
0519         return sysfs_emit(buf, "off\n");
0520 
0521     return sysfs_emit(buf, "%s\n",
0522               (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
0523               (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
0524 }
0525 
0526 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
0527                                struct device_attribute *attr,
0528                                const char *buf,
0529                                size_t count)
0530 {
0531     struct drm_device *ddev = dev_get_drvdata(dev);
0532     struct radeon_device *rdev = ddev->dev_private;
0533     enum radeon_dpm_forced_level level;
0534     int ret = 0;
0535 
0536     /* Can't force performance level when the card is off */
0537     if  ((rdev->flags & RADEON_IS_PX) &&
0538          (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
0539         return -EINVAL;
0540 
0541     mutex_lock(&rdev->pm.mutex);
0542     if (strncmp("low", buf, strlen("low")) == 0) {
0543         level = RADEON_DPM_FORCED_LEVEL_LOW;
0544     } else if (strncmp("high", buf, strlen("high")) == 0) {
0545         level = RADEON_DPM_FORCED_LEVEL_HIGH;
0546     } else if (strncmp("auto", buf, strlen("auto")) == 0) {
0547         level = RADEON_DPM_FORCED_LEVEL_AUTO;
0548     } else {
0549         count = -EINVAL;
0550         goto fail;
0551     }
0552     if (rdev->asic->dpm.force_performance_level) {
0553         if (rdev->pm.dpm.thermal_active) {
0554             count = -EINVAL;
0555             goto fail;
0556         }
0557         ret = radeon_dpm_force_performance_level(rdev, level);
0558         if (ret)
0559             count = -EINVAL;
0560     }
0561 fail:
0562     mutex_unlock(&rdev->pm.mutex);
0563 
0564     return count;
0565 }
0566 
0567 static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev,
0568                         struct device_attribute *attr,
0569                         char *buf)
0570 {
0571     struct radeon_device *rdev = dev_get_drvdata(dev);
0572     u32 pwm_mode = 0;
0573 
0574     if (rdev->asic->dpm.fan_ctrl_get_mode)
0575         pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev);
0576 
0577     /* never 0 (full-speed), fuse or smc-controlled always */
0578     return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
0579 }
0580 
0581 static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev,
0582                         struct device_attribute *attr,
0583                         const char *buf,
0584                         size_t count)
0585 {
0586     struct radeon_device *rdev = dev_get_drvdata(dev);
0587     int err;
0588     int value;
0589 
0590     if(!rdev->asic->dpm.fan_ctrl_set_mode)
0591         return -EINVAL;
0592 
0593     err = kstrtoint(buf, 10, &value);
0594     if (err)
0595         return err;
0596 
0597     switch (value) {
0598     case 1: /* manual, percent-based */
0599         rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC);
0600         break;
0601     default: /* disable */
0602         rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0);
0603         break;
0604     }
0605 
0606     return count;
0607 }
0608 
0609 static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev,
0610                      struct device_attribute *attr,
0611                      char *buf)
0612 {
0613     return sprintf(buf, "%i\n", 0);
0614 }
0615 
0616 static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev,
0617                      struct device_attribute *attr,
0618                      char *buf)
0619 {
0620     return sprintf(buf, "%i\n", 255);
0621 }
0622 
0623 static ssize_t radeon_hwmon_set_pwm1(struct device *dev,
0624                      struct device_attribute *attr,
0625                      const char *buf, size_t count)
0626 {
0627     struct radeon_device *rdev = dev_get_drvdata(dev);
0628     int err;
0629     u32 value;
0630 
0631     err = kstrtou32(buf, 10, &value);
0632     if (err)
0633         return err;
0634 
0635     value = (value * 100) / 255;
0636 
0637     err = rdev->asic->dpm.set_fan_speed_percent(rdev, value);
0638     if (err)
0639         return err;
0640 
0641     return count;
0642 }
0643 
0644 static ssize_t radeon_hwmon_get_pwm1(struct device *dev,
0645                      struct device_attribute *attr,
0646                      char *buf)
0647 {
0648     struct radeon_device *rdev = dev_get_drvdata(dev);
0649     int err;
0650     u32 speed;
0651 
0652     err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed);
0653     if (err)
0654         return err;
0655 
0656     speed = (speed * 255) / 100;
0657 
0658     return sprintf(buf, "%i\n", speed);
0659 }
0660 
0661 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
0662 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
0663 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
0664 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
0665            radeon_get_dpm_forced_performance_level,
0666            radeon_set_dpm_forced_performance_level);
0667 
0668 static ssize_t radeon_hwmon_show_temp(struct device *dev,
0669                       struct device_attribute *attr,
0670                       char *buf)
0671 {
0672     struct radeon_device *rdev = dev_get_drvdata(dev);
0673     struct drm_device *ddev = rdev->ddev;
0674     int temp;
0675 
0676     /* Can't get temperature when the card is off */
0677     if  ((rdev->flags & RADEON_IS_PX) &&
0678          (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
0679         return -EINVAL;
0680 
0681     if (rdev->asic->pm.get_temperature)
0682         temp = radeon_get_temperature(rdev);
0683     else
0684         temp = 0;
0685 
0686     return sysfs_emit(buf, "%d\n", temp);
0687 }
0688 
0689 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
0690                          struct device_attribute *attr,
0691                          char *buf)
0692 {
0693     struct radeon_device *rdev = dev_get_drvdata(dev);
0694     int hyst = to_sensor_dev_attr(attr)->index;
0695     int temp;
0696 
0697     if (hyst)
0698         temp = rdev->pm.dpm.thermal.min_temp;
0699     else
0700         temp = rdev->pm.dpm.thermal.max_temp;
0701 
0702     return sysfs_emit(buf, "%d\n", temp);
0703 }
0704 
0705 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
0706 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
0707 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
0708 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0);
0709 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0);
0710 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0);
0711 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0);
0712 
0713 static ssize_t radeon_hwmon_show_sclk(struct device *dev,
0714                       struct device_attribute *attr, char *buf)
0715 {
0716     struct radeon_device *rdev = dev_get_drvdata(dev);
0717     struct drm_device *ddev = rdev->ddev;
0718     u32 sclk = 0;
0719 
0720     /* Can't get clock frequency when the card is off */
0721     if ((rdev->flags & RADEON_IS_PX) &&
0722         (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
0723         return -EINVAL;
0724 
0725     if (rdev->asic->dpm.get_current_sclk)
0726         sclk = radeon_dpm_get_current_sclk(rdev);
0727 
0728     /* Value returned by dpm is in 10 KHz units, need to convert it into Hz 
0729        for hwmon */
0730     sclk *= 10000;
0731 
0732     return sysfs_emit(buf, "%u\n", sclk);
0733 }
0734 
0735 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, radeon_hwmon_show_sclk, NULL,
0736               0);
0737 
0738 static ssize_t radeon_hwmon_show_vddc(struct device *dev,
0739                       struct device_attribute *attr, char *buf)
0740 {
0741     struct radeon_device *rdev = dev_get_drvdata(dev);
0742     struct drm_device *ddev = rdev->ddev;
0743     u16 vddc = 0;
0744 
0745     /* Can't get vddc when the card is off */
0746     if ((rdev->flags & RADEON_IS_PX) &&
0747         (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
0748         return -EINVAL;
0749 
0750     if (rdev->asic->dpm.get_current_vddc)
0751         vddc = rdev->asic->dpm.get_current_vddc(rdev);
0752 
0753     return sysfs_emit(buf, "%u\n", vddc);
0754 }
0755 
0756 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, radeon_hwmon_show_vddc, NULL,
0757               0);
0758 
0759 static struct attribute *hwmon_attributes[] = {
0760     &sensor_dev_attr_temp1_input.dev_attr.attr,
0761     &sensor_dev_attr_temp1_crit.dev_attr.attr,
0762     &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
0763     &sensor_dev_attr_pwm1.dev_attr.attr,
0764     &sensor_dev_attr_pwm1_enable.dev_attr.attr,
0765     &sensor_dev_attr_pwm1_min.dev_attr.attr,
0766     &sensor_dev_attr_pwm1_max.dev_attr.attr,
0767     &sensor_dev_attr_freq1_input.dev_attr.attr,
0768     &sensor_dev_attr_in0_input.dev_attr.attr,
0769     NULL
0770 };
0771 
0772 static umode_t hwmon_attributes_visible(struct kobject *kobj,
0773                     struct attribute *attr, int index)
0774 {
0775     struct device *dev = kobj_to_dev(kobj);
0776     struct radeon_device *rdev = dev_get_drvdata(dev);
0777     umode_t effective_mode = attr->mode;
0778 
0779     /* Skip attributes if DPM is not enabled */
0780     if (rdev->pm.pm_method != PM_METHOD_DPM &&
0781         (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
0782          attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
0783          attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
0784          attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
0785          attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
0786          attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
0787          attr == &sensor_dev_attr_freq1_input.dev_attr.attr ||
0788          attr == &sensor_dev_attr_in0_input.dev_attr.attr))
0789         return 0;
0790 
0791     /* Skip vddc attribute if get_current_vddc is not implemented */
0792     if(attr == &sensor_dev_attr_in0_input.dev_attr.attr &&
0793         !rdev->asic->dpm.get_current_vddc)
0794         return 0;
0795 
0796     /* Skip fan attributes if fan is not present */
0797     if (rdev->pm.no_fan &&
0798         (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
0799          attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
0800          attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
0801          attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
0802         return 0;
0803 
0804     /* mask fan attributes if we have no bindings for this asic to expose */
0805     if ((!rdev->asic->dpm.get_fan_speed_percent &&
0806          attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
0807         (!rdev->asic->dpm.fan_ctrl_get_mode &&
0808          attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
0809         effective_mode &= ~S_IRUGO;
0810 
0811     if ((!rdev->asic->dpm.set_fan_speed_percent &&
0812          attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
0813         (!rdev->asic->dpm.fan_ctrl_set_mode &&
0814          attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
0815         effective_mode &= ~S_IWUSR;
0816 
0817     /* hide max/min values if we can't both query and manage the fan */
0818     if ((!rdev->asic->dpm.set_fan_speed_percent &&
0819          !rdev->asic->dpm.get_fan_speed_percent) &&
0820         (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
0821          attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
0822         return 0;
0823 
0824     return effective_mode;
0825 }
0826 
0827 static const struct attribute_group hwmon_attrgroup = {
0828     .attrs = hwmon_attributes,
0829     .is_visible = hwmon_attributes_visible,
0830 };
0831 
0832 static const struct attribute_group *hwmon_groups[] = {
0833     &hwmon_attrgroup,
0834     NULL
0835 };
0836 
0837 static int radeon_hwmon_init(struct radeon_device *rdev)
0838 {
0839     int err = 0;
0840 
0841     switch (rdev->pm.int_thermal_type) {
0842     case THERMAL_TYPE_RV6XX:
0843     case THERMAL_TYPE_RV770:
0844     case THERMAL_TYPE_EVERGREEN:
0845     case THERMAL_TYPE_NI:
0846     case THERMAL_TYPE_SUMO:
0847     case THERMAL_TYPE_SI:
0848     case THERMAL_TYPE_CI:
0849     case THERMAL_TYPE_KV:
0850         if (rdev->asic->pm.get_temperature == NULL)
0851             return err;
0852         rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
0853                                        "radeon", rdev,
0854                                        hwmon_groups);
0855         if (IS_ERR(rdev->pm.int_hwmon_dev)) {
0856             err = PTR_ERR(rdev->pm.int_hwmon_dev);
0857             dev_err(rdev->dev,
0858                 "Unable to register hwmon device: %d\n", err);
0859         }
0860         break;
0861     default:
0862         break;
0863     }
0864 
0865     return err;
0866 }
0867 
0868 static void radeon_hwmon_fini(struct radeon_device *rdev)
0869 {
0870     if (rdev->pm.int_hwmon_dev)
0871         hwmon_device_unregister(rdev->pm.int_hwmon_dev);
0872 }
0873 
0874 static void radeon_dpm_thermal_work_handler(struct work_struct *work)
0875 {
0876     struct radeon_device *rdev =
0877         container_of(work, struct radeon_device,
0878                  pm.dpm.thermal.work);
0879     /* switch to the thermal state */
0880     enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
0881 
0882     if (!rdev->pm.dpm_enabled)
0883         return;
0884 
0885     if (rdev->asic->pm.get_temperature) {
0886         int temp = radeon_get_temperature(rdev);
0887 
0888         if (temp < rdev->pm.dpm.thermal.min_temp)
0889             /* switch back the user state */
0890             dpm_state = rdev->pm.dpm.user_state;
0891     } else {
0892         if (rdev->pm.dpm.thermal.high_to_low)
0893             /* switch back the user state */
0894             dpm_state = rdev->pm.dpm.user_state;
0895     }
0896     mutex_lock(&rdev->pm.mutex);
0897     if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
0898         rdev->pm.dpm.thermal_active = true;
0899     else
0900         rdev->pm.dpm.thermal_active = false;
0901     rdev->pm.dpm.state = dpm_state;
0902     mutex_unlock(&rdev->pm.mutex);
0903 
0904     radeon_pm_compute_clocks(rdev);
0905 }
0906 
0907 static bool radeon_dpm_single_display(struct radeon_device *rdev)
0908 {
0909     bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
0910         true : false;
0911 
0912     /* check if the vblank period is too short to adjust the mclk */
0913     if (single_display && rdev->asic->dpm.vblank_too_short) {
0914         if (radeon_dpm_vblank_too_short(rdev))
0915             single_display = false;
0916     }
0917 
0918     /* 120hz tends to be problematic even if they are under the
0919      * vblank limit.
0920      */
0921     if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120))
0922         single_display = false;
0923 
0924     return single_display;
0925 }
0926 
0927 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
0928                              enum radeon_pm_state_type dpm_state)
0929 {
0930     int i;
0931     struct radeon_ps *ps;
0932     u32 ui_class;
0933     bool single_display = radeon_dpm_single_display(rdev);
0934 
0935     /* certain older asics have a separare 3D performance state,
0936      * so try that first if the user selected performance
0937      */
0938     if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
0939         dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
0940     /* balanced states don't exist at the moment */
0941     if (dpm_state == POWER_STATE_TYPE_BALANCED)
0942         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
0943 
0944 restart_search:
0945     /* Pick the best power state based on current conditions */
0946     for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
0947         ps = &rdev->pm.dpm.ps[i];
0948         ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
0949         switch (dpm_state) {
0950         /* user states */
0951         case POWER_STATE_TYPE_BATTERY:
0952             if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
0953                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
0954                     if (single_display)
0955                         return ps;
0956                 } else
0957                     return ps;
0958             }
0959             break;
0960         case POWER_STATE_TYPE_BALANCED:
0961             if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
0962                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
0963                     if (single_display)
0964                         return ps;
0965                 } else
0966                     return ps;
0967             }
0968             break;
0969         case POWER_STATE_TYPE_PERFORMANCE:
0970             if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
0971                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
0972                     if (single_display)
0973                         return ps;
0974                 } else
0975                     return ps;
0976             }
0977             break;
0978         /* internal states */
0979         case POWER_STATE_TYPE_INTERNAL_UVD:
0980             if (rdev->pm.dpm.uvd_ps)
0981                 return rdev->pm.dpm.uvd_ps;
0982             else
0983                 break;
0984         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
0985             if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
0986                 return ps;
0987             break;
0988         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
0989             if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
0990                 return ps;
0991             break;
0992         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
0993             if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
0994                 return ps;
0995             break;
0996         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
0997             if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
0998                 return ps;
0999             break;
1000         case POWER_STATE_TYPE_INTERNAL_BOOT:
1001             return rdev->pm.dpm.boot_ps;
1002         case POWER_STATE_TYPE_INTERNAL_THERMAL:
1003             if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1004                 return ps;
1005             break;
1006         case POWER_STATE_TYPE_INTERNAL_ACPI:
1007             if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
1008                 return ps;
1009             break;
1010         case POWER_STATE_TYPE_INTERNAL_ULV:
1011             if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
1012                 return ps;
1013             break;
1014         case POWER_STATE_TYPE_INTERNAL_3DPERF:
1015             if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1016                 return ps;
1017             break;
1018         default:
1019             break;
1020         }
1021     }
1022     /* use a fallback state if we didn't match */
1023     switch (dpm_state) {
1024     case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1025         dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1026         goto restart_search;
1027     case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1028     case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1029     case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1030         if (rdev->pm.dpm.uvd_ps) {
1031             return rdev->pm.dpm.uvd_ps;
1032         } else {
1033             dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1034             goto restart_search;
1035         }
1036     case POWER_STATE_TYPE_INTERNAL_THERMAL:
1037         dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1038         goto restart_search;
1039     case POWER_STATE_TYPE_INTERNAL_ACPI:
1040         dpm_state = POWER_STATE_TYPE_BATTERY;
1041         goto restart_search;
1042     case POWER_STATE_TYPE_BATTERY:
1043     case POWER_STATE_TYPE_BALANCED:
1044     case POWER_STATE_TYPE_INTERNAL_3DPERF:
1045         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1046         goto restart_search;
1047     default:
1048         break;
1049     }
1050 
1051     return NULL;
1052 }
1053 
1054 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
1055 {
1056     int i;
1057     struct radeon_ps *ps;
1058     enum radeon_pm_state_type dpm_state;
1059     int ret;
1060     bool single_display = radeon_dpm_single_display(rdev);
1061 
1062     /* if dpm init failed */
1063     if (!rdev->pm.dpm_enabled)
1064         return;
1065 
1066     if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
1067         /* add other state override checks here */
1068         if ((!rdev->pm.dpm.thermal_active) &&
1069             (!rdev->pm.dpm.uvd_active))
1070             rdev->pm.dpm.state = rdev->pm.dpm.user_state;
1071     }
1072     dpm_state = rdev->pm.dpm.state;
1073 
1074     ps = radeon_dpm_pick_power_state(rdev, dpm_state);
1075     if (ps)
1076         rdev->pm.dpm.requested_ps = ps;
1077     else
1078         return;
1079 
1080     /* no need to reprogram if nothing changed unless we are on BTC+ */
1081     if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
1082         /* vce just modifies an existing state so force a change */
1083         if (ps->vce_active != rdev->pm.dpm.vce_active)
1084             goto force;
1085         /* user has made a display change (such as timing) */
1086         if (rdev->pm.dpm.single_display != single_display)
1087             goto force;
1088         if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
1089             /* for pre-BTC and APUs if the num crtcs changed but state is the same,
1090              * all we need to do is update the display configuration.
1091              */
1092             if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
1093                 /* update display watermarks based on new power state */
1094                 radeon_bandwidth_update(rdev);
1095                 /* update displays */
1096                 radeon_dpm_display_configuration_changed(rdev);
1097                 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1098                 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1099             }
1100             return;
1101         } else {
1102             /* for BTC+ if the num crtcs hasn't changed and state is the same,
1103              * nothing to do, if the num crtcs is > 1 and state is the same,
1104              * update display configuration.
1105              */
1106             if (rdev->pm.dpm.new_active_crtcs ==
1107                 rdev->pm.dpm.current_active_crtcs) {
1108                 return;
1109             } else {
1110                 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
1111                     (rdev->pm.dpm.new_active_crtc_count > 1)) {
1112                     /* update display watermarks based on new power state */
1113                     radeon_bandwidth_update(rdev);
1114                     /* update displays */
1115                     radeon_dpm_display_configuration_changed(rdev);
1116                     rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1117                     rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1118                     return;
1119                 }
1120             }
1121         }
1122     }
1123 
1124 force:
1125     if (radeon_dpm == 1) {
1126         printk("switching from power state:\n");
1127         radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
1128         printk("switching to power state:\n");
1129         radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
1130     }
1131 
1132     down_write(&rdev->pm.mclk_lock);
1133     mutex_lock(&rdev->ring_lock);
1134 
1135     /* update whether vce is active */
1136     ps->vce_active = rdev->pm.dpm.vce_active;
1137 
1138     ret = radeon_dpm_pre_set_power_state(rdev);
1139     if (ret)
1140         goto done;
1141 
1142     /* update display watermarks based on new power state */
1143     radeon_bandwidth_update(rdev);
1144     /* update displays */
1145     radeon_dpm_display_configuration_changed(rdev);
1146 
1147     /* wait for the rings to drain */
1148     for (i = 0; i < RADEON_NUM_RINGS; i++) {
1149         struct radeon_ring *ring = &rdev->ring[i];
1150         if (ring->ready)
1151             radeon_fence_wait_empty(rdev, i);
1152     }
1153 
1154     /* program the new power state */
1155     radeon_dpm_set_power_state(rdev);
1156 
1157     /* update current power state */
1158     rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
1159 
1160     radeon_dpm_post_set_power_state(rdev);
1161 
1162     rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1163     rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1164     rdev->pm.dpm.single_display = single_display;
1165 
1166     if (rdev->asic->dpm.force_performance_level) {
1167         if (rdev->pm.dpm.thermal_active) {
1168             enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
1169             /* force low perf level for thermal */
1170             radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
1171             /* save the user's level */
1172             rdev->pm.dpm.forced_level = level;
1173         } else {
1174             /* otherwise, user selected level */
1175             radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
1176         }
1177     }
1178 
1179 done:
1180     mutex_unlock(&rdev->ring_lock);
1181     up_write(&rdev->pm.mclk_lock);
1182 }
1183 
1184 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
1185 {
1186     enum radeon_pm_state_type dpm_state;
1187 
1188     if (rdev->asic->dpm.powergate_uvd) {
1189         mutex_lock(&rdev->pm.mutex);
1190         /* don't powergate anything if we
1191            have active but pause streams */
1192         enable |= rdev->pm.dpm.sd > 0;
1193         enable |= rdev->pm.dpm.hd > 0;
1194         /* enable/disable UVD */
1195         radeon_dpm_powergate_uvd(rdev, !enable);
1196         mutex_unlock(&rdev->pm.mutex);
1197     } else {
1198         if (enable) {
1199             mutex_lock(&rdev->pm.mutex);
1200             rdev->pm.dpm.uvd_active = true;
1201             /* disable this for now */
1202 #if 0
1203             if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
1204                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
1205             else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
1206                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1207             else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
1208                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1209             else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
1210                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
1211             else
1212 #endif
1213                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
1214             rdev->pm.dpm.state = dpm_state;
1215             mutex_unlock(&rdev->pm.mutex);
1216         } else {
1217             mutex_lock(&rdev->pm.mutex);
1218             rdev->pm.dpm.uvd_active = false;
1219             mutex_unlock(&rdev->pm.mutex);
1220         }
1221 
1222         radeon_pm_compute_clocks(rdev);
1223     }
1224 }
1225 
1226 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
1227 {
1228     if (enable) {
1229         mutex_lock(&rdev->pm.mutex);
1230         rdev->pm.dpm.vce_active = true;
1231         /* XXX select vce level based on ring/task */
1232         rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
1233         mutex_unlock(&rdev->pm.mutex);
1234     } else {
1235         mutex_lock(&rdev->pm.mutex);
1236         rdev->pm.dpm.vce_active = false;
1237         mutex_unlock(&rdev->pm.mutex);
1238     }
1239 
1240     radeon_pm_compute_clocks(rdev);
1241 }
1242 
1243 static void radeon_pm_suspend_old(struct radeon_device *rdev)
1244 {
1245     mutex_lock(&rdev->pm.mutex);
1246     if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1247         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
1248             rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
1249     }
1250     mutex_unlock(&rdev->pm.mutex);
1251 
1252     cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1253 }
1254 
1255 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
1256 {
1257     mutex_lock(&rdev->pm.mutex);
1258     /* disable dpm */
1259     radeon_dpm_disable(rdev);
1260     /* reset the power state */
1261     rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1262     rdev->pm.dpm_enabled = false;
1263     mutex_unlock(&rdev->pm.mutex);
1264 }
1265 
1266 void radeon_pm_suspend(struct radeon_device *rdev)
1267 {
1268     if (rdev->pm.pm_method == PM_METHOD_DPM)
1269         radeon_pm_suspend_dpm(rdev);
1270     else
1271         radeon_pm_suspend_old(rdev);
1272 }
1273 
1274 static void radeon_pm_resume_old(struct radeon_device *rdev)
1275 {
1276     /* set up the default clocks if the MC ucode is loaded */
1277     if ((rdev->family >= CHIP_BARTS) &&
1278         (rdev->family <= CHIP_CAYMAN) &&
1279         rdev->mc_fw) {
1280         if (rdev->pm.default_vddc)
1281             radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1282                         SET_VOLTAGE_TYPE_ASIC_VDDC);
1283         if (rdev->pm.default_vddci)
1284             radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1285                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
1286         if (rdev->pm.default_sclk)
1287             radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1288         if (rdev->pm.default_mclk)
1289             radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1290     }
1291     /* asic init will reset the default power state */
1292     mutex_lock(&rdev->pm.mutex);
1293     rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1294     rdev->pm.current_clock_mode_index = 0;
1295     rdev->pm.current_sclk = rdev->pm.default_sclk;
1296     rdev->pm.current_mclk = rdev->pm.default_mclk;
1297     if (rdev->pm.power_state) {
1298         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1299         rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1300     }
1301     if (rdev->pm.pm_method == PM_METHOD_DYNPM
1302         && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1303         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1304         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1305                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1306     }
1307     mutex_unlock(&rdev->pm.mutex);
1308     radeon_pm_compute_clocks(rdev);
1309 }
1310 
1311 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1312 {
1313     int ret;
1314 
1315     /* asic init will reset to the boot state */
1316     mutex_lock(&rdev->pm.mutex);
1317     rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1318     radeon_dpm_setup_asic(rdev);
1319     ret = radeon_dpm_enable(rdev);
1320     mutex_unlock(&rdev->pm.mutex);
1321     if (ret)
1322         goto dpm_resume_fail;
1323     rdev->pm.dpm_enabled = true;
1324     return;
1325 
1326 dpm_resume_fail:
1327     DRM_ERROR("radeon: dpm resume failed\n");
1328     if ((rdev->family >= CHIP_BARTS) &&
1329         (rdev->family <= CHIP_CAYMAN) &&
1330         rdev->mc_fw) {
1331         if (rdev->pm.default_vddc)
1332             radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1333                         SET_VOLTAGE_TYPE_ASIC_VDDC);
1334         if (rdev->pm.default_vddci)
1335             radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1336                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
1337         if (rdev->pm.default_sclk)
1338             radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1339         if (rdev->pm.default_mclk)
1340             radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1341     }
1342 }
1343 
1344 void radeon_pm_resume(struct radeon_device *rdev)
1345 {
1346     if (rdev->pm.pm_method == PM_METHOD_DPM)
1347         radeon_pm_resume_dpm(rdev);
1348     else
1349         radeon_pm_resume_old(rdev);
1350 }
1351 
1352 static int radeon_pm_init_old(struct radeon_device *rdev)
1353 {
1354     int ret;
1355 
1356     rdev->pm.profile = PM_PROFILE_DEFAULT;
1357     rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1358     rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1359     rdev->pm.dynpm_can_upclock = true;
1360     rdev->pm.dynpm_can_downclock = true;
1361     rdev->pm.default_sclk = rdev->clock.default_sclk;
1362     rdev->pm.default_mclk = rdev->clock.default_mclk;
1363     rdev->pm.current_sclk = rdev->clock.default_sclk;
1364     rdev->pm.current_mclk = rdev->clock.default_mclk;
1365     rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1366 
1367     if (rdev->bios) {
1368         if (rdev->is_atom_bios)
1369             radeon_atombios_get_power_modes(rdev);
1370         else
1371             radeon_combios_get_power_modes(rdev);
1372         radeon_pm_print_states(rdev);
1373         radeon_pm_init_profile(rdev);
1374         /* set up the default clocks if the MC ucode is loaded */
1375         if ((rdev->family >= CHIP_BARTS) &&
1376             (rdev->family <= CHIP_CAYMAN) &&
1377             rdev->mc_fw) {
1378             if (rdev->pm.default_vddc)
1379                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1380                             SET_VOLTAGE_TYPE_ASIC_VDDC);
1381             if (rdev->pm.default_vddci)
1382                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1383                             SET_VOLTAGE_TYPE_ASIC_VDDCI);
1384             if (rdev->pm.default_sclk)
1385                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1386             if (rdev->pm.default_mclk)
1387                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1388         }
1389     }
1390 
1391     /* set up the internal thermal sensor if applicable */
1392     ret = radeon_hwmon_init(rdev);
1393     if (ret)
1394         return ret;
1395 
1396     INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1397 
1398     if (rdev->pm.num_power_states > 1) {
1399         radeon_debugfs_pm_init(rdev);
1400         DRM_INFO("radeon: power management initialized\n");
1401     }
1402 
1403     return 0;
1404 }
1405 
1406 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1407 {
1408     int i;
1409 
1410     for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1411         printk("== power state %d ==\n", i);
1412         radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1413     }
1414 }
1415 
1416 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1417 {
1418     int ret;
1419 
1420     /* default to balanced state */
1421     rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1422     rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1423     rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1424     rdev->pm.default_sclk = rdev->clock.default_sclk;
1425     rdev->pm.default_mclk = rdev->clock.default_mclk;
1426     rdev->pm.current_sclk = rdev->clock.default_sclk;
1427     rdev->pm.current_mclk = rdev->clock.default_mclk;
1428     rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1429 
1430     if (rdev->bios && rdev->is_atom_bios)
1431         radeon_atombios_get_power_modes(rdev);
1432     else
1433         return -EINVAL;
1434 
1435     /* set up the internal thermal sensor if applicable */
1436     ret = radeon_hwmon_init(rdev);
1437     if (ret)
1438         return ret;
1439 
1440     INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1441     mutex_lock(&rdev->pm.mutex);
1442     radeon_dpm_init(rdev);
1443     rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1444     if (radeon_dpm == 1)
1445         radeon_dpm_print_power_states(rdev);
1446     radeon_dpm_setup_asic(rdev);
1447     ret = radeon_dpm_enable(rdev);
1448     mutex_unlock(&rdev->pm.mutex);
1449     if (ret)
1450         goto dpm_failed;
1451     rdev->pm.dpm_enabled = true;
1452 
1453     radeon_debugfs_pm_init(rdev);
1454 
1455     DRM_INFO("radeon: dpm initialized\n");
1456 
1457     return 0;
1458 
1459 dpm_failed:
1460     rdev->pm.dpm_enabled = false;
1461     if ((rdev->family >= CHIP_BARTS) &&
1462         (rdev->family <= CHIP_CAYMAN) &&
1463         rdev->mc_fw) {
1464         if (rdev->pm.default_vddc)
1465             radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1466                         SET_VOLTAGE_TYPE_ASIC_VDDC);
1467         if (rdev->pm.default_vddci)
1468             radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1469                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
1470         if (rdev->pm.default_sclk)
1471             radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1472         if (rdev->pm.default_mclk)
1473             radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1474     }
1475     DRM_ERROR("radeon: dpm initialization failed\n");
1476     return ret;
1477 }
1478 
1479 struct radeon_dpm_quirk {
1480     u32 chip_vendor;
1481     u32 chip_device;
1482     u32 subsys_vendor;
1483     u32 subsys_device;
1484 };
1485 
1486 /* cards with dpm stability problems */
1487 static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = {
1488     /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */
1489     { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 },
1490     /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */
1491     { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 },
1492     { 0, 0, 0, 0 },
1493 };
1494 
1495 int radeon_pm_init(struct radeon_device *rdev)
1496 {
1497     struct radeon_dpm_quirk *p = radeon_dpm_quirk_list;
1498     bool disable_dpm = false;
1499 
1500     /* Apply dpm quirks */
1501     while (p && p->chip_device != 0) {
1502         if (rdev->pdev->vendor == p->chip_vendor &&
1503             rdev->pdev->device == p->chip_device &&
1504             rdev->pdev->subsystem_vendor == p->subsys_vendor &&
1505             rdev->pdev->subsystem_device == p->subsys_device) {
1506             disable_dpm = true;
1507             break;
1508         }
1509         ++p;
1510     }
1511 
1512     /* enable dpm on rv6xx+ */
1513     switch (rdev->family) {
1514     case CHIP_RV610:
1515     case CHIP_RV630:
1516     case CHIP_RV620:
1517     case CHIP_RV635:
1518     case CHIP_RV670:
1519     case CHIP_RS780:
1520     case CHIP_RS880:
1521     case CHIP_RV770:
1522         /* DPM requires the RLC, RV770+ dGPU requires SMC */
1523         if (!rdev->rlc_fw)
1524             rdev->pm.pm_method = PM_METHOD_PROFILE;
1525         else if ((rdev->family >= CHIP_RV770) &&
1526              (!(rdev->flags & RADEON_IS_IGP)) &&
1527              (!rdev->smc_fw))
1528             rdev->pm.pm_method = PM_METHOD_PROFILE;
1529         else if (radeon_dpm == 1)
1530             rdev->pm.pm_method = PM_METHOD_DPM;
1531         else
1532             rdev->pm.pm_method = PM_METHOD_PROFILE;
1533         break;
1534     case CHIP_RV730:
1535     case CHIP_RV710:
1536     case CHIP_RV740:
1537     case CHIP_CEDAR:
1538     case CHIP_REDWOOD:
1539     case CHIP_JUNIPER:
1540     case CHIP_CYPRESS:
1541     case CHIP_HEMLOCK:
1542     case CHIP_PALM:
1543     case CHIP_SUMO:
1544     case CHIP_SUMO2:
1545     case CHIP_BARTS:
1546     case CHIP_TURKS:
1547     case CHIP_CAICOS:
1548     case CHIP_CAYMAN:
1549     case CHIP_ARUBA:
1550     case CHIP_TAHITI:
1551     case CHIP_PITCAIRN:
1552     case CHIP_VERDE:
1553     case CHIP_OLAND:
1554     case CHIP_HAINAN:
1555     case CHIP_BONAIRE:
1556     case CHIP_KABINI:
1557     case CHIP_KAVERI:
1558     case CHIP_HAWAII:
1559     case CHIP_MULLINS:
1560         /* DPM requires the RLC, RV770+ dGPU requires SMC */
1561         if (!rdev->rlc_fw)
1562             rdev->pm.pm_method = PM_METHOD_PROFILE;
1563         else if ((rdev->family >= CHIP_RV770) &&
1564              (!(rdev->flags & RADEON_IS_IGP)) &&
1565              (!rdev->smc_fw))
1566             rdev->pm.pm_method = PM_METHOD_PROFILE;
1567         else if (disable_dpm && (radeon_dpm == -1))
1568             rdev->pm.pm_method = PM_METHOD_PROFILE;
1569         else if (radeon_dpm == 0)
1570             rdev->pm.pm_method = PM_METHOD_PROFILE;
1571         else
1572             rdev->pm.pm_method = PM_METHOD_DPM;
1573         break;
1574     default:
1575         /* default to profile method */
1576         rdev->pm.pm_method = PM_METHOD_PROFILE;
1577         break;
1578     }
1579 
1580     if (rdev->pm.pm_method == PM_METHOD_DPM)
1581         return radeon_pm_init_dpm(rdev);
1582     else
1583         return radeon_pm_init_old(rdev);
1584 }
1585 
1586 int radeon_pm_late_init(struct radeon_device *rdev)
1587 {
1588     int ret = 0;
1589 
1590     if (rdev->pm.pm_method == PM_METHOD_DPM) {
1591         if (rdev->pm.dpm_enabled) {
1592             if (!rdev->pm.sysfs_initialized) {
1593                 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1594                 if (ret)
1595                     DRM_ERROR("failed to create device file for dpm state\n");
1596                 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1597                 if (ret)
1598                     DRM_ERROR("failed to create device file for dpm state\n");
1599                 /* XXX: these are noops for dpm but are here for backwards compat */
1600                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1601                 if (ret)
1602                     DRM_ERROR("failed to create device file for power profile\n");
1603                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1604                 if (ret)
1605                     DRM_ERROR("failed to create device file for power method\n");
1606                 rdev->pm.sysfs_initialized = true;
1607             }
1608 
1609             mutex_lock(&rdev->pm.mutex);
1610             ret = radeon_dpm_late_enable(rdev);
1611             mutex_unlock(&rdev->pm.mutex);
1612             if (ret) {
1613                 rdev->pm.dpm_enabled = false;
1614                 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1615             } else {
1616                 /* set the dpm state for PX since there won't be
1617                  * a modeset to call this.
1618                  */
1619                 radeon_pm_compute_clocks(rdev);
1620             }
1621         }
1622     } else {
1623         if ((rdev->pm.num_power_states > 1) &&
1624             (!rdev->pm.sysfs_initialized)) {
1625             /* where's the best place to put these? */
1626             ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1627             if (ret)
1628                 DRM_ERROR("failed to create device file for power profile\n");
1629             ret = device_create_file(rdev->dev, &dev_attr_power_method);
1630             if (ret)
1631                 DRM_ERROR("failed to create device file for power method\n");
1632             else
1633                 rdev->pm.sysfs_initialized = true;
1634         }
1635     }
1636     return ret;
1637 }
1638 
1639 static void radeon_pm_fini_old(struct radeon_device *rdev)
1640 {
1641     if (rdev->pm.num_power_states > 1) {
1642         mutex_lock(&rdev->pm.mutex);
1643         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1644             rdev->pm.profile = PM_PROFILE_DEFAULT;
1645             radeon_pm_update_profile(rdev);
1646             radeon_pm_set_clocks(rdev);
1647         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1648             /* reset default clocks */
1649             rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1650             rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1651             radeon_pm_set_clocks(rdev);
1652         }
1653         mutex_unlock(&rdev->pm.mutex);
1654 
1655         cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1656 
1657         device_remove_file(rdev->dev, &dev_attr_power_profile);
1658         device_remove_file(rdev->dev, &dev_attr_power_method);
1659     }
1660 
1661     radeon_hwmon_fini(rdev);
1662     kfree(rdev->pm.power_state);
1663 }
1664 
1665 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1666 {
1667     if (rdev->pm.num_power_states > 1) {
1668         mutex_lock(&rdev->pm.mutex);
1669         radeon_dpm_disable(rdev);
1670         mutex_unlock(&rdev->pm.mutex);
1671 
1672         device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1673         device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1674         /* XXX backwards compat */
1675         device_remove_file(rdev->dev, &dev_attr_power_profile);
1676         device_remove_file(rdev->dev, &dev_attr_power_method);
1677     }
1678     radeon_dpm_fini(rdev);
1679 
1680     radeon_hwmon_fini(rdev);
1681     kfree(rdev->pm.power_state);
1682 }
1683 
1684 void radeon_pm_fini(struct radeon_device *rdev)
1685 {
1686     if (rdev->pm.pm_method == PM_METHOD_DPM)
1687         radeon_pm_fini_dpm(rdev);
1688     else
1689         radeon_pm_fini_old(rdev);
1690 }
1691 
1692 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1693 {
1694     struct drm_device *ddev = rdev->ddev;
1695     struct drm_crtc *crtc;
1696     struct radeon_crtc *radeon_crtc;
1697 
1698     if (rdev->pm.num_power_states < 2)
1699         return;
1700 
1701     mutex_lock(&rdev->pm.mutex);
1702 
1703     rdev->pm.active_crtcs = 0;
1704     rdev->pm.active_crtc_count = 0;
1705     if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1706         list_for_each_entry(crtc,
1707                     &ddev->mode_config.crtc_list, head) {
1708             radeon_crtc = to_radeon_crtc(crtc);
1709             if (radeon_crtc->enabled) {
1710                 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1711                 rdev->pm.active_crtc_count++;
1712             }
1713         }
1714     }
1715 
1716     if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1717         radeon_pm_update_profile(rdev);
1718         radeon_pm_set_clocks(rdev);
1719     } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1720         if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1721             if (rdev->pm.active_crtc_count > 1) {
1722                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1723                     cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1724 
1725                     rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1726                     rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1727                     radeon_pm_get_dynpm_state(rdev);
1728                     radeon_pm_set_clocks(rdev);
1729 
1730                     DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1731                 }
1732             } else if (rdev->pm.active_crtc_count == 1) {
1733                 /* TODO: Increase clocks if needed for current mode */
1734 
1735                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1736                     rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1737                     rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1738                     radeon_pm_get_dynpm_state(rdev);
1739                     radeon_pm_set_clocks(rdev);
1740 
1741                     schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1742                                   msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1743                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1744                     rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1745                     schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1746                                   msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1747                     DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1748                 }
1749             } else { /* count == 0 */
1750                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1751                     cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1752 
1753                     rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1754                     rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1755                     radeon_pm_get_dynpm_state(rdev);
1756                     radeon_pm_set_clocks(rdev);
1757                 }
1758             }
1759         }
1760     }
1761 
1762     mutex_unlock(&rdev->pm.mutex);
1763 }
1764 
1765 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1766 {
1767     struct drm_device *ddev = rdev->ddev;
1768     struct drm_crtc *crtc;
1769     struct radeon_crtc *radeon_crtc;
1770     struct radeon_connector *radeon_connector;
1771 
1772     if (!rdev->pm.dpm_enabled)
1773         return;
1774 
1775     mutex_lock(&rdev->pm.mutex);
1776 
1777     /* update active crtc counts */
1778     rdev->pm.dpm.new_active_crtcs = 0;
1779     rdev->pm.dpm.new_active_crtc_count = 0;
1780     rdev->pm.dpm.high_pixelclock_count = 0;
1781     if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1782         list_for_each_entry(crtc,
1783                     &ddev->mode_config.crtc_list, head) {
1784             radeon_crtc = to_radeon_crtc(crtc);
1785             if (crtc->enabled) {
1786                 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1787                 rdev->pm.dpm.new_active_crtc_count++;
1788                 if (!radeon_crtc->connector)
1789                     continue;
1790 
1791                 radeon_connector = to_radeon_connector(radeon_crtc->connector);
1792                 if (radeon_connector->pixelclock_for_modeset > 297000)
1793                     rdev->pm.dpm.high_pixelclock_count++;
1794             }
1795         }
1796     }
1797 
1798     /* update battery/ac status */
1799     if (power_supply_is_system_supplied() > 0)
1800         rdev->pm.dpm.ac_power = true;
1801     else
1802         rdev->pm.dpm.ac_power = false;
1803 
1804     radeon_dpm_change_power_state_locked(rdev);
1805 
1806     mutex_unlock(&rdev->pm.mutex);
1807 
1808 }
1809 
1810 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1811 {
1812     if (rdev->pm.pm_method == PM_METHOD_DPM)
1813         radeon_pm_compute_clocks_dpm(rdev);
1814     else
1815         radeon_pm_compute_clocks_old(rdev);
1816 }
1817 
1818 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1819 {
1820     int  crtc, vpos, hpos, vbl_status;
1821     bool in_vbl = true;
1822 
1823     /* Iterate over all active crtc's. All crtc's must be in vblank,
1824      * otherwise return in_vbl == false.
1825      */
1826     for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1827         if (rdev->pm.active_crtcs & (1 << crtc)) {
1828             vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev,
1829                                 crtc,
1830                                 USE_REAL_VBLANKSTART,
1831                                 &vpos, &hpos, NULL, NULL,
1832                                 &rdev->mode_info.crtcs[crtc]->base.hwmode);
1833             if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1834                 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK))
1835                 in_vbl = false;
1836         }
1837     }
1838 
1839     return in_vbl;
1840 }
1841 
1842 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1843 {
1844     u32 stat_crtc = 0;
1845     bool in_vbl = radeon_pm_in_vbl(rdev);
1846 
1847     if (!in_vbl)
1848         DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1849              finish ? "exit" : "entry");
1850     return in_vbl;
1851 }
1852 
1853 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1854 {
1855     struct radeon_device *rdev;
1856     int resched;
1857     rdev = container_of(work, struct radeon_device,
1858                 pm.dynpm_idle_work.work);
1859 
1860     resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1861     mutex_lock(&rdev->pm.mutex);
1862     if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1863         int not_processed = 0;
1864         int i;
1865 
1866         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1867             struct radeon_ring *ring = &rdev->ring[i];
1868 
1869             if (ring->ready) {
1870                 not_processed += radeon_fence_count_emitted(rdev, i);
1871                 if (not_processed >= 3)
1872                     break;
1873             }
1874         }
1875 
1876         if (not_processed >= 3) { /* should upclock */
1877             if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1878                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1879             } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1880                    rdev->pm.dynpm_can_upclock) {
1881                 rdev->pm.dynpm_planned_action =
1882                     DYNPM_ACTION_UPCLOCK;
1883                 rdev->pm.dynpm_action_timeout = jiffies +
1884                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1885             }
1886         } else if (not_processed == 0) { /* should downclock */
1887             if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1888                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1889             } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1890                    rdev->pm.dynpm_can_downclock) {
1891                 rdev->pm.dynpm_planned_action =
1892                     DYNPM_ACTION_DOWNCLOCK;
1893                 rdev->pm.dynpm_action_timeout = jiffies +
1894                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1895             }
1896         }
1897 
1898         /* Note, radeon_pm_set_clocks is called with static_switch set
1899          * to false since we want to wait for vbl to avoid flicker.
1900          */
1901         if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1902             jiffies > rdev->pm.dynpm_action_timeout) {
1903             radeon_pm_get_dynpm_state(rdev);
1904             radeon_pm_set_clocks(rdev);
1905         }
1906 
1907         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1908                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1909     }
1910     mutex_unlock(&rdev->pm.mutex);
1911     ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1912 }
1913 
1914 /*
1915  * Debugfs info
1916  */
1917 #if defined(CONFIG_DEBUG_FS)
1918 
1919 static int radeon_debugfs_pm_info_show(struct seq_file *m, void *unused)
1920 {
1921     struct radeon_device *rdev = (struct radeon_device *)m->private;
1922     struct drm_device *ddev = rdev->ddev;
1923 
1924     if  ((rdev->flags & RADEON_IS_PX) &&
1925          (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1926         seq_printf(m, "PX asic powered off\n");
1927     } else if (rdev->pm.dpm_enabled) {
1928         mutex_lock(&rdev->pm.mutex);
1929         if (rdev->asic->dpm.debugfs_print_current_performance_level)
1930             radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1931         else
1932             seq_printf(m, "Debugfs support not implemented for this asic\n");
1933         mutex_unlock(&rdev->pm.mutex);
1934     } else {
1935         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1936         /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1937         if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1938             seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1939         else
1940             seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1941         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1942         if (rdev->asic->pm.get_memory_clock)
1943             seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1944         if (rdev->pm.current_vddc)
1945             seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1946         if (rdev->asic->pm.get_pcie_lanes)
1947             seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1948     }
1949 
1950     return 0;
1951 }
1952 
1953 DEFINE_SHOW_ATTRIBUTE(radeon_debugfs_pm_info);
1954 #endif
1955 
1956 static void radeon_debugfs_pm_init(struct radeon_device *rdev)
1957 {
1958 #if defined(CONFIG_DEBUG_FS)
1959     struct dentry *root = rdev->ddev->primary->debugfs_root;
1960 
1961     debugfs_create_file("radeon_pm_info", 0444, root, rdev,
1962                 &radeon_debugfs_pm_info_fops);
1963 
1964 #endif
1965 }
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