drm/radeon/radeon_object.h

0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  * Copyright 2009 Jerome Glisse.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors: Dave Airlie
0025  *          Alex Deucher
0026  *          Jerome Glisse
0027  */
0028 #ifndef __RADEON_OBJECT_H__
0029 #define __RADEON_OBJECT_H__
0030
0031 #include <drm/radeon_drm.h>
0032 #include "radeon.h"
0033
0034 /**
0035  * radeon_mem_type_to_domain - return domain corresponding to mem_type
0036  * @mem_type:   ttm memory type
0037  *
0038  * Returns corresponding domain of the ttm mem_type
0039  */
0040 static inline unsigned radeon_mem_type_to_domain(u32 mem_type)
0041 {
0042     switch (mem_type) {
0043     case TTM_PL_VRAM:
0044         return RADEON_GEM_DOMAIN_VRAM;
0045     case TTM_PL_TT:
0046         return RADEON_GEM_DOMAIN_GTT;
0047     case TTM_PL_SYSTEM:
0048         return RADEON_GEM_DOMAIN_CPU;
0049     default:
0050         break;
0051     }
0052     return 0;
0053 }
0054
0055 /**
0056  * radeon_bo_reserve - reserve bo
0057  * @bo:     bo structure
0058  * @no_intr:    don't return -ERESTARTSYS on pending signal
0059  *
0060  * Returns:
0061  * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
0062  * a signal. Release all buffer reservations and return to user-space.
0063  */
0064 static inline int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr)
0065 {
0066     int r;
0067
0068     r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
0069     if (unlikely(r != 0)) {
0070         if (r != -ERESTARTSYS)
0071             dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
0072         return r;
0073     }
0074     return 0;
0075 }
0076
0077 static inline void radeon_bo_unreserve(struct radeon_bo *bo)
0078 {
0079     ttm_bo_unreserve(&bo->tbo);
0080 }
0081
0082 /**
0083  * radeon_bo_gpu_offset - return GPU offset of bo
0084  * @bo: radeon object for which we query the offset
0085  *
0086  * Returns current GPU offset of the object.
0087  *
0088  * Note: object should either be pinned or reserved when calling this
0089  * function, it might be useful to add check for this for debugging.
0090  */
0091 static inline u64 radeon_bo_gpu_offset(struct radeon_bo *bo)
0092 {
0093     struct radeon_device *rdev;
0094     u64 start = 0;
0095
0096     rdev = radeon_get_rdev(bo->tbo.bdev);
0097
0098     switch (bo->tbo.resource->mem_type) {
0099     case TTM_PL_TT:
0100         start = rdev->mc.gtt_start;
0101         break;
0102     case TTM_PL_VRAM:
0103         start = rdev->mc.vram_start;
0104         break;
0105     }
0106
0107     return (bo->tbo.resource->start << PAGE_SHIFT) + start;
0108 }
0109
0110 static inline unsigned long radeon_bo_size(struct radeon_bo *bo)
0111 {
0112     return bo->tbo.base.size;
0113 }
0114
0115 static inline unsigned radeon_bo_ngpu_pages(struct radeon_bo *bo)
0116 {
0117     return bo->tbo.base.size / RADEON_GPU_PAGE_SIZE;
0118 }
0119
0120 static inline unsigned radeon_bo_gpu_page_alignment(struct radeon_bo *bo)
0121 {
0122     return (bo->tbo.page_alignment << PAGE_SHIFT) / RADEON_GPU_PAGE_SIZE;
0123 }
0124
0125 /**
0126  * radeon_bo_mmap_offset - return mmap offset of bo
0127  * @bo: radeon object for which we query the offset
0128  *
0129  * Returns mmap offset of the object.
0130  */
0131 static inline u64 radeon_bo_mmap_offset(struct radeon_bo *bo)
0132 {
0133     return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
0134 }
0135
0136 extern int radeon_bo_create(struct radeon_device *rdev,
0137                 unsigned long size, int byte_align,
0138                 bool kernel, u32 domain, u32 flags,
0139                 struct sg_table *sg,
0140                 struct dma_resv *resv,
0141                 struct radeon_bo **bo_ptr);
0142 extern int radeon_bo_kmap(struct radeon_bo *bo, void **ptr);
0143 extern void radeon_bo_kunmap(struct radeon_bo *bo);
0144 extern struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo);
0145 extern void radeon_bo_unref(struct radeon_bo **bo);
0146 extern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr);
0147 extern int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain,
0148                     u64 max_offset, u64 *gpu_addr);
0149 extern void radeon_bo_unpin(struct radeon_bo *bo);
0150 extern int radeon_bo_evict_vram(struct radeon_device *rdev);
0151 extern void radeon_bo_force_delete(struct radeon_device *rdev);
0152 extern int radeon_bo_init(struct radeon_device *rdev);
0153 extern void radeon_bo_fini(struct radeon_device *rdev);
0154 extern int radeon_bo_list_validate(struct radeon_device *rdev,
0155                    struct ww_acquire_ctx *ticket,
0156                    struct list_head *head, int ring);
0157 extern int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
0158                 u32 tiling_flags, u32 pitch);
0159 extern void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
0160                 u32 *tiling_flags, u32 *pitch);
0161 extern int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
0162                 bool force_drop);
0163 extern void radeon_bo_move_notify(struct ttm_buffer_object *bo);
0164 extern vm_fault_t radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
0165 extern int radeon_bo_get_surface_reg(struct radeon_bo *bo);
0166 extern void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
0167                 bool shared);
0168
0169 /*
0170  * sub allocation
0171  */
0172
0173 static inline uint64_t radeon_sa_bo_gpu_addr(struct radeon_sa_bo *sa_bo)
0174 {
0175     return sa_bo->manager->gpu_addr + sa_bo->soffset;
0176 }
0177
0178 static inline void * radeon_sa_bo_cpu_addr(struct radeon_sa_bo *sa_bo)
0179 {
0180     return sa_bo->manager->cpu_ptr + sa_bo->soffset;
0181 }
0182
0183 extern int radeon_sa_bo_manager_init(struct radeon_device *rdev,
0184                      struct radeon_sa_manager *sa_manager,
0185                      unsigned size, u32 align, u32 domain,
0186                      u32 flags);
0187 extern void radeon_sa_bo_manager_fini(struct radeon_device *rdev,
0188                       struct radeon_sa_manager *sa_manager);
0189 extern int radeon_sa_bo_manager_start(struct radeon_device *rdev,
0190                       struct radeon_sa_manager *sa_manager);
0191 extern int radeon_sa_bo_manager_suspend(struct radeon_device *rdev,
0192                     struct radeon_sa_manager *sa_manager);
0193 extern int radeon_sa_bo_new(struct radeon_device *rdev,
0194                 struct radeon_sa_manager *sa_manager,
0195                 struct radeon_sa_bo **sa_bo,
0196                 unsigned size, unsigned align);
0197 extern void radeon_sa_bo_free(struct radeon_device *rdev,
0198                   struct radeon_sa_bo **sa_bo,
0199                   struct radeon_fence *fence);
0200 #if defined(CONFIG_DEBUG_FS)
0201 extern void radeon_sa_bo_dump_debug_info(struct radeon_sa_manager *sa_manager,
0202                      struct seq_file *m);
0203 #endif
0204
0205
0206 #endif