Back to home page

OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
0003  *                VA Linux Systems Inc., Fremont, California.
0004  * Copyright 2008 Red Hat Inc.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Original Authors:
0025  *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
0026  *
0027  * Kernel port Author: Dave Airlie
0028  */
0029 
0030 #ifndef RADEON_MODE_H
0031 #define RADEON_MODE_H
0032 
0033 #include <drm/display/drm_dp_helper.h>
0034 #include <drm/display/drm_dp_mst_helper.h>
0035 #include <drm/drm_crtc.h>
0036 #include <drm/drm_edid.h>
0037 #include <drm/drm_encoder.h>
0038 #include <drm/drm_fixed.h>
0039 #include <drm/drm_crtc_helper.h>
0040 #include <linux/i2c.h>
0041 #include <linux/i2c-algo-bit.h>
0042 
0043 struct radeon_bo;
0044 struct radeon_device;
0045 
0046 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
0047 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
0048 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
0049 
0050 #define RADEON_MAX_HPD_PINS 7
0051 #define RADEON_MAX_CRTCS 6
0052 #define RADEON_MAX_AFMT_BLOCKS 7
0053 
0054 enum radeon_rmx_type {
0055     RMX_OFF,
0056     RMX_FULL,
0057     RMX_CENTER,
0058     RMX_ASPECT
0059 };
0060 
0061 enum radeon_tv_std {
0062     TV_STD_NTSC,
0063     TV_STD_PAL,
0064     TV_STD_PAL_M,
0065     TV_STD_PAL_60,
0066     TV_STD_NTSC_J,
0067     TV_STD_SCART_PAL,
0068     TV_STD_SECAM,
0069     TV_STD_PAL_CN,
0070     TV_STD_PAL_N,
0071 };
0072 
0073 enum radeon_underscan_type {
0074     UNDERSCAN_OFF,
0075     UNDERSCAN_ON,
0076     UNDERSCAN_AUTO,
0077 };
0078 
0079 enum radeon_hpd_id {
0080     RADEON_HPD_1 = 0,
0081     RADEON_HPD_2,
0082     RADEON_HPD_3,
0083     RADEON_HPD_4,
0084     RADEON_HPD_5,
0085     RADEON_HPD_6,
0086     RADEON_HPD_NONE = 0xff,
0087 };
0088 
0089 enum radeon_output_csc {
0090     RADEON_OUTPUT_CSC_BYPASS = 0,
0091     RADEON_OUTPUT_CSC_TVRGB = 1,
0092     RADEON_OUTPUT_CSC_YCBCR601 = 2,
0093     RADEON_OUTPUT_CSC_YCBCR709 = 3,
0094 };
0095 
0096 #define RADEON_MAX_I2C_BUS 16
0097 
0098 /* radeon gpio-based i2c
0099  * 1. "mask" reg and bits
0100  *    grabs the gpio pins for software use
0101  *    0=not held  1=held
0102  * 2. "a" reg and bits
0103  *    output pin value
0104  *    0=low 1=high
0105  * 3. "en" reg and bits
0106  *    sets the pin direction
0107  *    0=input 1=output
0108  * 4. "y" reg and bits
0109  *    input pin value
0110  *    0=low 1=high
0111  */
0112 struct radeon_i2c_bus_rec {
0113     bool valid;
0114     /* id used by atom */
0115     uint8_t i2c_id;
0116     /* id used by atom */
0117     enum radeon_hpd_id hpd;
0118     /* can be used with hw i2c engine */
0119     bool hw_capable;
0120     /* uses multi-media i2c engine */
0121     bool mm_i2c;
0122     /* regs and bits */
0123     uint32_t mask_clk_reg;
0124     uint32_t mask_data_reg;
0125     uint32_t a_clk_reg;
0126     uint32_t a_data_reg;
0127     uint32_t en_clk_reg;
0128     uint32_t en_data_reg;
0129     uint32_t y_clk_reg;
0130     uint32_t y_data_reg;
0131     uint32_t mask_clk_mask;
0132     uint32_t mask_data_mask;
0133     uint32_t a_clk_mask;
0134     uint32_t a_data_mask;
0135     uint32_t en_clk_mask;
0136     uint32_t en_data_mask;
0137     uint32_t y_clk_mask;
0138     uint32_t y_data_mask;
0139 };
0140 
0141 struct radeon_tmds_pll {
0142     uint32_t freq;
0143     uint32_t value;
0144 };
0145 
0146 #define RADEON_MAX_BIOS_CONNECTOR 16
0147 
0148 /* pll flags */
0149 #define RADEON_PLL_USE_BIOS_DIVS        (1 << 0)
0150 #define RADEON_PLL_NO_ODD_POST_DIV      (1 << 1)
0151 #define RADEON_PLL_USE_REF_DIV          (1 << 2)
0152 #define RADEON_PLL_LEGACY               (1 << 3)
0153 #define RADEON_PLL_PREFER_LOW_REF_DIV   (1 << 4)
0154 #define RADEON_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
0155 #define RADEON_PLL_PREFER_LOW_FB_DIV    (1 << 6)
0156 #define RADEON_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
0157 #define RADEON_PLL_PREFER_LOW_POST_DIV  (1 << 8)
0158 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
0159 #define RADEON_PLL_USE_FRAC_FB_DIV      (1 << 10)
0160 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
0161 #define RADEON_PLL_USE_POST_DIV         (1 << 12)
0162 #define RADEON_PLL_IS_LCD               (1 << 13)
0163 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
0164 
0165 struct radeon_pll {
0166     /* reference frequency */
0167     uint32_t reference_freq;
0168 
0169     /* fixed dividers */
0170     uint32_t reference_div;
0171     uint32_t post_div;
0172 
0173     /* pll in/out limits */
0174     uint32_t pll_in_min;
0175     uint32_t pll_in_max;
0176     uint32_t pll_out_min;
0177     uint32_t pll_out_max;
0178     uint32_t lcd_pll_out_min;
0179     uint32_t lcd_pll_out_max;
0180     uint32_t best_vco;
0181 
0182     /* divider limits */
0183     uint32_t min_ref_div;
0184     uint32_t max_ref_div;
0185     uint32_t min_post_div;
0186     uint32_t max_post_div;
0187     uint32_t min_feedback_div;
0188     uint32_t max_feedback_div;
0189     uint32_t min_frac_feedback_div;
0190     uint32_t max_frac_feedback_div;
0191 
0192     /* flags for the current clock */
0193     uint32_t flags;
0194 
0195     /* pll id */
0196     uint32_t id;
0197 };
0198 
0199 struct radeon_i2c_chan {
0200     struct i2c_adapter adapter;
0201     struct drm_device *dev;
0202     struct i2c_algo_bit_data bit;
0203     struct radeon_i2c_bus_rec rec;
0204     struct drm_dp_aux aux;
0205     bool has_aux;
0206     struct mutex mutex;
0207 };
0208 
0209 /* mostly for macs, but really any system without connector tables */
0210 enum radeon_connector_table {
0211     CT_NONE = 0,
0212     CT_GENERIC,
0213     CT_IBOOK,
0214     CT_POWERBOOK_EXTERNAL,
0215     CT_POWERBOOK_INTERNAL,
0216     CT_POWERBOOK_VGA,
0217     CT_MINI_EXTERNAL,
0218     CT_MINI_INTERNAL,
0219     CT_IMAC_G5_ISIGHT,
0220     CT_EMAC,
0221     CT_RN50_POWER,
0222     CT_MAC_X800,
0223     CT_MAC_G5_9600,
0224     CT_SAM440EP,
0225     CT_MAC_G4_SILVER
0226 };
0227 
0228 enum radeon_dvo_chip {
0229     DVO_SIL164,
0230     DVO_SIL1178,
0231 };
0232 
0233 struct radeon_fbdev;
0234 
0235 struct radeon_afmt {
0236     bool enabled;
0237     int offset;
0238     bool last_buffer_filled_status;
0239     int id;
0240 };
0241 
0242 struct radeon_mode_info {
0243     struct atom_context *atom_context;
0244     struct card_info *atom_card_info;
0245     enum radeon_connector_table connector_table;
0246     bool mode_config_initialized;
0247     struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];
0248     struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS];
0249     /* DVI-I properties */
0250     struct drm_property *coherent_mode_property;
0251     /* DAC enable load detect */
0252     struct drm_property *load_detect_property;
0253     /* TV standard */
0254     struct drm_property *tv_std_property;
0255     /* legacy TMDS PLL detect */
0256     struct drm_property *tmds_pll_property;
0257     /* underscan */
0258     struct drm_property *underscan_property;
0259     struct drm_property *underscan_hborder_property;
0260     struct drm_property *underscan_vborder_property;
0261     /* audio */
0262     struct drm_property *audio_property;
0263     /* FMT dithering */
0264     struct drm_property *dither_property;
0265     /* Output CSC */
0266     struct drm_property *output_csc_property;
0267     /* hardcoded DFP edid from BIOS */
0268     struct edid *bios_hardcoded_edid;
0269     int bios_hardcoded_edid_size;
0270 
0271     /* pointer to fbdev info structure */
0272     struct radeon_fbdev *rfbdev;
0273     /* firmware flags */
0274     u16 firmware_flags;
0275     /* pointer to backlight encoder */
0276     struct radeon_encoder *bl_encoder;
0277 
0278     /* bitmask for active encoder frontends */
0279     uint32_t active_encoders;
0280 };
0281 
0282 #define RADEON_MAX_BL_LEVEL 0xFF
0283 
0284 struct radeon_backlight_privdata {
0285     struct radeon_encoder *encoder;
0286     uint8_t negative;
0287 };
0288 
0289 #define MAX_H_CODE_TIMING_LEN 32
0290 #define MAX_V_CODE_TIMING_LEN 32
0291 
0292 /* need to store these as reading
0293    back code tables is excessive */
0294 struct radeon_tv_regs {
0295     uint32_t tv_uv_adr;
0296     uint32_t timing_cntl;
0297     uint32_t hrestart;
0298     uint32_t vrestart;
0299     uint32_t frestart;
0300     uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
0301     uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
0302 };
0303 
0304 struct radeon_atom_ss {
0305     uint16_t percentage;
0306     uint16_t percentage_divider;
0307     uint8_t type;
0308     uint16_t step;
0309     uint8_t delay;
0310     uint8_t range;
0311     uint8_t refdiv;
0312     /* asic_ss */
0313     uint16_t rate;
0314     uint16_t amount;
0315 };
0316 
0317 enum radeon_flip_status {
0318     RADEON_FLIP_NONE,
0319     RADEON_FLIP_PENDING,
0320     RADEON_FLIP_SUBMITTED
0321 };
0322 
0323 struct radeon_crtc {
0324     struct drm_crtc base;
0325     int crtc_id;
0326     bool enabled;
0327     bool can_tile;
0328     bool cursor_out_of_bounds;
0329     uint32_t crtc_offset;
0330     struct drm_gem_object *cursor_bo;
0331     uint64_t cursor_addr;
0332     int cursor_x;
0333     int cursor_y;
0334     int cursor_hot_x;
0335     int cursor_hot_y;
0336     int cursor_width;
0337     int cursor_height;
0338     int max_cursor_width;
0339     int max_cursor_height;
0340     uint32_t legacy_display_base_addr;
0341     enum radeon_rmx_type rmx_type;
0342     u8 h_border;
0343     u8 v_border;
0344     fixed20_12 vsc;
0345     fixed20_12 hsc;
0346     struct drm_display_mode native_mode;
0347     int pll_id;
0348     /* page flipping */
0349     struct workqueue_struct *flip_queue;
0350     struct radeon_flip_work *flip_work;
0351     enum radeon_flip_status flip_status;
0352     /* pll sharing */
0353     struct radeon_atom_ss ss;
0354     bool ss_enabled;
0355     u32 adjusted_clock;
0356     int bpc;
0357     u32 pll_reference_div;
0358     u32 pll_post_div;
0359     u32 pll_flags;
0360     struct drm_encoder *encoder;
0361     struct drm_connector *connector;
0362     /* for dpm */
0363     u32 line_time;
0364     u32 wm_low;
0365     u32 wm_high;
0366     u32 lb_vblank_lead_lines;
0367     struct drm_display_mode hw_mode;
0368     enum radeon_output_csc output_csc;
0369 };
0370 
0371 struct radeon_encoder_primary_dac {
0372     /* legacy primary dac */
0373     uint32_t ps2_pdac_adj;
0374 };
0375 
0376 struct radeon_encoder_lvds {
0377     /* legacy lvds */
0378     uint16_t panel_vcc_delay;
0379     uint8_t  panel_pwr_delay;
0380     uint8_t  panel_digon_delay;
0381     uint8_t  panel_blon_delay;
0382     uint16_t panel_ref_divider;
0383     uint8_t  panel_post_divider;
0384     uint16_t panel_fb_divider;
0385     bool     use_bios_dividers;
0386     uint32_t lvds_gen_cntl;
0387     /* panel mode */
0388     struct drm_display_mode native_mode;
0389     struct backlight_device *bl_dev;
0390     int      dpms_mode;
0391     uint8_t  backlight_level;
0392 };
0393 
0394 struct radeon_encoder_tv_dac {
0395     /* legacy tv dac */
0396     uint32_t ps2_tvdac_adj;
0397     uint32_t ntsc_tvdac_adj;
0398     uint32_t pal_tvdac_adj;
0399 
0400     int               h_pos;
0401     int               v_pos;
0402     int               h_size;
0403     int               supported_tv_stds;
0404     bool              tv_on;
0405     enum radeon_tv_std tv_std;
0406     struct radeon_tv_regs tv;
0407 };
0408 
0409 struct radeon_encoder_int_tmds {
0410     /* legacy int tmds */
0411     struct radeon_tmds_pll tmds_pll[4];
0412 };
0413 
0414 struct radeon_encoder_ext_tmds {
0415     /* tmds over dvo */
0416     struct radeon_i2c_chan *i2c_bus;
0417     uint8_t slave_addr;
0418     enum radeon_dvo_chip dvo_chip;
0419 };
0420 
0421 /* spread spectrum */
0422 struct radeon_encoder_atom_dig {
0423     bool linkb;
0424     /* atom dig */
0425     bool coherent_mode;
0426     int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
0427     /* atom lvds/edp */
0428     uint32_t lcd_misc;
0429     uint16_t panel_pwr_delay;
0430     uint32_t lcd_ss_id;
0431     /* panel mode */
0432     struct drm_display_mode native_mode;
0433     struct backlight_device *bl_dev;
0434     int dpms_mode;
0435     uint8_t backlight_level;
0436     int panel_mode;
0437     struct radeon_afmt *afmt;
0438     struct r600_audio_pin *pin;
0439     int active_mst_links;
0440 };
0441 
0442 struct radeon_encoder_atom_dac {
0443     enum radeon_tv_std tv_std;
0444 };
0445 
0446 struct radeon_encoder_mst {
0447     int crtc;
0448     struct radeon_encoder *primary;
0449     struct radeon_connector *connector;
0450     struct drm_dp_mst_port *port;
0451     int pbn;
0452     int fe;
0453     bool fe_from_be;
0454     bool enc_active;
0455 };
0456 
0457 struct radeon_encoder {
0458     struct drm_encoder base;
0459     uint32_t encoder_enum;
0460     uint32_t encoder_id;
0461     uint32_t devices;
0462     uint32_t active_device;
0463     uint32_t flags;
0464     uint32_t pixel_clock;
0465     enum radeon_rmx_type rmx_type;
0466     enum radeon_underscan_type underscan_type;
0467     uint32_t underscan_hborder;
0468     uint32_t underscan_vborder;
0469     struct drm_display_mode native_mode;
0470     void *enc_priv;
0471     int audio_polling_active;
0472     bool is_ext_encoder;
0473     u16 caps;
0474     struct radeon_audio_funcs *audio;
0475     enum radeon_output_csc output_csc;
0476     bool can_mst;
0477     uint32_t offset;
0478     bool is_mst_encoder;
0479     /* front end for this mst encoder */
0480 };
0481 
0482 struct radeon_connector_atom_dig {
0483     uint32_t igp_lane_info;
0484     /* displayport */
0485     u8 dpcd[DP_RECEIVER_CAP_SIZE];
0486     u8 dp_sink_type;
0487     int dp_clock;
0488     int dp_lane_count;
0489     bool edp_on;
0490     bool is_mst;
0491 };
0492 
0493 struct radeon_gpio_rec {
0494     bool valid;
0495     u8 id;
0496     u32 reg;
0497     u32 mask;
0498     u32 shift;
0499 };
0500 
0501 struct radeon_hpd {
0502     enum radeon_hpd_id hpd;
0503     u8 plugged_state;
0504     struct radeon_gpio_rec gpio;
0505 };
0506 
0507 struct radeon_router {
0508     u32 router_id;
0509     struct radeon_i2c_bus_rec i2c_info;
0510     u8 i2c_addr;
0511     /* i2c mux */
0512     bool ddc_valid;
0513     u8 ddc_mux_type;
0514     u8 ddc_mux_control_pin;
0515     u8 ddc_mux_state;
0516     /* clock/data mux */
0517     bool cd_valid;
0518     u8 cd_mux_type;
0519     u8 cd_mux_control_pin;
0520     u8 cd_mux_state;
0521 };
0522 
0523 enum radeon_connector_audio {
0524     RADEON_AUDIO_DISABLE = 0,
0525     RADEON_AUDIO_ENABLE = 1,
0526     RADEON_AUDIO_AUTO = 2
0527 };
0528 
0529 enum radeon_connector_dither {
0530     RADEON_FMT_DITHER_DISABLE = 0,
0531     RADEON_FMT_DITHER_ENABLE = 1,
0532 };
0533 
0534 struct stream_attribs {
0535     uint16_t fe;
0536     uint16_t slots;
0537 };
0538 
0539 struct radeon_connector {
0540     struct drm_connector base;
0541     uint32_t connector_id;
0542     uint32_t devices;
0543     struct radeon_i2c_chan *ddc_bus;
0544     /* some systems have an hdmi and vga port with a shared ddc line */
0545     bool shared_ddc;
0546     bool use_digital;
0547     /* we need to mind the EDID between detect
0548        and get modes due to analog/digital/tvencoder */
0549     struct edid *edid;
0550     void *con_priv;
0551     bool dac_load_detect;
0552     bool detected_by_load; /* if the connection status was determined by load */
0553     bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */
0554     uint16_t connector_object_id;
0555     struct radeon_hpd hpd;
0556     struct radeon_router router;
0557     struct radeon_i2c_chan *router_bus;
0558     enum radeon_connector_audio audio;
0559     enum radeon_connector_dither dither;
0560     int pixelclock_for_modeset;
0561     bool is_mst_connector;
0562     struct radeon_connector *mst_port;
0563     struct drm_dp_mst_port *port;
0564     struct drm_dp_mst_topology_mgr mst_mgr;
0565 
0566     struct radeon_encoder *mst_encoder;
0567     struct stream_attribs cur_stream_attribs[6];
0568     int enabled_attribs;
0569 };
0570 
0571 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
0572                 ((em) == ATOM_ENCODER_MODE_DP_MST))
0573 
0574 struct atom_clock_dividers {
0575     u32 post_div;
0576     union {
0577         struct {
0578 #ifdef __BIG_ENDIAN
0579             u32 reserved : 6;
0580             u32 whole_fb_div : 12;
0581             u32 frac_fb_div : 14;
0582 #else
0583             u32 frac_fb_div : 14;
0584             u32 whole_fb_div : 12;
0585             u32 reserved : 6;
0586 #endif
0587         };
0588         u32 fb_div;
0589     };
0590     u32 ref_div;
0591     bool enable_post_div;
0592     bool enable_dithen;
0593     u32 vco_mode;
0594     u32 real_clock;
0595     /* added for CI */
0596     u32 post_divider;
0597     u32 flags;
0598 };
0599 
0600 struct atom_mpll_param {
0601     union {
0602         struct {
0603 #ifdef __BIG_ENDIAN
0604             u32 reserved : 8;
0605             u32 clkfrac : 12;
0606             u32 clkf : 12;
0607 #else
0608             u32 clkf : 12;
0609             u32 clkfrac : 12;
0610             u32 reserved : 8;
0611 #endif
0612         };
0613         u32 fb_div;
0614     };
0615     u32 post_div;
0616     u32 bwcntl;
0617     u32 dll_speed;
0618     u32 vco_mode;
0619     u32 yclk_sel;
0620     u32 qdr;
0621     u32 half_rate;
0622 };
0623 
0624 #define MEM_TYPE_GDDR5  0x50
0625 #define MEM_TYPE_GDDR4  0x40
0626 #define MEM_TYPE_GDDR3  0x30
0627 #define MEM_TYPE_DDR2   0x20
0628 #define MEM_TYPE_GDDR1  0x10
0629 #define MEM_TYPE_DDR3   0xb0
0630 #define MEM_TYPE_MASK   0xf0
0631 
0632 struct atom_memory_info {
0633     u8 mem_vendor;
0634     u8 mem_type;
0635 };
0636 
0637 #define MAX_AC_TIMING_ENTRIES 16
0638 
0639 struct atom_memory_clock_range_table
0640 {
0641     u8 num_entries;
0642     u8 rsv[3];
0643     u32 mclk[MAX_AC_TIMING_ENTRIES];
0644 };
0645 
0646 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32
0647 #define VBIOS_MAX_AC_TIMING_ENTRIES 20
0648 
0649 struct atom_mc_reg_entry {
0650     u32 mclk_max;
0651     u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
0652 };
0653 
0654 struct atom_mc_register_address {
0655     u16 s1;
0656     u8 pre_reg_data;
0657 };
0658 
0659 struct atom_mc_reg_table {
0660     u8 last;
0661     u8 num_entries;
0662     struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
0663     struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
0664 };
0665 
0666 #define MAX_VOLTAGE_ENTRIES 32
0667 
0668 struct atom_voltage_table_entry
0669 {
0670     u16 value;
0671     u32 smio_low;
0672 };
0673 
0674 struct atom_voltage_table
0675 {
0676     u32 count;
0677     u32 mask_low;
0678     u32 phase_delay;
0679     struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
0680 };
0681 
0682 /* Driver internal use only flags of radeon_get_crtc_scanoutpos() */
0683 #define DRM_SCANOUTPOS_VALID        (1 << 0)
0684 #define DRM_SCANOUTPOS_IN_VBLANK    (1 << 1)
0685 #define DRM_SCANOUTPOS_ACCURATE     (1 << 2)
0686 #define USE_REAL_VBLANKSTART        (1 << 30)
0687 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
0688 
0689 extern void
0690 radeon_add_atom_connector(struct drm_device *dev,
0691               uint32_t connector_id,
0692               uint32_t supported_device,
0693               int connector_type,
0694               struct radeon_i2c_bus_rec *i2c_bus,
0695               uint32_t igp_lane_info,
0696               uint16_t connector_object_id,
0697               struct radeon_hpd *hpd,
0698               struct radeon_router *router);
0699 extern void
0700 radeon_add_legacy_connector(struct drm_device *dev,
0701                 uint32_t connector_id,
0702                 uint32_t supported_device,
0703                 int connector_type,
0704                 struct radeon_i2c_bus_rec *i2c_bus,
0705                 uint16_t connector_object_id,
0706                 struct radeon_hpd *hpd);
0707 extern uint32_t
0708 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
0709             uint8_t dac);
0710 extern void radeon_link_encoder_connector(struct drm_device *dev);
0711 
0712 extern enum radeon_tv_std
0713 radeon_combios_get_tv_info(struct radeon_device *rdev);
0714 extern enum radeon_tv_std
0715 radeon_atombios_get_tv_info(struct radeon_device *rdev);
0716 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
0717                          u16 *vddc, u16 *vddci, u16 *mvdd);
0718 
0719 extern void
0720 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
0721                       struct drm_encoder *encoder,
0722                       bool connected);
0723 extern void
0724 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
0725                        struct drm_encoder *encoder,
0726                        bool connected);
0727 
0728 extern struct drm_connector *
0729 radeon_get_connector_for_encoder(struct drm_encoder *encoder);
0730 extern struct drm_connector *
0731 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
0732 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
0733                     u32 pixel_clock);
0734 
0735 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
0736 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
0737 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
0738 extern int radeon_get_monitor_bpc(struct drm_connector *connector);
0739 
0740 extern struct edid *radeon_connector_edid(struct drm_connector *connector);
0741 
0742 extern void radeon_connector_hotplug(struct drm_connector *connector);
0743 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
0744                        struct drm_display_mode *mode);
0745 extern void radeon_dp_set_link_config(struct drm_connector *connector,
0746                       const struct drm_display_mode *mode);
0747 extern void radeon_dp_link_train(struct drm_encoder *encoder,
0748                  struct drm_connector *connector);
0749 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
0750 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
0751 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
0752 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
0753                     struct drm_connector *connector);
0754 extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
0755                      u8 power_state);
0756 extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
0757 extern ssize_t
0758 radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg);
0759 
0760 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
0761 extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override);
0762 extern void radeon_atom_encoder_init(struct radeon_device *rdev);
0763 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
0764 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
0765                        int action, uint8_t lane_num,
0766                        uint8_t lane_set);
0767 extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder,
0768                         int action, uint8_t lane_num,
0769                         uint8_t lane_set, int fe);
0770 extern void atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder,
0771                          int fe);
0772 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
0773 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
0774 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
0775 
0776 extern void radeon_i2c_init(struct radeon_device *rdev);
0777 extern void radeon_i2c_fini(struct radeon_device *rdev);
0778 extern void radeon_combios_i2c_init(struct radeon_device *rdev);
0779 extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
0780 extern void radeon_i2c_add(struct radeon_device *rdev,
0781                struct radeon_i2c_bus_rec *rec,
0782                const char *name);
0783 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
0784                          struct radeon_i2c_bus_rec *i2c_bus);
0785 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
0786                          struct radeon_i2c_bus_rec *rec,
0787                          const char *name);
0788 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
0789 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
0790                 u8 slave_addr,
0791                 u8 addr,
0792                 u8 *val);
0793 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
0794                 u8 slave_addr,
0795                 u8 addr,
0796                 u8 val);
0797 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
0798 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
0799 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
0800 
0801 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
0802                          struct radeon_atom_ss *ss,
0803                          int id);
0804 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
0805                          struct radeon_atom_ss *ss,
0806                          int id, u32 clock);
0807 extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
0808                               u8 id);
0809 
0810 extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
0811                       uint64_t freq,
0812                       uint32_t *dot_clock_p,
0813                       uint32_t *fb_div_p,
0814                       uint32_t *frac_fb_div_p,
0815                       uint32_t *ref_div_p,
0816                       uint32_t *post_div_p);
0817 
0818 extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
0819                      u32 freq,
0820                      u32 *dot_clock_p,
0821                      u32 *fb_div_p,
0822                      u32 *frac_fb_div_p,
0823                      u32 *ref_div_p,
0824                      u32 *post_div_p);
0825 
0826 extern void radeon_setup_encoder_clones(struct drm_device *dev);
0827 
0828 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
0829 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
0830 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
0831 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
0832 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
0833 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
0834 extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
0835 extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
0836 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
0837 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
0838 extern bool radeon_encoder_is_digital(struct drm_encoder *encoder);
0839 
0840 extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
0841 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
0842                    struct drm_framebuffer *old_fb);
0843 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
0844                      struct drm_framebuffer *fb,
0845                      int x, int y,
0846                      enum mode_set_atomic state);
0847 extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
0848                    struct drm_display_mode *mode,
0849                    struct drm_display_mode *adjusted_mode,
0850                    int x, int y,
0851                    struct drm_framebuffer *old_fb);
0852 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
0853 
0854 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
0855                  struct drm_framebuffer *old_fb);
0856 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
0857                        struct drm_framebuffer *fb,
0858                        int x, int y,
0859                        enum mode_set_atomic state);
0860 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
0861                    struct drm_framebuffer *fb,
0862                    int x, int y, int atomic);
0863 extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
0864                    struct drm_file *file_priv,
0865                    uint32_t handle,
0866                    uint32_t width,
0867                    uint32_t height,
0868                    int32_t hot_x,
0869                    int32_t hot_y);
0870 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
0871                    int x, int y);
0872 extern void radeon_cursor_reset(struct drm_crtc *crtc);
0873 
0874 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
0875                       unsigned int flags, int *vpos, int *hpos,
0876                       ktime_t *stime, ktime_t *etime,
0877                       const struct drm_display_mode *mode);
0878 
0879 extern bool
0880 radeon_get_crtc_scanout_position(struct drm_crtc *crtc, bool in_vblank_irq,
0881                  int *vpos, int *hpos,
0882                  ktime_t *stime, ktime_t *etime,
0883                  const struct drm_display_mode *mode);
0884 
0885 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
0886 extern struct edid *
0887 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
0888 extern bool radeon_atom_get_clock_info(struct drm_device *dev);
0889 extern bool radeon_combios_get_clock_info(struct drm_device *dev);
0890 extern struct radeon_encoder_atom_dig *
0891 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
0892 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
0893                       struct radeon_encoder_int_tmds *tmds);
0894 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
0895                              struct radeon_encoder_int_tmds *tmds);
0896 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
0897                            struct radeon_encoder_int_tmds *tmds);
0898 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
0899                              struct radeon_encoder_ext_tmds *tmds);
0900 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
0901                                struct radeon_encoder_ext_tmds *tmds);
0902 extern struct radeon_encoder_primary_dac *
0903 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
0904 extern struct radeon_encoder_tv_dac *
0905 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
0906 extern struct radeon_encoder_lvds *
0907 radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
0908 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
0909 extern struct radeon_encoder_tv_dac *
0910 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
0911 extern struct radeon_encoder_primary_dac *
0912 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
0913 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
0914 extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
0915 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
0916 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
0917 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
0918 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
0919 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
0920 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
0921 extern void
0922 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
0923 extern void
0924 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
0925 extern void
0926 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
0927 extern void
0928 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
0929 int radeon_framebuffer_init(struct drm_device *dev,
0930                  struct drm_framebuffer *rfb,
0931                  const struct drm_mode_fb_cmd2 *mode_cmd,
0932                  struct drm_gem_object *obj);
0933 
0934 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
0935 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
0936 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
0937 void radeon_atombios_init_crtc(struct drm_device *dev,
0938                    struct radeon_crtc *radeon_crtc);
0939 void radeon_legacy_init_crtc(struct drm_device *dev,
0940                  struct radeon_crtc *radeon_crtc);
0941 
0942 void radeon_get_clock_info(struct drm_device *dev);
0943 
0944 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
0945 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
0946 
0947 void radeon_enc_destroy(struct drm_encoder *encoder);
0948 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
0949 void radeon_combios_asic_init(struct drm_device *dev);
0950 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
0951                     const struct drm_display_mode *mode,
0952                     struct drm_display_mode *adjusted_mode);
0953 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
0954                  struct drm_display_mode *adjusted_mode);
0955 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
0956 
0957 /* legacy tv */
0958 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
0959                       uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
0960                       uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
0961 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
0962                   uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
0963                   uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
0964 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
0965                   uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
0966                   uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
0967 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
0968                    struct drm_display_mode *mode,
0969                    struct drm_display_mode *adjusted_mode);
0970 
0971 /* fmt blocks */
0972 void avivo_program_fmt(struct drm_encoder *encoder);
0973 void dce3_program_fmt(struct drm_encoder *encoder);
0974 void dce4_program_fmt(struct drm_encoder *encoder);
0975 void dce8_program_fmt(struct drm_encoder *encoder);
0976 
0977 /* fbdev layer */
0978 int radeon_fbdev_init(struct radeon_device *rdev);
0979 void radeon_fbdev_fini(struct radeon_device *rdev);
0980 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
0981 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
0982 
0983 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id);
0984 
0985 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
0986 
0987 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
0988 
0989 /* mst */
0990 int radeon_dp_mst_init(struct radeon_connector *radeon_connector);
0991 int radeon_dp_mst_probe(struct radeon_connector *radeon_connector);
0992 int radeon_dp_mst_check_status(struct radeon_connector *radeon_connector);
0993 void radeon_mst_debugfs_init(struct radeon_device *rdev);
0994 void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode);
0995 
0996 void radeon_setup_mst_connector(struct drm_device *dev);
0997 
0998 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx);
0999 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx);
1000 #endif
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!