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0001 // SPDX-License-Identifier: MIT
0002 
0003 #include <drm/drm_crtc_helper.h>
0004 #include <drm/drm_device.h>
0005 
0006 #include "radeon.h"
0007 
0008 /*
0009  * Integrated TV out support based on the GATOS code by
0010  * Federico Ulivi <fulivi@lycos.com>
0011  */
0012 
0013 
0014 /*
0015  * Limits of h/v positions (hPos & vPos)
0016  */
0017 #define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on the right */
0018 #define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */
0019 
0020 /*
0021  * Unit for hPos (in TV clock periods)
0022  */
0023 #define H_POS_UNIT 10
0024 
0025 /*
0026  * Indexes in h. code timing table for horizontal line position adjustment
0027  */
0028 #define H_TABLE_POS1 6
0029 #define H_TABLE_POS2 8
0030 
0031 /*
0032  * Limits of hor. size (hSize)
0033  */
0034 #define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */
0035 
0036 /* tv standard constants */
0037 #define NTSC_TV_CLOCK_T 233
0038 #define NTSC_TV_VFTOTAL 1
0039 #define NTSC_TV_LINES_PER_FRAME 525
0040 #define NTSC_TV_ZERO_H_SIZE 479166
0041 #define NTSC_TV_H_SIZE_UNIT 9478
0042 
0043 #define PAL_TV_CLOCK_T 188
0044 #define PAL_TV_VFTOTAL 3
0045 #define PAL_TV_LINES_PER_FRAME 625
0046 #define PAL_TV_ZERO_H_SIZE 473200
0047 #define PAL_TV_H_SIZE_UNIT 9360
0048 
0049 /* tv pll setting for 27 mhz ref clk */
0050 #define NTSC_TV_PLL_M_27 22
0051 #define NTSC_TV_PLL_N_27 175
0052 #define NTSC_TV_PLL_P_27 5
0053 
0054 #define PAL_TV_PLL_M_27 113
0055 #define PAL_TV_PLL_N_27 668
0056 #define PAL_TV_PLL_P_27 3
0057 
0058 /* tv pll setting for 14 mhz ref clk */
0059 #define NTSC_TV_PLL_M_14 33
0060 #define NTSC_TV_PLL_N_14 693
0061 #define NTSC_TV_PLL_P_14 7
0062 
0063 #define PAL_TV_PLL_M_14 19
0064 #define PAL_TV_PLL_N_14 353
0065 #define PAL_TV_PLL_P_14 5
0066 
0067 #define VERT_LEAD_IN_LINES 2
0068 #define FRAC_BITS 0xe
0069 #define FRAC_MASK 0x3fff
0070 
0071 struct radeon_tv_mode_constants {
0072     uint16_t hor_resolution;
0073     uint16_t ver_resolution;
0074     enum radeon_tv_std standard;
0075     uint16_t hor_total;
0076     uint16_t ver_total;
0077     uint16_t hor_start;
0078     uint16_t hor_syncstart;
0079     uint16_t ver_syncstart;
0080     unsigned def_restart;
0081     uint16_t crtcPLL_N;
0082     uint8_t  crtcPLL_M;
0083     uint8_t  crtcPLL_post_div;
0084     unsigned pix_to_tv;
0085 };
0086 
0087 static const uint16_t hor_timing_NTSC[MAX_H_CODE_TIMING_LEN] = {
0088     0x0007,
0089     0x003f,
0090     0x0263,
0091     0x0a24,
0092     0x2a6b,
0093     0x0a36,
0094     0x126d, /* H_TABLE_POS1 */
0095     0x1bfe,
0096     0x1a8f, /* H_TABLE_POS2 */
0097     0x1ec7,
0098     0x3863,
0099     0x1bfe,
0100     0x1bfe,
0101     0x1a2a,
0102     0x1e95,
0103     0x0e31,
0104     0x201b,
0105     0
0106 };
0107 
0108 static const uint16_t vert_timing_NTSC[MAX_V_CODE_TIMING_LEN] = {
0109     0x2001,
0110     0x200d,
0111     0x1006,
0112     0x0c06,
0113     0x1006,
0114     0x1818,
0115     0x21e3,
0116     0x1006,
0117     0x0c06,
0118     0x1006,
0119     0x1817,
0120     0x21d4,
0121     0x0002,
0122     0
0123 };
0124 
0125 static const uint16_t hor_timing_PAL[MAX_H_CODE_TIMING_LEN] = {
0126     0x0007,
0127     0x0058,
0128     0x027c,
0129     0x0a31,
0130     0x2a77,
0131     0x0a95,
0132     0x124f, /* H_TABLE_POS1 */
0133     0x1bfe,
0134     0x1b22, /* H_TABLE_POS2 */
0135     0x1ef9,
0136     0x387c,
0137     0x1bfe,
0138     0x1bfe,
0139     0x1b31,
0140     0x1eb5,
0141     0x0e43,
0142     0x201b,
0143     0
0144 };
0145 
0146 static const uint16_t vert_timing_PAL[MAX_V_CODE_TIMING_LEN] = {
0147     0x2001,
0148     0x200c,
0149     0x1005,
0150     0x0c05,
0151     0x1005,
0152     0x1401,
0153     0x1821,
0154     0x2240,
0155     0x1005,
0156     0x0c05,
0157     0x1005,
0158     0x1401,
0159     0x1822,
0160     0x2230,
0161     0x0002,
0162     0
0163 };
0164 
0165 /**********************************************************************
0166  *
0167  * availableModes
0168  *
0169  * Table of all allowed modes for tv output
0170  *
0171  **********************************************************************/
0172 static const struct radeon_tv_mode_constants available_tv_modes[] = {
0173     {   /* NTSC timing for 27 Mhz ref clk */
0174         800,                /* horResolution */
0175         600,                /* verResolution */
0176         TV_STD_NTSC,        /* standard */
0177         990,                /* horTotal */
0178         740,                /* verTotal */
0179         813,                /* horStart */
0180         824,                /* horSyncStart */
0181         632,                /* verSyncStart */
0182         625592,             /* defRestart */
0183         592,                /* crtcPLL_N */
0184         91,                 /* crtcPLL_M */
0185         4,                  /* crtcPLL_postDiv */
0186         1022,               /* pixToTV */
0187     },
0188     {   /* PAL timing for 27 Mhz ref clk */
0189         800,               /* horResolution */
0190         600,               /* verResolution */
0191         TV_STD_PAL,        /* standard */
0192         1144,              /* horTotal */
0193         706,               /* verTotal */
0194         812,               /* horStart */
0195         824,               /* horSyncStart */
0196         669,               /* verSyncStart */
0197         696700,            /* defRestart */
0198         1382,              /* crtcPLL_N */
0199         231,               /* crtcPLL_M */
0200         4,                 /* crtcPLL_postDiv */
0201         759,               /* pixToTV */
0202     },
0203     {   /* NTSC timing for 14 Mhz ref clk */
0204         800,                /* horResolution */
0205         600,                /* verResolution */
0206         TV_STD_NTSC,        /* standard */
0207         1018,               /* horTotal */
0208         727,                /* verTotal */
0209         813,                /* horStart */
0210         840,                /* horSyncStart */
0211         633,                /* verSyncStart */
0212         630627,             /* defRestart */
0213         347,                /* crtcPLL_N */
0214         14,                 /* crtcPLL_M */
0215         8,                  /* crtcPLL_postDiv */
0216         1022,               /* pixToTV */
0217     },
0218     { /* PAL timing for 14 Mhz ref clk */
0219         800,                /* horResolution */
0220         600,                /* verResolution */
0221         TV_STD_PAL,         /* standard */
0222         1131,               /* horTotal */
0223         742,                /* verTotal */
0224         813,                /* horStart */
0225         840,                /* horSyncStart */
0226         633,                /* verSyncStart */
0227         708369,             /* defRestart */
0228         211,                /* crtcPLL_N */
0229         9,                  /* crtcPLL_M */
0230         8,                  /* crtcPLL_postDiv */
0231         759,                /* pixToTV */
0232     },
0233 };
0234 
0235 #define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes)
0236 
0237 static const struct radeon_tv_mode_constants *radeon_legacy_tv_get_std_mode(struct radeon_encoder *radeon_encoder,
0238                                         uint16_t *pll_ref_freq)
0239 {
0240     struct drm_device *dev = radeon_encoder->base.dev;
0241     struct radeon_device *rdev = dev->dev_private;
0242     struct radeon_crtc *radeon_crtc;
0243     struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
0244     const struct radeon_tv_mode_constants *const_ptr;
0245     struct radeon_pll *pll;
0246 
0247     radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc);
0248     if (radeon_crtc->crtc_id == 1)
0249         pll = &rdev->clock.p2pll;
0250     else
0251         pll = &rdev->clock.p1pll;
0252 
0253     if (pll_ref_freq)
0254         *pll_ref_freq = pll->reference_freq;
0255 
0256     if (tv_dac->tv_std == TV_STD_NTSC ||
0257         tv_dac->tv_std == TV_STD_NTSC_J ||
0258         tv_dac->tv_std == TV_STD_PAL_M) {
0259         if (pll->reference_freq == 2700)
0260             const_ptr = &available_tv_modes[0];
0261         else
0262             const_ptr = &available_tv_modes[2];
0263     } else {
0264         if (pll->reference_freq == 2700)
0265             const_ptr = &available_tv_modes[1];
0266         else
0267             const_ptr = &available_tv_modes[3];
0268     }
0269     return const_ptr;
0270 }
0271 
0272 static long YCOEF_value[5] = { 2, 2, 0, 4, 0 };
0273 static long YCOEF_EN_value[5] = { 1, 1, 0, 1, 0 };
0274 static long SLOPE_value[5] = { 1, 2, 2, 4, 8 };
0275 static long SLOPE_limit[5] = { 6, 5, 4, 3, 2 };
0276 
0277 static void radeon_wait_pll_lock(struct drm_encoder *encoder, unsigned n_tests,
0278                  unsigned n_wait_loops, unsigned cnt_threshold)
0279 {
0280     struct drm_device *dev = encoder->dev;
0281     struct radeon_device *rdev = dev->dev_private;
0282     uint32_t save_pll_test;
0283     unsigned int i, j;
0284 
0285     WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100);
0286     save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL);
0287     WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B);
0288 
0289     WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL);
0290     for (i = 0; i < n_tests; i++) {
0291         WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0);
0292         for (j = 0; j < n_wait_loops; j++)
0293             if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold)
0294                 break;
0295     }
0296     WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test);
0297     WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff);
0298 }
0299 
0300 
0301 static void radeon_legacy_tv_write_fifo(struct radeon_encoder *radeon_encoder,
0302                     uint16_t addr, uint32_t value)
0303 {
0304     struct drm_device *dev = radeon_encoder->base.dev;
0305     struct radeon_device *rdev = dev->dev_private;
0306     uint32_t tmp;
0307     int i = 0;
0308 
0309     WREG32(RADEON_TV_HOST_WRITE_DATA, value);
0310 
0311     WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr);
0312     WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT);
0313 
0314     do {
0315         tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
0316         if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0)
0317             break;
0318         i++;
0319     } while (i < 10000);
0320     WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0);
0321 }
0322 
0323 #if 0 /* included for completeness */
0324 static uint32_t radeon_legacy_tv_read_fifo(struct radeon_encoder *radeon_encoder, uint16_t addr)
0325 {
0326     struct drm_device *dev = radeon_encoder->base.dev;
0327     struct radeon_device *rdev = dev->dev_private;
0328     uint32_t tmp;
0329     int i = 0;
0330 
0331     WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr);
0332     WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD);
0333 
0334     do {
0335         tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
0336         if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0)
0337             break;
0338         i++;
0339     } while (i < 10000);
0340     WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0);
0341     return RREG32(RADEON_TV_HOST_READ_DATA);
0342 }
0343 #endif
0344 
0345 static uint16_t radeon_get_htiming_tables_addr(uint32_t tv_uv_adr)
0346 {
0347     uint16_t h_table;
0348 
0349     switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) {
0350     case 0:
0351         h_table = RADEON_TV_MAX_FIFO_ADDR_INTERNAL;
0352         break;
0353     case 1:
0354         h_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2;
0355         break;
0356     case 2:
0357         h_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2;
0358         break;
0359     default:
0360         h_table = 0;
0361         break;
0362     }
0363     return h_table;
0364 }
0365 
0366 static uint16_t radeon_get_vtiming_tables_addr(uint32_t tv_uv_adr)
0367 {
0368     uint16_t v_table;
0369 
0370     switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) {
0371     case 0:
0372         v_table = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1;
0373         break;
0374     case 1:
0375         v_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1;
0376         break;
0377     case 2:
0378         v_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1;
0379         break;
0380     default:
0381         v_table = 0;
0382         break;
0383     }
0384     return v_table;
0385 }
0386 
0387 static void radeon_restore_tv_timing_tables(struct radeon_encoder *radeon_encoder)
0388 {
0389     struct drm_device *dev = radeon_encoder->base.dev;
0390     struct radeon_device *rdev = dev->dev_private;
0391     struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
0392     uint16_t h_table, v_table;
0393     uint32_t tmp;
0394     int i;
0395 
0396     WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr);
0397     h_table = radeon_get_htiming_tables_addr(tv_dac->tv.tv_uv_adr);
0398     v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr);
0399 
0400     for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, h_table--) {
0401         tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]);
0402         radeon_legacy_tv_write_fifo(radeon_encoder, h_table, tmp);
0403         if (tv_dac->tv.h_code_timing[i] == 0 || tv_dac->tv.h_code_timing[i + 1] == 0)
0404             break;
0405     }
0406     for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, v_table++) {
0407         tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]);
0408         radeon_legacy_tv_write_fifo(radeon_encoder, v_table, tmp);
0409         if (tv_dac->tv.v_code_timing[i] == 0 || tv_dac->tv.v_code_timing[i + 1] == 0)
0410             break;
0411     }
0412 }
0413 
0414 static void radeon_legacy_write_tv_restarts(struct radeon_encoder *radeon_encoder)
0415 {
0416     struct drm_device *dev = radeon_encoder->base.dev;
0417     struct radeon_device *rdev = dev->dev_private;
0418     struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
0419     WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart);
0420     WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart);
0421     WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart);
0422 }
0423 
0424 static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder)
0425 {
0426     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0427     struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
0428     int restart;
0429     unsigned int h_total, v_total, f_total;
0430     int v_offset, h_offset;
0431     u16 p1, p2, h_inc;
0432     bool h_changed;
0433     const struct radeon_tv_mode_constants *const_ptr;
0434 
0435     const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
0436     if (!const_ptr)
0437         return false;
0438 
0439     h_total = const_ptr->hor_total;
0440     v_total = const_ptr->ver_total;
0441 
0442     if (tv_dac->tv_std == TV_STD_NTSC ||
0443         tv_dac->tv_std == TV_STD_NTSC_J ||
0444         tv_dac->tv_std == TV_STD_PAL_M ||
0445         tv_dac->tv_std == TV_STD_PAL_60)
0446         f_total = NTSC_TV_VFTOTAL + 1;
0447     else
0448         f_total = PAL_TV_VFTOTAL + 1;
0449 
0450     /* adjust positions 1&2 in hor. cod timing table */
0451     h_offset = tv_dac->h_pos * H_POS_UNIT;
0452 
0453     if (tv_dac->tv_std == TV_STD_NTSC ||
0454         tv_dac->tv_std == TV_STD_NTSC_J ||
0455         tv_dac->tv_std == TV_STD_PAL_M) {
0456         h_offset -= 50;
0457         p1 = hor_timing_NTSC[H_TABLE_POS1];
0458         p2 = hor_timing_NTSC[H_TABLE_POS2];
0459     } else {
0460         p1 = hor_timing_PAL[H_TABLE_POS1];
0461         p2 = hor_timing_PAL[H_TABLE_POS2];
0462     }
0463 
0464     p1 = (u16)((int)p1 + h_offset);
0465     p2 = (u16)((int)p2 - h_offset);
0466 
0467     h_changed = (p1 != tv_dac->tv.h_code_timing[H_TABLE_POS1] ||
0468              p2 != tv_dac->tv.h_code_timing[H_TABLE_POS2]);
0469 
0470     tv_dac->tv.h_code_timing[H_TABLE_POS1] = p1;
0471     tv_dac->tv.h_code_timing[H_TABLE_POS2] = p2;
0472 
0473     /* Convert hOffset from n. of TV clock periods to n. of CRTC clock periods (CRTC pixels) */
0474     h_offset = (h_offset * (int)(const_ptr->pix_to_tv)) / 1000;
0475 
0476     /* adjust restart */
0477     restart = const_ptr->def_restart;
0478 
0479     /*
0480      * convert v_pos TV lines to n. of CRTC pixels
0481      */
0482     if (tv_dac->tv_std == TV_STD_NTSC ||
0483         tv_dac->tv_std == TV_STD_NTSC_J ||
0484         tv_dac->tv_std == TV_STD_PAL_M ||
0485         tv_dac->tv_std == TV_STD_PAL_60)
0486         v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME);
0487     else
0488         v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME);
0489 
0490     restart -= v_offset + h_offset;
0491 
0492     DRM_DEBUG_KMS("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n",
0493           const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart);
0494 
0495     tv_dac->tv.hrestart = restart % h_total;
0496     restart /= h_total;
0497     tv_dac->tv.vrestart = restart % v_total;
0498     restart /= v_total;
0499     tv_dac->tv.frestart = restart % f_total;
0500 
0501     DRM_DEBUG_KMS("compute_restart: F/H/V=%u,%u,%u\n",
0502           (unsigned)tv_dac->tv.frestart,
0503           (unsigned)tv_dac->tv.vrestart,
0504           (unsigned)tv_dac->tv.hrestart);
0505 
0506     /* compute h_inc from hsize */
0507     if (tv_dac->tv_std == TV_STD_NTSC ||
0508         tv_dac->tv_std == TV_STD_NTSC_J ||
0509         tv_dac->tv_std == TV_STD_PAL_M)
0510         h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * NTSC_TV_CLOCK_T) /
0511                   (tv_dac->h_size * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE)));
0512     else
0513         h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * PAL_TV_CLOCK_T) /
0514                   (tv_dac->h_size * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE)));
0515 
0516     tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) |
0517         ((u32)h_inc << RADEON_H_INC_SHIFT);
0518 
0519     DRM_DEBUG_KMS("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc);
0520 
0521     return h_changed;
0522 }
0523 
0524 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
0525                    struct drm_display_mode *mode,
0526                    struct drm_display_mode *adjusted_mode)
0527 {
0528     struct drm_device *dev = encoder->dev;
0529     struct radeon_device *rdev = dev->dev_private;
0530     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0531     struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
0532     const struct radeon_tv_mode_constants *const_ptr;
0533     struct radeon_crtc *radeon_crtc;
0534     int i;
0535     uint16_t pll_ref_freq;
0536     uint32_t vert_space, flicker_removal, tmp;
0537     uint32_t tv_master_cntl, tv_rgb_cntl, tv_dac_cntl;
0538     uint32_t tv_modulator_cntl1, tv_modulator_cntl2;
0539     uint32_t tv_vscaler_cntl1, tv_vscaler_cntl2;
0540     uint32_t tv_pll_cntl, tv_ftotal;
0541     uint32_t tv_y_fall_cntl, tv_y_rise_cntl, tv_y_saw_tooth_cntl;
0542     uint32_t m, n, p;
0543     const uint16_t *hor_timing;
0544     const uint16_t *vert_timing;
0545 
0546     const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, &pll_ref_freq);
0547     if (!const_ptr)
0548         return;
0549 
0550     radeon_crtc = to_radeon_crtc(encoder->crtc);
0551 
0552     tv_master_cntl = (RADEON_VIN_ASYNC_RST |
0553               RADEON_CRT_FIFO_CE_EN |
0554               RADEON_TV_FIFO_CE_EN |
0555               RADEON_TV_ON);
0556 
0557     if (!ASIC_IS_R300(rdev))
0558         tv_master_cntl |= RADEON_TVCLK_ALWAYS_ONb;
0559 
0560     if (tv_dac->tv_std == TV_STD_NTSC ||
0561         tv_dac->tv_std == TV_STD_NTSC_J)
0562         tv_master_cntl |= RADEON_RESTART_PHASE_FIX;
0563 
0564     tv_modulator_cntl1 = (RADEON_SLEW_RATE_LIMIT |
0565                   RADEON_SYNC_TIP_LEVEL |
0566                   RADEON_YFLT_EN |
0567                   RADEON_UVFLT_EN |
0568                   (6 << RADEON_CY_FILT_BLEND_SHIFT));
0569 
0570     if (tv_dac->tv_std == TV_STD_NTSC ||
0571         tv_dac->tv_std == TV_STD_NTSC_J) {
0572         tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT) |
0573             (0x3b << RADEON_BLANK_LEVEL_SHIFT);
0574         tv_modulator_cntl2 = (-111 & RADEON_TV_U_BURST_LEVEL_MASK) |
0575             ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
0576     } else if (tv_dac->tv_std == TV_STD_SCART_PAL) {
0577         tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN;
0578         tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) |
0579             ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
0580     } else {
0581         tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN |
0582             (0x3b << RADEON_SET_UP_LEVEL_SHIFT) |
0583             (0x3b << RADEON_BLANK_LEVEL_SHIFT);
0584         tv_modulator_cntl2 = (-78 & RADEON_TV_U_BURST_LEVEL_MASK) |
0585             ((62 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
0586     }
0587 
0588 
0589     tv_rgb_cntl = (RADEON_RGB_DITHER_EN
0590                | RADEON_TVOUT_SCALE_EN
0591                | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT)
0592                | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT)
0593                | RADEON_RGB_ATTEN_SEL(0x3)
0594                | RADEON_RGB_ATTEN_VAL(0xc));
0595 
0596     if (radeon_crtc->crtc_id == 1)
0597         tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC2;
0598     else {
0599         if (radeon_crtc->rmx_type != RMX_OFF)
0600             tv_rgb_cntl |= RADEON_RGB_SRC_SEL_RMX;
0601         else
0602             tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC1;
0603     }
0604 
0605     if (tv_dac->tv_std == TV_STD_NTSC ||
0606         tv_dac->tv_std == TV_STD_NTSC_J ||
0607         tv_dac->tv_std == TV_STD_PAL_M ||
0608         tv_dac->tv_std == TV_STD_PAL_60)
0609         vert_space = const_ptr->ver_total * 2 * 10000 / NTSC_TV_LINES_PER_FRAME;
0610     else
0611         vert_space = const_ptr->ver_total * 2 * 10000 / PAL_TV_LINES_PER_FRAME;
0612 
0613     tmp = RREG32(RADEON_TV_VSCALER_CNTL1);
0614     tmp &= 0xe3ff0000;
0615     tmp |= (vert_space * (1 << FRAC_BITS) / 10000);
0616     tv_vscaler_cntl1 = tmp;
0617 
0618     if (pll_ref_freq == 2700)
0619         tv_vscaler_cntl1 |= RADEON_RESTART_FIELD;
0620 
0621     if (const_ptr->hor_resolution == 1024)
0622         tv_vscaler_cntl1 |= (4 << RADEON_Y_DEL_W_SIG_SHIFT);
0623     else
0624         tv_vscaler_cntl1 |= (2 << RADEON_Y_DEL_W_SIG_SHIFT);
0625 
0626     /* scale up for int divide */
0627     tmp = const_ptr->ver_total * 2 * 1000;
0628     if (tv_dac->tv_std == TV_STD_NTSC ||
0629         tv_dac->tv_std == TV_STD_NTSC_J ||
0630         tv_dac->tv_std == TV_STD_PAL_M ||
0631         tv_dac->tv_std == TV_STD_PAL_60) {
0632         tmp /= NTSC_TV_LINES_PER_FRAME;
0633     } else {
0634         tmp /= PAL_TV_LINES_PER_FRAME;
0635     }
0636     flicker_removal = (tmp + 500) / 1000;
0637 
0638     if (flicker_removal < 3)
0639         flicker_removal = 3;
0640     for (i = 0; i < ARRAY_SIZE(SLOPE_limit); ++i) {
0641         if (flicker_removal == SLOPE_limit[i])
0642             break;
0643     }
0644 
0645     tv_y_saw_tooth_cntl = (vert_space * SLOPE_value[i] * (1 << (FRAC_BITS - 1)) +
0646                 5001) / 10000 / 8 | ((SLOPE_value[i] *
0647                 (1 << (FRAC_BITS - 1)) / 8) << 16);
0648     tv_y_fall_cntl =
0649         (YCOEF_EN_value[i] << 17) | ((YCOEF_value[i] * (1 << 8) / 8) << 24) |
0650         RADEON_Y_FALL_PING_PONG | (272 * SLOPE_value[i] / 8) * (1 << (FRAC_BITS - 1)) /
0651         1024;
0652     tv_y_rise_cntl = RADEON_Y_RISE_PING_PONG|
0653         (flicker_removal * 1024 - 272) * SLOPE_value[i] / 8 * (1 << (FRAC_BITS - 1)) / 1024;
0654 
0655     tv_vscaler_cntl2 = RREG32(RADEON_TV_VSCALER_CNTL2) & 0x00fffff0;
0656     tv_vscaler_cntl2 |= (0x10 << 24) |
0657         RADEON_DITHER_MODE |
0658         RADEON_Y_OUTPUT_DITHER_EN |
0659         RADEON_UV_OUTPUT_DITHER_EN |
0660         RADEON_UV_TO_BUF_DITHER_EN;
0661 
0662     tmp = (tv_vscaler_cntl1 >> RADEON_UV_INC_SHIFT) & RADEON_UV_INC_MASK;
0663     tmp = ((16384 * 256 * 10) / tmp + 5) / 10;
0664     tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000;
0665     tv_dac->tv.timing_cntl = tmp;
0666 
0667     if (tv_dac->tv_std == TV_STD_NTSC ||
0668         tv_dac->tv_std == TV_STD_NTSC_J ||
0669         tv_dac->tv_std == TV_STD_PAL_M ||
0670         tv_dac->tv_std == TV_STD_PAL_60)
0671         tv_dac_cntl = tv_dac->ntsc_tvdac_adj;
0672     else
0673         tv_dac_cntl = tv_dac->pal_tvdac_adj;
0674 
0675     tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
0676 
0677     if (tv_dac->tv_std == TV_STD_NTSC ||
0678         tv_dac->tv_std == TV_STD_NTSC_J)
0679         tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
0680     else
0681         tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
0682 
0683     if (tv_dac->tv_std == TV_STD_NTSC ||
0684         tv_dac->tv_std == TV_STD_NTSC_J) {
0685         if (pll_ref_freq == 2700) {
0686             m = NTSC_TV_PLL_M_27;
0687             n = NTSC_TV_PLL_N_27;
0688             p = NTSC_TV_PLL_P_27;
0689         } else {
0690             m = NTSC_TV_PLL_M_14;
0691             n = NTSC_TV_PLL_N_14;
0692             p = NTSC_TV_PLL_P_14;
0693         }
0694     } else {
0695         if (pll_ref_freq == 2700) {
0696             m = PAL_TV_PLL_M_27;
0697             n = PAL_TV_PLL_N_27;
0698             p = PAL_TV_PLL_P_27;
0699         } else {
0700             m = PAL_TV_PLL_M_14;
0701             n = PAL_TV_PLL_N_14;
0702             p = PAL_TV_PLL_P_14;
0703         }
0704     }
0705 
0706     tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) |
0707         (((m >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) |
0708         ((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) |
0709         (((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) |
0710         ((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT);
0711 
0712     tv_dac->tv.tv_uv_adr = 0xc8;
0713 
0714     if (tv_dac->tv_std == TV_STD_NTSC ||
0715         tv_dac->tv_std == TV_STD_NTSC_J ||
0716         tv_dac->tv_std == TV_STD_PAL_M ||
0717         tv_dac->tv_std == TV_STD_PAL_60) {
0718         tv_ftotal = NTSC_TV_VFTOTAL;
0719         hor_timing = hor_timing_NTSC;
0720         vert_timing = vert_timing_NTSC;
0721     } else {
0722         hor_timing = hor_timing_PAL;
0723         vert_timing = vert_timing_PAL;
0724         tv_ftotal = PAL_TV_VFTOTAL;
0725     }
0726 
0727     for (i = 0; i < MAX_H_CODE_TIMING_LEN; i++) {
0728         if ((tv_dac->tv.h_code_timing[i] = hor_timing[i]) == 0)
0729             break;
0730     }
0731 
0732     for (i = 0; i < MAX_V_CODE_TIMING_LEN; i++) {
0733         if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0)
0734             break;
0735     }
0736 
0737     radeon_legacy_tv_init_restarts(encoder);
0738 
0739     /* play with DAC_CNTL */
0740     /* play with GPIOPAD_A */
0741     /* DISP_OUTPUT_CNTL */
0742     /* use reference freq */
0743 
0744     /* program the TV registers */
0745     WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST |
0746                        RADEON_CRT_ASYNC_RST | RADEON_TV_FIFO_ASYNC_RST));
0747 
0748     tmp = RREG32(RADEON_TV_DAC_CNTL);
0749     tmp &= ~RADEON_TV_DAC_NBLANK;
0750     tmp |= RADEON_TV_DAC_BGSLEEP |
0751         RADEON_TV_DAC_RDACPD |
0752         RADEON_TV_DAC_GDACPD |
0753         RADEON_TV_DAC_BDACPD;
0754     WREG32(RADEON_TV_DAC_CNTL, tmp);
0755 
0756     /* TV PLL */
0757     WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL);
0758     WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl);
0759     WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET);
0760 
0761     radeon_wait_pll_lock(encoder, 200, 800, 135);
0762 
0763     WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET);
0764 
0765     radeon_wait_pll_lock(encoder, 300, 160, 27);
0766     radeon_wait_pll_lock(encoder, 200, 800, 135);
0767 
0768     WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf);
0769     WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL);
0770 
0771     WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK);
0772     WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP);
0773 
0774     /* TV HV */
0775     WREG32(RADEON_TV_RGB_CNTL, tv_rgb_cntl);
0776     WREG32(RADEON_TV_HTOTAL, const_ptr->hor_total - 1);
0777     WREG32(RADEON_TV_HDISP, const_ptr->hor_resolution - 1);
0778     WREG32(RADEON_TV_HSTART, const_ptr->hor_start);
0779 
0780     WREG32(RADEON_TV_VTOTAL, const_ptr->ver_total - 1);
0781     WREG32(RADEON_TV_VDISP, const_ptr->ver_resolution - 1);
0782     WREG32(RADEON_TV_FTOTAL, tv_ftotal);
0783     WREG32(RADEON_TV_VSCALER_CNTL1, tv_vscaler_cntl1);
0784     WREG32(RADEON_TV_VSCALER_CNTL2, tv_vscaler_cntl2);
0785 
0786     WREG32(RADEON_TV_Y_FALL_CNTL, tv_y_fall_cntl);
0787     WREG32(RADEON_TV_Y_RISE_CNTL, tv_y_rise_cntl);
0788     WREG32(RADEON_TV_Y_SAW_TOOTH_CNTL, tv_y_saw_tooth_cntl);
0789 
0790     WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST |
0791                        RADEON_CRT_ASYNC_RST));
0792 
0793     /* TV restarts */
0794     radeon_legacy_write_tv_restarts(radeon_encoder);
0795 
0796     /* tv timings */
0797     radeon_restore_tv_timing_tables(radeon_encoder);
0798 
0799     WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST));
0800 
0801     /* tv std */
0802     WREG32(RADEON_TV_SYNC_CNTL, (RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE));
0803     WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl);
0804     WREG32(RADEON_TV_MODULATOR_CNTL1, tv_modulator_cntl1);
0805     WREG32(RADEON_TV_MODULATOR_CNTL2, tv_modulator_cntl2);
0806     WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, (RADEON_Y_RED_EN |
0807                         RADEON_C_GRN_EN |
0808                         RADEON_CMP_BLU_EN |
0809                         RADEON_DAC_DITHER_EN));
0810 
0811     WREG32(RADEON_TV_CRC_CNTL, 0);
0812 
0813     WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
0814 
0815     WREG32(RADEON_TV_GAIN_LIMIT_SETTINGS, ((0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) |
0816                            (0x5ff << RADEON_Y_GAIN_LIMIT_SHIFT)));
0817     WREG32(RADEON_TV_LINEAR_GAIN_SETTINGS, ((0x100 << RADEON_UV_GAIN_SHIFT) |
0818                         (0x100 << RADEON_Y_GAIN_SHIFT)));
0819 
0820     WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
0821 
0822 }
0823 
0824 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
0825                       uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
0826                       uint32_t *v_total_disp, uint32_t *v_sync_strt_wid)
0827 {
0828     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0829     const struct radeon_tv_mode_constants *const_ptr;
0830     uint32_t tmp;
0831 
0832     const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
0833     if (!const_ptr)
0834         return;
0835 
0836     *h_total_disp = (((const_ptr->hor_resolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) |
0837         (((const_ptr->hor_total / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT);
0838 
0839     tmp = *h_sync_strt_wid;
0840     tmp &= ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR);
0841     tmp |= (((const_ptr->hor_syncstart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) |
0842         (const_ptr->hor_syncstart & 7);
0843     *h_sync_strt_wid = tmp;
0844 
0845     *v_total_disp = ((const_ptr->ver_resolution - 1) << RADEON_CRTC_V_DISP_SHIFT) |
0846         ((const_ptr->ver_total - 1) << RADEON_CRTC_V_TOTAL_SHIFT);
0847 
0848     tmp = *v_sync_strt_wid;
0849     tmp &= ~RADEON_CRTC_V_SYNC_STRT;
0850     tmp |= ((const_ptr->ver_syncstart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT);
0851     *v_sync_strt_wid = tmp;
0852 }
0853 
0854 static int get_post_div(int value)
0855 {
0856     int post_div;
0857     switch (value) {
0858     case 1: post_div = 0; break;
0859     case 2: post_div = 1; break;
0860     case 3: post_div = 4; break;
0861     case 4: post_div = 2; break;
0862     case 6: post_div = 6; break;
0863     case 8: post_div = 3; break;
0864     case 12: post_div = 7; break;
0865     case 16:
0866     default: post_div = 5; break;
0867     }
0868     return post_div;
0869 }
0870 
0871 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
0872                   uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
0873                   uint32_t *ppll_div_3, uint32_t *pixclks_cntl)
0874 {
0875     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0876     const struct radeon_tv_mode_constants *const_ptr;
0877 
0878     const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
0879     if (!const_ptr)
0880         return;
0881 
0882     *htotal_cntl = (const_ptr->hor_total & 0x7) | RADEON_HTOT_CNTL_VGA_EN;
0883 
0884     *ppll_ref_div = const_ptr->crtcPLL_M;
0885 
0886     *ppll_div_3 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16);
0887     *pixclks_cntl &= ~(RADEON_PIX2CLK_SRC_SEL_MASK | RADEON_PIXCLK_TV_SRC_SEL);
0888     *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK;
0889 }
0890 
0891 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
0892                   uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
0893                   uint32_t *p2pll_div_0, uint32_t *pixclks_cntl)
0894 {
0895     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0896     const struct radeon_tv_mode_constants *const_ptr;
0897 
0898     const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
0899     if (!const_ptr)
0900         return;
0901 
0902     *htotal2_cntl = (const_ptr->hor_total & 0x7);
0903 
0904     *p2pll_ref_div = const_ptr->crtcPLL_M;
0905 
0906     *p2pll_div_0 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16);
0907     *pixclks_cntl &= ~RADEON_PIX2CLK_SRC_SEL_MASK;
0908     *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK | RADEON_PIXCLK_TV_SRC_SEL;
0909 }
0910
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