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0001 /*
0002  * Copyright 2007-8 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors: Dave Airlie
0024  *          Alex Deucher
0025  */
0026 
0027 #include <linux/backlight.h>
0028 #include <linux/pci.h>
0029 
0030 #include <drm/drm_crtc_helper.h>
0031 #include <drm/drm_device.h>
0032 #include <drm/drm_file.h>
0033 #include <drm/drm_util.h>
0034 #include <drm/radeon_drm.h>
0035 
0036 #include "radeon.h"
0037 #include "radeon_asic.h"
0038 #include "radeon_legacy_encoders.h"
0039 #include "atom.h"
0040 #ifdef CONFIG_PMAC_BACKLIGHT
0041 #include <asm/backlight.h>
0042 #endif
0043 
0044 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
0045 {
0046     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0047     const struct drm_encoder_helper_funcs *encoder_funcs;
0048 
0049     encoder_funcs = encoder->helper_private;
0050     encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
0051     radeon_encoder->active_device = 0;
0052 }
0053 
0054 static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
0055 {
0056     struct drm_device *dev = encoder->dev;
0057     struct radeon_device *rdev = dev->dev_private;
0058     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0059     uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
0060     int panel_pwr_delay = 2000;
0061     bool is_mac = false;
0062     uint8_t backlight_level;
0063     DRM_DEBUG_KMS("\n");
0064 
0065     lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
0066     backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
0067 
0068     if (radeon_encoder->enc_priv) {
0069         if (rdev->is_atom_bios) {
0070             struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
0071             panel_pwr_delay = lvds->panel_pwr_delay;
0072             if (lvds->bl_dev)
0073                 backlight_level = lvds->backlight_level;
0074         } else {
0075             struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
0076             panel_pwr_delay = lvds->panel_pwr_delay;
0077             if (lvds->bl_dev)
0078                 backlight_level = lvds->backlight_level;
0079         }
0080     }
0081 
0082     /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
0083      * Taken from radeonfb.
0084      */
0085     if ((rdev->mode_info.connector_table == CT_IBOOK) ||
0086         (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
0087         (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
0088         (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
0089         is_mac = true;
0090 
0091     switch (mode) {
0092     case DRM_MODE_DPMS_ON:
0093         disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
0094         disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
0095         WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
0096         lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
0097         lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
0098         WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
0099         mdelay(1);
0100 
0101         lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
0102         lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
0103         WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
0104 
0105         lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS |
0106                    RADEON_LVDS_BL_MOD_LEVEL_MASK);
0107         lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN |
0108                   RADEON_LVDS_DIGON | RADEON_LVDS_BLON |
0109                   (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT));
0110         if (is_mac)
0111             lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
0112         mdelay(panel_pwr_delay);
0113         WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
0114         break;
0115     case DRM_MODE_DPMS_STANDBY:
0116     case DRM_MODE_DPMS_SUSPEND:
0117     case DRM_MODE_DPMS_OFF:
0118         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
0119         WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
0120         lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
0121         if (is_mac) {
0122             lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
0123             WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
0124             lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
0125         } else {
0126             WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
0127             lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
0128         }
0129         mdelay(panel_pwr_delay);
0130         WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
0131         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
0132         mdelay(panel_pwr_delay);
0133         break;
0134     }
0135 
0136     if (rdev->is_atom_bios)
0137         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
0138     else
0139         radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
0140 
0141 }
0142 
0143 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
0144 {
0145     struct radeon_device *rdev = encoder->dev->dev_private;
0146     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0147     DRM_DEBUG("\n");
0148 
0149     if (radeon_encoder->enc_priv) {
0150         if (rdev->is_atom_bios) {
0151             struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
0152             lvds->dpms_mode = mode;
0153         } else {
0154             struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
0155             lvds->dpms_mode = mode;
0156         }
0157     }
0158 
0159     radeon_legacy_lvds_update(encoder, mode);
0160 }
0161 
0162 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
0163 {
0164     struct radeon_device *rdev = encoder->dev->dev_private;
0165 
0166     if (rdev->is_atom_bios)
0167         radeon_atom_output_lock(encoder, true);
0168     else
0169         radeon_combios_output_lock(encoder, true);
0170     radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
0171 }
0172 
0173 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
0174 {
0175     struct radeon_device *rdev = encoder->dev->dev_private;
0176 
0177     radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
0178     if (rdev->is_atom_bios)
0179         radeon_atom_output_lock(encoder, false);
0180     else
0181         radeon_combios_output_lock(encoder, false);
0182 }
0183 
0184 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
0185                     struct drm_display_mode *mode,
0186                     struct drm_display_mode *adjusted_mode)
0187 {
0188     struct drm_device *dev = encoder->dev;
0189     struct radeon_device *rdev = dev->dev_private;
0190     struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
0191     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0192     uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
0193 
0194     DRM_DEBUG_KMS("\n");
0195 
0196     lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
0197     lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
0198 
0199     lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
0200     if (rdev->is_atom_bios) {
0201         /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
0202          * need to call that on resume to set up the reg properly.
0203          */
0204         radeon_encoder->pixel_clock = adjusted_mode->clock;
0205         atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
0206         lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
0207     } else {
0208         struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
0209         if (lvds) {
0210             DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
0211             lvds_gen_cntl = lvds->lvds_gen_cntl;
0212             lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
0213                           (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
0214             lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
0215                          (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
0216         } else
0217             lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
0218     }
0219     lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
0220     lvds_gen_cntl &= ~(RADEON_LVDS_ON |
0221                RADEON_LVDS_BLON |
0222                RADEON_LVDS_EN |
0223                RADEON_LVDS_RST_FM);
0224 
0225     if (ASIC_IS_R300(rdev))
0226         lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
0227 
0228     if (radeon_crtc->crtc_id == 0) {
0229         if (ASIC_IS_R300(rdev)) {
0230             if (radeon_encoder->rmx_type != RMX_OFF)
0231                 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
0232         } else
0233             lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
0234     } else {
0235         if (ASIC_IS_R300(rdev))
0236             lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
0237         else
0238             lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
0239     }
0240 
0241     WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
0242     WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
0243     WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
0244 
0245     if (rdev->family == CHIP_RV410)
0246         WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
0247 
0248     if (rdev->is_atom_bios)
0249         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
0250     else
0251         radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
0252 }
0253 
0254 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
0255                      const struct drm_display_mode *mode,
0256                      struct drm_display_mode *adjusted_mode)
0257 {
0258     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0259 
0260     /* set the active encoder to connector routing */
0261     radeon_encoder_set_active_device(encoder);
0262     drm_mode_set_crtcinfo(adjusted_mode, 0);
0263 
0264     /* get the native mode for LVDS */
0265     if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
0266         radeon_panel_mode_fixup(encoder, adjusted_mode);
0267 
0268     return true;
0269 }
0270 
0271 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
0272     .dpms = radeon_legacy_lvds_dpms,
0273     .mode_fixup = radeon_legacy_mode_fixup,
0274     .prepare = radeon_legacy_lvds_prepare,
0275     .mode_set = radeon_legacy_lvds_mode_set,
0276     .commit = radeon_legacy_lvds_commit,
0277     .disable = radeon_legacy_encoder_disable,
0278 };
0279 
0280 u8
0281 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder)
0282 {
0283     struct drm_device *dev = radeon_encoder->base.dev;
0284     struct radeon_device *rdev = dev->dev_private;
0285     u8 backlight_level;
0286 
0287     backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
0288                RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
0289 
0290     return backlight_level;
0291 }
0292 
0293 void
0294 radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
0295 {
0296     struct drm_device *dev = radeon_encoder->base.dev;
0297     struct radeon_device *rdev = dev->dev_private;
0298     int dpms_mode = DRM_MODE_DPMS_ON;
0299 
0300     if (radeon_encoder->enc_priv) {
0301         if (rdev->is_atom_bios) {
0302             struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
0303             if (lvds->backlight_level > 0)
0304                 dpms_mode = lvds->dpms_mode;
0305             else
0306                 dpms_mode = DRM_MODE_DPMS_OFF;
0307             lvds->backlight_level = level;
0308         } else {
0309             struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
0310             if (lvds->backlight_level > 0)
0311                 dpms_mode = lvds->dpms_mode;
0312             else
0313                 dpms_mode = DRM_MODE_DPMS_OFF;
0314             lvds->backlight_level = level;
0315         }
0316     }
0317 
0318     radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode);
0319 }
0320 
0321 static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
0322 {
0323     struct radeon_backlight_privdata *pdata = bl_get_data(bd);
0324     uint8_t level;
0325 
0326     /* Convert brightness to hardware level */
0327     if (bd->props.brightness < 0)
0328         level = 0;
0329     else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
0330         level = RADEON_MAX_BL_LEVEL;
0331     else
0332         level = bd->props.brightness;
0333 
0334     if (pdata->negative)
0335         level = RADEON_MAX_BL_LEVEL - level;
0336 
0337     return level;
0338 }
0339 
0340 static int radeon_legacy_backlight_update_status(struct backlight_device *bd)
0341 {
0342     struct radeon_backlight_privdata *pdata = bl_get_data(bd);
0343     struct radeon_encoder *radeon_encoder = pdata->encoder;
0344 
0345     radeon_legacy_set_backlight_level(radeon_encoder,
0346                       radeon_legacy_lvds_level(bd));
0347 
0348     return 0;
0349 }
0350 
0351 static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd)
0352 {
0353     struct radeon_backlight_privdata *pdata = bl_get_data(bd);
0354     struct radeon_encoder *radeon_encoder = pdata->encoder;
0355     struct drm_device *dev = radeon_encoder->base.dev;
0356     struct radeon_device *rdev = dev->dev_private;
0357     uint8_t backlight_level;
0358 
0359     backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
0360                RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
0361 
0362     return pdata->negative ? RADEON_MAX_BL_LEVEL - backlight_level : backlight_level;
0363 }
0364 
0365 static const struct backlight_ops radeon_backlight_ops = {
0366     .get_brightness = radeon_legacy_backlight_get_brightness,
0367     .update_status  = radeon_legacy_backlight_update_status,
0368 };
0369 
0370 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
0371                   struct drm_connector *drm_connector)
0372 {
0373     struct drm_device *dev = radeon_encoder->base.dev;
0374     struct radeon_device *rdev = dev->dev_private;
0375     struct backlight_device *bd;
0376     struct backlight_properties props;
0377     struct radeon_backlight_privdata *pdata;
0378     uint8_t backlight_level;
0379     char bl_name[16];
0380 
0381     if (!radeon_encoder->enc_priv)
0382         return;
0383 
0384 #ifdef CONFIG_PMAC_BACKLIGHT
0385     if (!pmac_has_backlight_type("ati") &&
0386         !pmac_has_backlight_type("mnca"))
0387         return;
0388 #endif
0389 
0390     pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
0391     if (!pdata) {
0392         DRM_ERROR("Memory allocation failed\n");
0393         goto error;
0394     }
0395 
0396     memset(&props, 0, sizeof(props));
0397     props.max_brightness = RADEON_MAX_BL_LEVEL;
0398     props.type = BACKLIGHT_RAW;
0399     snprintf(bl_name, sizeof(bl_name),
0400          "radeon_bl%d", dev->primary->index);
0401     bd = backlight_device_register(bl_name, drm_connector->kdev,
0402                        pdata, &radeon_backlight_ops, &props);
0403     if (IS_ERR(bd)) {
0404         DRM_ERROR("Backlight registration failed\n");
0405         goto error;
0406     }
0407 
0408     pdata->encoder = radeon_encoder;
0409 
0410     backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
0411                RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
0412 
0413     /* First, try to detect backlight level sense based on the assumption
0414      * that firmware set it up at full brightness
0415      */
0416     if (backlight_level == 0)
0417         pdata->negative = true;
0418     else if (backlight_level == 0xff)
0419         pdata->negative = false;
0420     else {
0421         /* XXX hack... maybe some day we can figure out in what direction
0422          * backlight should work on a given panel?
0423          */
0424         pdata->negative = (rdev->family != CHIP_RV200 &&
0425                    rdev->family != CHIP_RV250 &&
0426                    rdev->family != CHIP_RV280 &&
0427                    rdev->family != CHIP_RV350);
0428 
0429 #ifdef CONFIG_PMAC_BACKLIGHT
0430         pdata->negative = (pdata->negative ||
0431                    of_machine_is_compatible("PowerBook4,3") ||
0432                    of_machine_is_compatible("PowerBook6,3") ||
0433                    of_machine_is_compatible("PowerBook6,5"));
0434 #endif
0435     }
0436 
0437     if (rdev->is_atom_bios) {
0438         struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
0439         lvds->bl_dev = bd;
0440     } else {
0441         struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
0442         lvds->bl_dev = bd;
0443     }
0444 
0445     bd->props.brightness = radeon_legacy_backlight_get_brightness(bd);
0446     bd->props.power = FB_BLANK_UNBLANK;
0447     backlight_update_status(bd);
0448 
0449     DRM_INFO("radeon legacy LVDS backlight initialized\n");
0450     rdev->mode_info.bl_encoder = radeon_encoder;
0451 
0452     return;
0453 
0454 error:
0455     kfree(pdata);
0456     return;
0457 }
0458 
0459 static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder)
0460 {
0461     struct drm_device *dev = radeon_encoder->base.dev;
0462     struct radeon_device *rdev = dev->dev_private;
0463     struct backlight_device *bd = NULL;
0464 
0465     if (!radeon_encoder->enc_priv)
0466         return;
0467 
0468     if (rdev->is_atom_bios) {
0469         struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
0470         bd = lvds->bl_dev;
0471         lvds->bl_dev = NULL;
0472     } else {
0473         struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
0474         bd = lvds->bl_dev;
0475         lvds->bl_dev = NULL;
0476     }
0477 
0478     if (bd) {
0479         struct radeon_backlight_privdata *pdata;
0480 
0481         pdata = bl_get_data(bd);
0482         backlight_device_unregister(bd);
0483         kfree(pdata);
0484 
0485         DRM_INFO("radeon legacy LVDS backlight unloaded\n");
0486     }
0487 }
0488 
0489 static void radeon_lvds_enc_destroy(struct drm_encoder *encoder)
0490 {
0491     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0492 
0493     if (radeon_encoder->enc_priv) {
0494         radeon_legacy_backlight_exit(radeon_encoder);
0495         kfree(radeon_encoder->enc_priv);
0496     }
0497     drm_encoder_cleanup(encoder);
0498     kfree(radeon_encoder);
0499 }
0500 
0501 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
0502     .destroy = radeon_lvds_enc_destroy,
0503 };
0504 
0505 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
0506 {
0507     struct drm_device *dev = encoder->dev;
0508     struct radeon_device *rdev = dev->dev_private;
0509     uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
0510     uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
0511     uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
0512 
0513     DRM_DEBUG_KMS("\n");
0514 
0515     switch (mode) {
0516     case DRM_MODE_DPMS_ON:
0517         crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
0518         dac_cntl &= ~RADEON_DAC_PDWN;
0519         dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
0520                     RADEON_DAC_PDWN_G |
0521                     RADEON_DAC_PDWN_B);
0522         break;
0523     case DRM_MODE_DPMS_STANDBY:
0524     case DRM_MODE_DPMS_SUSPEND:
0525     case DRM_MODE_DPMS_OFF:
0526         crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
0527         dac_cntl |= RADEON_DAC_PDWN;
0528         dac_macro_cntl |= (RADEON_DAC_PDWN_R |
0529                    RADEON_DAC_PDWN_G |
0530                    RADEON_DAC_PDWN_B);
0531         break;
0532     }
0533 
0534     /* handled in radeon_crtc_dpms() */
0535     if (!(rdev->flags & RADEON_SINGLE_CRTC))
0536         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
0537     WREG32(RADEON_DAC_CNTL, dac_cntl);
0538     WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
0539 
0540     if (rdev->is_atom_bios)
0541         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
0542     else
0543         radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
0544 
0545 }
0546 
0547 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
0548 {
0549     struct radeon_device *rdev = encoder->dev->dev_private;
0550 
0551     if (rdev->is_atom_bios)
0552         radeon_atom_output_lock(encoder, true);
0553     else
0554         radeon_combios_output_lock(encoder, true);
0555     radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
0556 }
0557 
0558 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
0559 {
0560     struct radeon_device *rdev = encoder->dev->dev_private;
0561 
0562     radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
0563 
0564     if (rdev->is_atom_bios)
0565         radeon_atom_output_lock(encoder, false);
0566     else
0567         radeon_combios_output_lock(encoder, false);
0568 }
0569 
0570 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
0571                            struct drm_display_mode *mode,
0572                            struct drm_display_mode *adjusted_mode)
0573 {
0574     struct drm_device *dev = encoder->dev;
0575     struct radeon_device *rdev = dev->dev_private;
0576     struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
0577     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0578     uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
0579 
0580     DRM_DEBUG_KMS("\n");
0581 
0582     if (radeon_crtc->crtc_id == 0) {
0583         if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
0584             disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
0585                 ~(RADEON_DISP_DAC_SOURCE_MASK);
0586             WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
0587         } else {
0588             dac2_cntl = RREG32(RADEON_DAC_CNTL2)  & ~(RADEON_DAC2_DAC_CLK_SEL);
0589             WREG32(RADEON_DAC_CNTL2, dac2_cntl);
0590         }
0591     } else {
0592         if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
0593             disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
0594                 ~(RADEON_DISP_DAC_SOURCE_MASK);
0595             disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
0596             WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
0597         } else {
0598             dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
0599             WREG32(RADEON_DAC_CNTL2, dac2_cntl);
0600         }
0601     }
0602 
0603     dac_cntl = (RADEON_DAC_MASK_ALL |
0604             RADEON_DAC_VGA_ADR_EN |
0605             /* TODO 6-bits */
0606             RADEON_DAC_8BIT_EN);
0607 
0608     WREG32_P(RADEON_DAC_CNTL,
0609                dac_cntl,
0610                RADEON_DAC_RANGE_CNTL |
0611                RADEON_DAC_BLANKING);
0612 
0613     if (radeon_encoder->enc_priv) {
0614         struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
0615         dac_macro_cntl = p_dac->ps2_pdac_adj;
0616     } else
0617         dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
0618     dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
0619     WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
0620 
0621     if (rdev->is_atom_bios)
0622         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
0623     else
0624         radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
0625 }
0626 
0627 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
0628                                   struct drm_connector *connector)
0629 {
0630     struct drm_device *dev = encoder->dev;
0631     struct radeon_device *rdev = dev->dev_private;
0632     uint32_t vclk_ecp_cntl, crtc_ext_cntl;
0633     uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
0634     enum drm_connector_status found = connector_status_disconnected;
0635     bool color = true;
0636 
0637     /* just don't bother on RN50 those chip are often connected to remoting
0638      * console hw and often we get failure to load detect those. So to make
0639      * everyone happy report the encoder as always connected.
0640      */
0641     if (ASIC_IS_RN50(rdev)) {
0642         return connector_status_connected;
0643     }
0644 
0645     /* save the regs we need */
0646     vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
0647     crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
0648     dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
0649     dac_cntl = RREG32(RADEON_DAC_CNTL);
0650     dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
0651 
0652     tmp = vclk_ecp_cntl &
0653         ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
0654     WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
0655 
0656     tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
0657     WREG32(RADEON_CRTC_EXT_CNTL, tmp);
0658 
0659     tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
0660         RADEON_DAC_FORCE_DATA_EN;
0661 
0662     if (color)
0663         tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
0664     else
0665         tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
0666 
0667     if (ASIC_IS_R300(rdev))
0668         tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
0669     else if (ASIC_IS_RV100(rdev))
0670         tmp |= (0x1ac << RADEON_DAC_FORCE_DATA_SHIFT);
0671     else
0672         tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
0673 
0674     WREG32(RADEON_DAC_EXT_CNTL, tmp);
0675 
0676     tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
0677     tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
0678     WREG32(RADEON_DAC_CNTL, tmp);
0679 
0680     tmp = dac_macro_cntl;
0681     tmp &= ~(RADEON_DAC_PDWN_R |
0682          RADEON_DAC_PDWN_G |
0683          RADEON_DAC_PDWN_B);
0684 
0685     WREG32(RADEON_DAC_MACRO_CNTL, tmp);
0686 
0687     mdelay(2);
0688 
0689     if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
0690         found = connector_status_connected;
0691 
0692     /* restore the regs we used */
0693     WREG32(RADEON_DAC_CNTL, dac_cntl);
0694     WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
0695     WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
0696     WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
0697     WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
0698 
0699     return found;
0700 }
0701 
0702 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
0703     .dpms = radeon_legacy_primary_dac_dpms,
0704     .mode_fixup = radeon_legacy_mode_fixup,
0705     .prepare = radeon_legacy_primary_dac_prepare,
0706     .mode_set = radeon_legacy_primary_dac_mode_set,
0707     .commit = radeon_legacy_primary_dac_commit,
0708     .detect = radeon_legacy_primary_dac_detect,
0709     .disable = radeon_legacy_encoder_disable,
0710 };
0711 
0712 
0713 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
0714     .destroy = radeon_enc_destroy,
0715 };
0716 
0717 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
0718 {
0719     struct drm_device *dev = encoder->dev;
0720     struct radeon_device *rdev = dev->dev_private;
0721     uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
0722     DRM_DEBUG_KMS("\n");
0723 
0724     switch (mode) {
0725     case DRM_MODE_DPMS_ON:
0726         fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
0727         break;
0728     case DRM_MODE_DPMS_STANDBY:
0729     case DRM_MODE_DPMS_SUSPEND:
0730     case DRM_MODE_DPMS_OFF:
0731         fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
0732         break;
0733     }
0734 
0735     WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
0736 
0737     if (rdev->is_atom_bios)
0738         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
0739     else
0740         radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
0741 
0742 }
0743 
0744 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
0745 {
0746     struct radeon_device *rdev = encoder->dev->dev_private;
0747 
0748     if (rdev->is_atom_bios)
0749         radeon_atom_output_lock(encoder, true);
0750     else
0751         radeon_combios_output_lock(encoder, true);
0752     radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
0753 }
0754 
0755 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
0756 {
0757     struct radeon_device *rdev = encoder->dev->dev_private;
0758 
0759     radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
0760 
0761     if (rdev->is_atom_bios)
0762         radeon_atom_output_lock(encoder, true);
0763     else
0764         radeon_combios_output_lock(encoder, true);
0765 }
0766 
0767 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
0768                         struct drm_display_mode *mode,
0769                         struct drm_display_mode *adjusted_mode)
0770 {
0771     struct drm_device *dev = encoder->dev;
0772     struct radeon_device *rdev = dev->dev_private;
0773     struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
0774     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0775     uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
0776     int i;
0777 
0778     DRM_DEBUG_KMS("\n");
0779 
0780     tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
0781     tmp &= 0xfffff;
0782     if (rdev->family == CHIP_RV280) {
0783         /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
0784         tmp ^= (1 << 22);
0785         tmds_pll_cntl ^= (1 << 22);
0786     }
0787 
0788     if (radeon_encoder->enc_priv) {
0789         struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
0790 
0791         for (i = 0; i < 4; i++) {
0792             if (tmds->tmds_pll[i].freq == 0)
0793                 break;
0794             if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
0795                 tmp = tmds->tmds_pll[i].value ;
0796                 break;
0797             }
0798         }
0799     }
0800 
0801     if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
0802         if (tmp & 0xfff00000)
0803             tmds_pll_cntl = tmp;
0804         else {
0805             tmds_pll_cntl &= 0xfff00000;
0806             tmds_pll_cntl |= tmp;
0807         }
0808     } else
0809         tmds_pll_cntl = tmp;
0810 
0811     tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
0812         ~(RADEON_TMDS_TRANSMITTER_PLLRST);
0813 
0814     if (rdev->family == CHIP_R200 ||
0815         rdev->family == CHIP_R100 ||
0816         ASIC_IS_R300(rdev))
0817         tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
0818     else /* RV chips got this bit reversed */
0819         tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
0820 
0821     fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
0822               (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
0823                RADEON_FP_CRTC_DONT_SHADOW_HEND));
0824 
0825     fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
0826 
0827     fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
0828              RADEON_FP_DFP_SYNC_SEL |
0829              RADEON_FP_CRT_SYNC_SEL |
0830              RADEON_FP_CRTC_LOCK_8DOT |
0831              RADEON_FP_USE_SHADOW_EN |
0832              RADEON_FP_CRTC_USE_SHADOW_VEND |
0833              RADEON_FP_CRT_SYNC_ALT);
0834 
0835     if (1) /*  FIXME rgbBits == 8 */
0836         fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */
0837     else
0838         fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
0839 
0840     if (radeon_crtc->crtc_id == 0) {
0841         if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
0842             fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
0843             if (radeon_encoder->rmx_type != RMX_OFF)
0844                 fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
0845             else
0846                 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
0847         } else
0848             fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
0849     } else {
0850         if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
0851             fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
0852             fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
0853         } else
0854             fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
0855     }
0856 
0857     WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
0858     WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
0859     WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
0860 
0861     if (rdev->is_atom_bios)
0862         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
0863     else
0864         radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
0865 }
0866 
0867 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
0868     .dpms = radeon_legacy_tmds_int_dpms,
0869     .mode_fixup = radeon_legacy_mode_fixup,
0870     .prepare = radeon_legacy_tmds_int_prepare,
0871     .mode_set = radeon_legacy_tmds_int_mode_set,
0872     .commit = radeon_legacy_tmds_int_commit,
0873     .disable = radeon_legacy_encoder_disable,
0874 };
0875 
0876 
0877 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
0878     .destroy = radeon_enc_destroy,
0879 };
0880 
0881 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
0882 {
0883     struct drm_device *dev = encoder->dev;
0884     struct radeon_device *rdev = dev->dev_private;
0885     uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
0886     DRM_DEBUG_KMS("\n");
0887 
0888     switch (mode) {
0889     case DRM_MODE_DPMS_ON:
0890         fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
0891         fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
0892         break;
0893     case DRM_MODE_DPMS_STANDBY:
0894     case DRM_MODE_DPMS_SUSPEND:
0895     case DRM_MODE_DPMS_OFF:
0896         fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
0897         fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
0898         break;
0899     }
0900 
0901     WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
0902 
0903     if (rdev->is_atom_bios)
0904         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
0905     else
0906         radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
0907 
0908 }
0909 
0910 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
0911 {
0912     struct radeon_device *rdev = encoder->dev->dev_private;
0913 
0914     if (rdev->is_atom_bios)
0915         radeon_atom_output_lock(encoder, true);
0916     else
0917         radeon_combios_output_lock(encoder, true);
0918     radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
0919 }
0920 
0921 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
0922 {
0923     struct radeon_device *rdev = encoder->dev->dev_private;
0924     radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
0925 
0926     if (rdev->is_atom_bios)
0927         radeon_atom_output_lock(encoder, false);
0928     else
0929         radeon_combios_output_lock(encoder, false);
0930 }
0931 
0932 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
0933                         struct drm_display_mode *mode,
0934                         struct drm_display_mode *adjusted_mode)
0935 {
0936     struct drm_device *dev = encoder->dev;
0937     struct radeon_device *rdev = dev->dev_private;
0938     struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
0939     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0940     uint32_t fp2_gen_cntl;
0941 
0942     DRM_DEBUG_KMS("\n");
0943 
0944     if (rdev->is_atom_bios) {
0945         radeon_encoder->pixel_clock = adjusted_mode->clock;
0946         atombios_dvo_setup(encoder, ATOM_ENABLE);
0947         fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
0948     } else {
0949         fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
0950 
0951         if (1) /*  FIXME rgbBits == 8 */
0952             fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
0953         else
0954             fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
0955 
0956         fp2_gen_cntl &= ~(RADEON_FP2_ON |
0957                   RADEON_FP2_DVO_EN |
0958                   RADEON_FP2_DVO_RATE_SEL_SDR);
0959 
0960         /* XXX: these are oem specific */
0961         if (ASIC_IS_R300(rdev)) {
0962             if ((rdev->pdev->device == 0x4850) &&
0963                 (rdev->pdev->subsystem_vendor == 0x1028) &&
0964                 (rdev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
0965                 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
0966             else
0967                 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
0968 
0969             /*if (mode->clock > 165000)
0970               fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
0971         }
0972         if (!radeon_combios_external_tmds_setup(encoder))
0973             radeon_external_tmds_setup(encoder);
0974     }
0975 
0976     if (radeon_crtc->crtc_id == 0) {
0977         if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
0978             fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
0979             if (radeon_encoder->rmx_type != RMX_OFF)
0980                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
0981             else
0982                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
0983         } else
0984             fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
0985     } else {
0986         if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
0987             fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
0988             fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
0989         } else
0990             fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
0991     }
0992 
0993     WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
0994 
0995     if (rdev->is_atom_bios)
0996         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
0997     else
0998         radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
0999 }
1000 
1001 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
1002 {
1003     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1004     /* don't destroy the i2c bus record here, this will be done in radeon_i2c_fini */
1005     kfree(radeon_encoder->enc_priv);
1006     drm_encoder_cleanup(encoder);
1007     kfree(radeon_encoder);
1008 }
1009 
1010 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
1011     .dpms = radeon_legacy_tmds_ext_dpms,
1012     .mode_fixup = radeon_legacy_mode_fixup,
1013     .prepare = radeon_legacy_tmds_ext_prepare,
1014     .mode_set = radeon_legacy_tmds_ext_mode_set,
1015     .commit = radeon_legacy_tmds_ext_commit,
1016     .disable = radeon_legacy_encoder_disable,
1017 };
1018 
1019 
1020 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
1021     .destroy = radeon_ext_tmds_enc_destroy,
1022 };
1023 
1024 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
1025 {
1026     struct drm_device *dev = encoder->dev;
1027     struct radeon_device *rdev = dev->dev_private;
1028     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1029     uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
1030     uint32_t tv_master_cntl = 0;
1031     bool is_tv;
1032     DRM_DEBUG_KMS("\n");
1033 
1034     is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1035 
1036     if (rdev->family == CHIP_R200)
1037         fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1038     else {
1039         if (is_tv)
1040             tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1041         else
1042             crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1043         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1044     }
1045 
1046     switch (mode) {
1047     case DRM_MODE_DPMS_ON:
1048         if (rdev->family == CHIP_R200) {
1049             fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1050         } else {
1051             if (is_tv)
1052                 tv_master_cntl |= RADEON_TV_ON;
1053             else
1054                 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
1055 
1056             if (rdev->family == CHIP_R420 ||
1057                 rdev->family == CHIP_R423 ||
1058                 rdev->family == CHIP_RV410)
1059                 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
1060                          R420_TV_DAC_GDACPD |
1061                          R420_TV_DAC_BDACPD |
1062                          RADEON_TV_DAC_BGSLEEP);
1063             else
1064                 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
1065                          RADEON_TV_DAC_GDACPD |
1066                          RADEON_TV_DAC_BDACPD |
1067                          RADEON_TV_DAC_BGSLEEP);
1068         }
1069         break;
1070     case DRM_MODE_DPMS_STANDBY:
1071     case DRM_MODE_DPMS_SUSPEND:
1072     case DRM_MODE_DPMS_OFF:
1073         if (rdev->family == CHIP_R200)
1074             fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1075         else {
1076             if (is_tv)
1077                 tv_master_cntl &= ~RADEON_TV_ON;
1078             else
1079                 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1080 
1081             if (rdev->family == CHIP_R420 ||
1082                 rdev->family == CHIP_R423 ||
1083                 rdev->family == CHIP_RV410)
1084                 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
1085                         R420_TV_DAC_GDACPD |
1086                         R420_TV_DAC_BDACPD |
1087                         RADEON_TV_DAC_BGSLEEP);
1088             else
1089                 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
1090                         RADEON_TV_DAC_GDACPD |
1091                         RADEON_TV_DAC_BDACPD |
1092                         RADEON_TV_DAC_BGSLEEP);
1093         }
1094         break;
1095     }
1096 
1097     if (rdev->family == CHIP_R200) {
1098         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1099     } else {
1100         if (is_tv)
1101             WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1102         /* handled in radeon_crtc_dpms() */
1103         else if (!(rdev->flags & RADEON_SINGLE_CRTC))
1104             WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1105         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1106     }
1107 
1108     if (rdev->is_atom_bios)
1109         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1110     else
1111         radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1112 
1113 }
1114 
1115 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
1116 {
1117     struct radeon_device *rdev = encoder->dev->dev_private;
1118 
1119     if (rdev->is_atom_bios)
1120         radeon_atom_output_lock(encoder, true);
1121     else
1122         radeon_combios_output_lock(encoder, true);
1123     radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
1124 }
1125 
1126 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
1127 {
1128     struct radeon_device *rdev = encoder->dev->dev_private;
1129 
1130     radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1131 
1132     if (rdev->is_atom_bios)
1133         radeon_atom_output_lock(encoder, true);
1134     else
1135         radeon_combios_output_lock(encoder, true);
1136 }
1137 
1138 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
1139         struct drm_display_mode *mode,
1140         struct drm_display_mode *adjusted_mode)
1141 {
1142     struct drm_device *dev = encoder->dev;
1143     struct radeon_device *rdev = dev->dev_private;
1144     struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1145     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1146     struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1147     uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
1148     uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
1149     bool is_tv = false;
1150 
1151     DRM_DEBUG_KMS("\n");
1152 
1153     is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1154 
1155     if (rdev->family != CHIP_R200) {
1156         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1157         if (rdev->family == CHIP_R420 ||
1158             rdev->family == CHIP_R423 ||
1159             rdev->family == CHIP_RV410) {
1160             tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1161                      RADEON_TV_DAC_BGADJ_MASK |
1162                      R420_TV_DAC_DACADJ_MASK |
1163                      R420_TV_DAC_RDACPD |
1164                      R420_TV_DAC_GDACPD |
1165                      R420_TV_DAC_BDACPD |
1166                      R420_TV_DAC_TVENABLE);
1167         } else {
1168             tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1169                      RADEON_TV_DAC_BGADJ_MASK |
1170                      RADEON_TV_DAC_DACADJ_MASK |
1171                      RADEON_TV_DAC_RDACPD |
1172                      RADEON_TV_DAC_GDACPD |
1173                      RADEON_TV_DAC_BDACPD);
1174         }
1175 
1176         tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
1177 
1178         if (is_tv) {
1179             if (tv_dac->tv_std == TV_STD_NTSC ||
1180                 tv_dac->tv_std == TV_STD_NTSC_J ||
1181                 tv_dac->tv_std == TV_STD_PAL_M ||
1182                 tv_dac->tv_std == TV_STD_PAL_60)
1183                 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
1184             else
1185                 tv_dac_cntl |= tv_dac->pal_tvdac_adj;
1186 
1187             if (tv_dac->tv_std == TV_STD_NTSC ||
1188                 tv_dac->tv_std == TV_STD_NTSC_J)
1189                 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
1190             else
1191                 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
1192         } else
1193             tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
1194                     tv_dac->ps2_tvdac_adj);
1195 
1196         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1197     }
1198 
1199     if (ASIC_IS_R300(rdev)) {
1200         gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
1201         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1202     } else if (rdev->family != CHIP_R200)
1203         disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1204     else if (rdev->family == CHIP_R200)
1205         fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1206 
1207     if (rdev->family >= CHIP_R200)
1208         disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
1209 
1210     if (is_tv) {
1211         uint32_t dac_cntl;
1212 
1213         dac_cntl = RREG32(RADEON_DAC_CNTL);
1214         dac_cntl &= ~RADEON_DAC_TVO_EN;
1215         WREG32(RADEON_DAC_CNTL, dac_cntl);
1216 
1217         if (ASIC_IS_R300(rdev))
1218             gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
1219 
1220         dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
1221         if (radeon_crtc->crtc_id == 0) {
1222             if (ASIC_IS_R300(rdev)) {
1223                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1224                 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
1225                              RADEON_DISP_TV_SOURCE_CRTC);
1226             }
1227             if (rdev->family >= CHIP_R200) {
1228                 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
1229             } else {
1230                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1231             }
1232         } else {
1233             if (ASIC_IS_R300(rdev)) {
1234                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1235                 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
1236             }
1237             if (rdev->family >= CHIP_R200) {
1238                 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
1239             } else {
1240                 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1241             }
1242         }
1243         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1244     } else {
1245 
1246         dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
1247 
1248         if (radeon_crtc->crtc_id == 0) {
1249             if (ASIC_IS_R300(rdev)) {
1250                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1251                 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
1252             } else if (rdev->family == CHIP_R200) {
1253                 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1254                           RADEON_FP2_DVO_RATE_SEL_SDR);
1255             } else
1256                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1257         } else {
1258             if (ASIC_IS_R300(rdev)) {
1259                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1260                 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1261             } else if (rdev->family == CHIP_R200) {
1262                 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1263                           RADEON_FP2_DVO_RATE_SEL_SDR);
1264                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1265             } else
1266                 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1267         }
1268         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1269     }
1270 
1271     if (ASIC_IS_R300(rdev)) {
1272         WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1273         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1274     } else if (rdev->family != CHIP_R200)
1275         WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1276     else if (rdev->family == CHIP_R200)
1277         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1278 
1279     if (rdev->family >= CHIP_R200)
1280         WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1281 
1282     if (is_tv)
1283         radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
1284 
1285     if (rdev->is_atom_bios)
1286         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1287     else
1288         radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1289 
1290 }
1291 
1292 static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1293                   struct drm_connector *connector)
1294 {
1295     struct drm_device *dev = encoder->dev;
1296     struct radeon_device *rdev = dev->dev_private;
1297     uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1298     uint32_t disp_output_cntl, gpiopad_a, tmp;
1299     bool found = false;
1300 
1301     /* save regs needed */
1302     gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1303     dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1304     crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1305     dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1306     tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1307     disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1308 
1309     WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1310 
1311     WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1312 
1313     WREG32(RADEON_CRTC2_GEN_CNTL,
1314            RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1315 
1316     tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1317     tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1318     WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1319 
1320     WREG32(RADEON_DAC_EXT_CNTL,
1321            RADEON_DAC2_FORCE_BLANK_OFF_EN |
1322            RADEON_DAC2_FORCE_DATA_EN |
1323            RADEON_DAC_FORCE_DATA_SEL_RGB |
1324            (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1325 
1326     WREG32(RADEON_TV_DAC_CNTL,
1327            RADEON_TV_DAC_STD_NTSC |
1328            (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1329            (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1330 
1331     RREG32(RADEON_TV_DAC_CNTL);
1332     mdelay(4);
1333 
1334     WREG32(RADEON_TV_DAC_CNTL,
1335            RADEON_TV_DAC_NBLANK |
1336            RADEON_TV_DAC_NHOLD |
1337            RADEON_TV_MONITOR_DETECT_EN |
1338            RADEON_TV_DAC_STD_NTSC |
1339            (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1340            (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1341 
1342     RREG32(RADEON_TV_DAC_CNTL);
1343     mdelay(6);
1344 
1345     tmp = RREG32(RADEON_TV_DAC_CNTL);
1346     if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1347         found = true;
1348         DRM_DEBUG_KMS("S-video TV connection detected\n");
1349     } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1350         found = true;
1351         DRM_DEBUG_KMS("Composite TV connection detected\n");
1352     }
1353 
1354     WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1355     WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1356     WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1357     WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1358     WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1359     WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1360     return found;
1361 }
1362 
1363 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1364                     struct drm_connector *connector)
1365 {
1366     struct drm_device *dev = encoder->dev;
1367     struct radeon_device *rdev = dev->dev_private;
1368     uint32_t tv_dac_cntl, dac_cntl2;
1369     uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1370     bool found = false;
1371 
1372     if (ASIC_IS_R300(rdev))
1373         return r300_legacy_tv_detect(encoder, connector);
1374 
1375     dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1376     tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1377     tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1378     config_cntl = RREG32(RADEON_CONFIG_CNTL);
1379     tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1380 
1381     tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1382     WREG32(RADEON_DAC_CNTL2, tmp);
1383 
1384     tmp = tv_master_cntl | RADEON_TV_ON;
1385     tmp &= ~(RADEON_TV_ASYNC_RST |
1386          RADEON_RESTART_PHASE_FIX |
1387          RADEON_CRT_FIFO_CE_EN |
1388          RADEON_TV_FIFO_CE_EN |
1389          RADEON_RE_SYNC_NOW_SEL_MASK);
1390     tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1391     WREG32(RADEON_TV_MASTER_CNTL, tmp);
1392 
1393     tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1394         RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1395         (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1396 
1397     if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1398         tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1399     else
1400         tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1401     WREG32(RADEON_TV_DAC_CNTL, tmp);
1402 
1403     tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1404         RADEON_RED_MX_FORCE_DAC_DATA |
1405         RADEON_GRN_MX_FORCE_DAC_DATA |
1406         RADEON_BLU_MX_FORCE_DAC_DATA |
1407         (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1408     WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1409 
1410     mdelay(3);
1411     tmp = RREG32(RADEON_TV_DAC_CNTL);
1412     if (tmp & RADEON_TV_DAC_GDACDET) {
1413         found = true;
1414         DRM_DEBUG_KMS("S-video TV connection detected\n");
1415     } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1416         found = true;
1417         DRM_DEBUG_KMS("Composite TV connection detected\n");
1418     }
1419 
1420     WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1421     WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1422     WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1423     WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1424     return found;
1425 }
1426 
1427 static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder,
1428                      struct drm_connector *connector)
1429 {
1430     struct drm_device *dev = encoder->dev;
1431     struct radeon_device *rdev = dev->dev_private;
1432     uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl;
1433     uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c;
1434     uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f;
1435     uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp;
1436     uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid;
1437     bool found = false;
1438     int i;
1439 
1440     /* save the regs we need */
1441     gpio_monid = RREG32(RADEON_GPIO_MONID);
1442     fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1443     disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1444     crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1445     disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A);
1446     disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B);
1447     disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C);
1448     disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D);
1449     disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E);
1450     disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F);
1451     crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP);
1452     crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP);
1453     crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID);
1454     crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID);
1455 
1456     tmp = RREG32(RADEON_GPIO_MONID);
1457     tmp &= ~RADEON_GPIO_A_0;
1458     WREG32(RADEON_GPIO_MONID, tmp);
1459 
1460     WREG32(RADEON_FP2_GEN_CNTL, (RADEON_FP2_ON |
1461                      RADEON_FP2_PANEL_FORMAT |
1462                      R200_FP2_SOURCE_SEL_TRANS_UNIT |
1463                      RADEON_FP2_DVO_EN |
1464                      R200_FP2_DVO_RATE_SEL_SDR));
1465 
1466     WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX |
1467                      RADEON_DISP_TRANS_MATRIX_GRAPHICS));
1468 
1469     WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN |
1470                        RADEON_CRTC2_DISP_REQ_EN_B));
1471 
1472     WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000);
1473     WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0);
1474     WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000);
1475     WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0);
1476     WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000);
1477     WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0);
1478 
1479     WREG32(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008);
1480     WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800);
1481     WREG32(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001);
1482     WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080);
1483 
1484     for (i = 0; i < 200; i++) {
1485         tmp = RREG32(RADEON_GPIO_MONID);
1486         if (tmp & RADEON_GPIO_Y_0)
1487             found = true;
1488 
1489         if (found)
1490             break;
1491 
1492         if (!drm_can_sleep())
1493             mdelay(1);
1494         else
1495             msleep(1);
1496     }
1497 
1498     /* restore the regs we used */
1499     WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a);
1500     WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b);
1501     WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c);
1502     WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d);
1503     WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e);
1504     WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f);
1505     WREG32(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp);
1506     WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp);
1507     WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);
1508     WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);
1509     WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1510     WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1511     WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1512     WREG32(RADEON_GPIO_MONID, gpio_monid);
1513 
1514     return found;
1515 }
1516 
1517 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1518                                  struct drm_connector *connector)
1519 {
1520     struct drm_device *dev = encoder->dev;
1521     struct radeon_device *rdev = dev->dev_private;
1522     uint32_t crtc2_gen_cntl = 0, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1523     uint32_t gpiopad_a = 0, pixclks_cntl, tmp;
1524     uint32_t disp_output_cntl = 0, disp_hw_debug = 0, crtc_ext_cntl = 0;
1525     enum drm_connector_status found = connector_status_disconnected;
1526     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1527     struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1528     bool color = true;
1529     struct drm_crtc *crtc;
1530 
1531     /* find out if crtc2 is in use or if this encoder is using it */
1532     list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1533         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1534         if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
1535             if (encoder->crtc != crtc) {
1536                 return connector_status_disconnected;
1537             }
1538         }
1539     }
1540 
1541     if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1542         connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1543         connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1544         bool tv_detect;
1545 
1546         if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1547             return connector_status_disconnected;
1548 
1549         tv_detect = radeon_legacy_tv_detect(encoder, connector);
1550         if (tv_detect && tv_dac)
1551             found = connector_status_connected;
1552         return found;
1553     }
1554 
1555     /* don't probe if the encoder is being used for something else not CRT related */
1556     if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1557         DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1558         return connector_status_disconnected;
1559     }
1560 
1561     /* R200 uses an external DAC for secondary DAC */
1562     if (rdev->family == CHIP_R200) {
1563         if (radeon_legacy_ext_dac_detect(encoder, connector))
1564             found = connector_status_connected;
1565         return found;
1566     }
1567 
1568     /* save the regs we need */
1569     pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1570 
1571     if (rdev->flags & RADEON_SINGLE_CRTC) {
1572         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
1573     } else {
1574         if (ASIC_IS_R300(rdev)) {
1575             gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1576             disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1577         } else {
1578             disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1579         }
1580         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1581     }
1582     tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1583     dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1584     dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1585 
1586     tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1587                    | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1588     WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1589 
1590     if (rdev->flags & RADEON_SINGLE_CRTC) {
1591         tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
1592         WREG32(RADEON_CRTC_EXT_CNTL, tmp);
1593     } else {
1594         tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1595         tmp |= RADEON_CRTC2_CRT2_ON |
1596             (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1597         WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1598 
1599         if (ASIC_IS_R300(rdev)) {
1600             WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1601             tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1602             tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1603             WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1604         } else {
1605             tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1606             WREG32(RADEON_DISP_HW_DEBUG, tmp);
1607         }
1608     }
1609 
1610     tmp = RADEON_TV_DAC_NBLANK |
1611         RADEON_TV_DAC_NHOLD |
1612         RADEON_TV_MONITOR_DETECT_EN |
1613         RADEON_TV_DAC_STD_PS2;
1614 
1615     WREG32(RADEON_TV_DAC_CNTL, tmp);
1616 
1617     tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1618         RADEON_DAC2_FORCE_DATA_EN;
1619 
1620     if (color)
1621         tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1622     else
1623         tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1624 
1625     if (ASIC_IS_R300(rdev))
1626         tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1627     else
1628         tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1629 
1630     WREG32(RADEON_DAC_EXT_CNTL, tmp);
1631 
1632     tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1633     WREG32(RADEON_DAC_CNTL2, tmp);
1634 
1635     mdelay(10);
1636 
1637     if (ASIC_IS_R300(rdev)) {
1638         if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1639             found = connector_status_connected;
1640     } else {
1641         if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1642             found = connector_status_connected;
1643     }
1644 
1645     /* restore regs we used */
1646     WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1647     WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1648     WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1649 
1650     if (rdev->flags & RADEON_SINGLE_CRTC) {
1651         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
1652     } else {
1653         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1654         if (ASIC_IS_R300(rdev)) {
1655             WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1656             WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1657         } else {
1658             WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1659         }
1660     }
1661 
1662     WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1663 
1664     return found;
1665 
1666 }
1667 
1668 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1669     .dpms = radeon_legacy_tv_dac_dpms,
1670     .mode_fixup = radeon_legacy_mode_fixup,
1671     .prepare = radeon_legacy_tv_dac_prepare,
1672     .mode_set = radeon_legacy_tv_dac_mode_set,
1673     .commit = radeon_legacy_tv_dac_commit,
1674     .detect = radeon_legacy_tv_dac_detect,
1675     .disable = radeon_legacy_encoder_disable,
1676 };
1677 
1678 
1679 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1680     .destroy = radeon_enc_destroy,
1681 };
1682 
1683 
1684 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1685 {
1686     struct drm_device *dev = encoder->base.dev;
1687     struct radeon_device *rdev = dev->dev_private;
1688     struct radeon_encoder_int_tmds *tmds = NULL;
1689     bool ret;
1690 
1691     tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1692 
1693     if (!tmds)
1694         return NULL;
1695 
1696     if (rdev->is_atom_bios)
1697         ret = radeon_atombios_get_tmds_info(encoder, tmds);
1698     else
1699         ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1700 
1701     if (!ret)
1702         radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1703 
1704     return tmds;
1705 }
1706 
1707 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1708 {
1709     struct drm_device *dev = encoder->base.dev;
1710     struct radeon_device *rdev = dev->dev_private;
1711     struct radeon_encoder_ext_tmds *tmds = NULL;
1712     bool ret;
1713 
1714     if (rdev->is_atom_bios)
1715         return NULL;
1716 
1717     tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1718 
1719     if (!tmds)
1720         return NULL;
1721 
1722     ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1723 
1724     if (!ret)
1725         radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1726 
1727     return tmds;
1728 }
1729 
1730 void
1731 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1732 {
1733     struct radeon_device *rdev = dev->dev_private;
1734     struct drm_encoder *encoder;
1735     struct radeon_encoder *radeon_encoder;
1736 
1737     /* see if we already added it */
1738     list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1739         radeon_encoder = to_radeon_encoder(encoder);
1740         if (radeon_encoder->encoder_enum == encoder_enum) {
1741             radeon_encoder->devices |= supported_device;
1742             return;
1743         }
1744 
1745     }
1746 
1747     /* add a new one */
1748     radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1749     if (!radeon_encoder)
1750         return;
1751 
1752     encoder = &radeon_encoder->base;
1753     if (rdev->flags & RADEON_SINGLE_CRTC)
1754         encoder->possible_crtcs = 0x1;
1755     else
1756         encoder->possible_crtcs = 0x3;
1757 
1758     radeon_encoder->enc_priv = NULL;
1759 
1760     radeon_encoder->encoder_enum = encoder_enum;
1761     radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1762     radeon_encoder->devices = supported_device;
1763     radeon_encoder->rmx_type = RMX_OFF;
1764 
1765     switch (radeon_encoder->encoder_id) {
1766     case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1767         encoder->possible_crtcs = 0x1;
1768         drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs,
1769                  DRM_MODE_ENCODER_LVDS, NULL);
1770         drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1771         if (rdev->is_atom_bios)
1772             radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1773         else
1774             radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1775         radeon_encoder->rmx_type = RMX_FULL;
1776         break;
1777     case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1778         drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs,
1779                  DRM_MODE_ENCODER_TMDS, NULL);
1780         drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1781         radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1782         break;
1783     case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1784         drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs,
1785                  DRM_MODE_ENCODER_DAC, NULL);
1786         drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1787         if (rdev->is_atom_bios)
1788             radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1789         else
1790             radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1791         break;
1792     case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1793         drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs,
1794                  DRM_MODE_ENCODER_TVDAC, NULL);
1795         drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1796         if (rdev->is_atom_bios)
1797             radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1798         else
1799             radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1800         break;
1801     case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1802         drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs,
1803                  DRM_MODE_ENCODER_TMDS, NULL);
1804         drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1805         if (!rdev->is_atom_bios)
1806             radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
1807         break;
1808     }
1809 }
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