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0001 /*
0002  * Copyright 2007-8 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors: Dave Airlie
0024  *          Alex Deucher
0025  */
0026 
0027 #include <drm/drm_crtc_helper.h>
0028 #include <drm/drm_fb_helper.h>
0029 #include <drm/drm_fixed.h>
0030 #include <drm/drm_fourcc.h>
0031 #include <drm/drm_framebuffer.h>
0032 #include <drm/drm_vblank.h>
0033 #include <drm/radeon_drm.h>
0034 
0035 #include "atom.h"
0036 #include "radeon.h"
0037 
0038 static void radeon_overscan_setup(struct drm_crtc *crtc,
0039                   struct drm_display_mode *mode)
0040 {
0041     struct drm_device *dev = crtc->dev;
0042     struct radeon_device *rdev = dev->dev_private;
0043     struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
0044 
0045     WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
0046     WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
0047     WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
0048 }
0049 
0050 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
0051                        struct drm_display_mode *mode)
0052 {
0053     struct drm_device *dev = crtc->dev;
0054     struct radeon_device *rdev = dev->dev_private;
0055     struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
0056     int xres = mode->hdisplay;
0057     int yres = mode->vdisplay;
0058     bool hscale = true, vscale = true;
0059     int hsync_wid;
0060     int vsync_wid;
0061     int hsync_start;
0062     int blank_width;
0063     u32 scale, inc, crtc_more_cntl;
0064     u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
0065     u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
0066     u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
0067     struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
0068 
0069     fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
0070         (RADEON_VERT_STRETCH_RESERVED |
0071          RADEON_VERT_AUTO_RATIO_INC);
0072     fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
0073         (RADEON_HORZ_FP_LOOP_STRETCH |
0074          RADEON_HORZ_AUTO_RATIO_INC);
0075 
0076     crtc_more_cntl = 0;
0077     if ((rdev->family == CHIP_RS100) ||
0078         (rdev->family == CHIP_RS200)) {
0079         /* This is to workaround the asic bug for RMX, some versions
0080            of BIOS dosen't have this register initialized correctly. */
0081         crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
0082     }
0083 
0084 
0085     fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
0086                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
0087 
0088     hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
0089     if (!hsync_wid)
0090         hsync_wid = 1;
0091     hsync_start = mode->crtc_hsync_start - 8;
0092 
0093     fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
0094                   | ((hsync_wid & 0x3f) << 16)
0095                   | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
0096                  ? RADEON_CRTC_H_SYNC_POL
0097                  : 0));
0098 
0099     fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
0100                 | ((mode->crtc_vdisplay - 1) << 16));
0101 
0102     vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
0103     if (!vsync_wid)
0104         vsync_wid = 1;
0105 
0106     fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
0107                   | ((vsync_wid & 0x1f) << 16)
0108                   | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
0109                  ? RADEON_CRTC_V_SYNC_POL
0110                  : 0));
0111 
0112     fp_horz_vert_active = 0;
0113 
0114     if (native_mode->hdisplay == 0 ||
0115         native_mode->vdisplay == 0) {
0116         hscale = false;
0117         vscale = false;
0118     } else {
0119         if (xres > native_mode->hdisplay)
0120             xres = native_mode->hdisplay;
0121         if (yres > native_mode->vdisplay)
0122             yres = native_mode->vdisplay;
0123 
0124         if (xres == native_mode->hdisplay)
0125             hscale = false;
0126         if (yres == native_mode->vdisplay)
0127             vscale = false;
0128     }
0129 
0130     switch (radeon_crtc->rmx_type) {
0131     case RMX_FULL:
0132     case RMX_ASPECT:
0133         if (!hscale)
0134             fp_horz_stretch |= ((xres/8-1) << 16);
0135         else {
0136             inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
0137             scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
0138                 / native_mode->hdisplay + 1;
0139             fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
0140                     RADEON_HORZ_STRETCH_BLEND |
0141                     RADEON_HORZ_STRETCH_ENABLE |
0142                     ((native_mode->hdisplay/8-1) << 16));
0143         }
0144 
0145         if (!vscale)
0146             fp_vert_stretch |= ((yres-1) << 12);
0147         else {
0148             inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
0149             scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
0150                 / native_mode->vdisplay + 1;
0151             fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
0152                     RADEON_VERT_STRETCH_ENABLE |
0153                     RADEON_VERT_STRETCH_BLEND |
0154                     ((native_mode->vdisplay-1) << 12));
0155         }
0156         break;
0157     case RMX_CENTER:
0158         fp_horz_stretch |= ((xres/8-1) << 16);
0159         fp_vert_stretch |= ((yres-1) << 12);
0160 
0161         crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
0162                 RADEON_CRTC_AUTO_VERT_CENTER_EN);
0163 
0164         blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
0165         if (blank_width > 110)
0166             blank_width = 110;
0167 
0168         fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
0169                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
0170 
0171         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
0172         if (!hsync_wid)
0173             hsync_wid = 1;
0174 
0175         fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
0176                 | ((hsync_wid & 0x3f) << 16)
0177                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
0178                     ? RADEON_CRTC_H_SYNC_POL
0179                     : 0));
0180 
0181         fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
0182                 | ((mode->crtc_vdisplay - 1) << 16));
0183 
0184         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
0185         if (!vsync_wid)
0186             vsync_wid = 1;
0187 
0188         fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
0189                     | ((vsync_wid & 0x1f) << 16)
0190                     | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
0191                         ? RADEON_CRTC_V_SYNC_POL
0192                         : 0)));
0193 
0194         fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
0195                 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
0196         break;
0197     case RMX_OFF:
0198     default:
0199         fp_horz_stretch |= ((xres/8-1) << 16);
0200         fp_vert_stretch |= ((yres-1) << 12);
0201         break;
0202     }
0203 
0204     WREG32(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
0205     WREG32(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
0206     WREG32(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
0207     WREG32(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
0208     WREG32(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
0209     WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
0210     WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
0211     WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
0212 }
0213 
0214 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
0215 {
0216     struct radeon_device *rdev = dev->dev_private;
0217     int i = 0;
0218 
0219     /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
0220        the cause yet, but this workaround will mask the problem for now.
0221        Other chips usually will pass at the very first test, so the
0222        workaround shouldn't have any effect on them. */
0223     for (i = 0;
0224          (i < 10000 &&
0225           RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
0226          i++);
0227 }
0228 
0229 static void radeon_pll_write_update(struct drm_device *dev)
0230 {
0231     struct radeon_device *rdev = dev->dev_private;
0232 
0233     while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
0234 
0235     WREG32_PLL_P(RADEON_PPLL_REF_DIV,
0236                RADEON_PPLL_ATOMIC_UPDATE_W,
0237                ~(RADEON_PPLL_ATOMIC_UPDATE_W));
0238 }
0239 
0240 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
0241 {
0242     struct radeon_device *rdev = dev->dev_private;
0243     int i = 0;
0244 
0245 
0246     /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
0247        the cause yet, but this workaround will mask the problem for now.
0248        Other chips usually will pass at the very first test, so the
0249        workaround shouldn't have any effect on them. */
0250     for (i = 0;
0251          (i < 10000 &&
0252           RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
0253          i++);
0254 }
0255 
0256 static void radeon_pll2_write_update(struct drm_device *dev)
0257 {
0258     struct radeon_device *rdev = dev->dev_private;
0259 
0260     while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
0261 
0262     WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
0263                RADEON_P2PLL_ATOMIC_UPDATE_W,
0264                ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
0265 }
0266 
0267 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
0268                        uint16_t fb_div)
0269 {
0270     unsigned int vcoFreq;
0271 
0272     if (!ref_div)
0273         return 1;
0274 
0275     vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
0276 
0277     /*
0278      * This is horribly crude: the VCO frequency range is divided into
0279      * 3 parts, each part having a fixed PLL gain value.
0280      */
0281     if (vcoFreq >= 30000)
0282         /*
0283          * [300..max] MHz : 7
0284          */
0285         return 7;
0286     else if (vcoFreq >= 18000)
0287         /*
0288          * [180..300) MHz : 4
0289          */
0290         return 4;
0291     else
0292         /*
0293          * [0..180) MHz : 1
0294          */
0295         return 1;
0296 }
0297 
0298 static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
0299 {
0300     struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
0301     struct drm_device *dev = crtc->dev;
0302     struct radeon_device *rdev = dev->dev_private;
0303     uint32_t crtc_ext_cntl = 0;
0304     uint32_t mask;
0305 
0306     if (radeon_crtc->crtc_id)
0307         mask = (RADEON_CRTC2_DISP_DIS |
0308             RADEON_CRTC2_VSYNC_DIS |
0309             RADEON_CRTC2_HSYNC_DIS |
0310             RADEON_CRTC2_DISP_REQ_EN_B);
0311     else
0312         mask = (RADEON_CRTC_DISPLAY_DIS |
0313             RADEON_CRTC_VSYNC_DIS |
0314             RADEON_CRTC_HSYNC_DIS);
0315 
0316     /*
0317      * On all dual CRTC GPUs this bit controls the CRTC of the primary DAC.
0318      * Therefore it is set in the DAC DMPS function.
0319      * This is different for GPU's with a single CRTC but a primary and a
0320      * TV DAC: here it controls the single CRTC no matter where it is
0321      * routed. Therefore we set it here.
0322      */
0323     if (rdev->flags & RADEON_SINGLE_CRTC)
0324         crtc_ext_cntl = RADEON_CRTC_CRT_ON;
0325     
0326     switch (mode) {
0327     case DRM_MODE_DPMS_ON:
0328         radeon_crtc->enabled = true;
0329         /* adjust pm to dpms changes BEFORE enabling crtcs */
0330         radeon_pm_compute_clocks(rdev);
0331         if (radeon_crtc->crtc_id)
0332             WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
0333         else {
0334             WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
0335                                      RADEON_CRTC_DISP_REQ_EN_B));
0336             WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));
0337         }
0338         if (dev->num_crtcs > radeon_crtc->crtc_id)
0339             drm_crtc_vblank_on(crtc);
0340         radeon_crtc_load_lut(crtc);
0341         break;
0342     case DRM_MODE_DPMS_STANDBY:
0343     case DRM_MODE_DPMS_SUSPEND:
0344     case DRM_MODE_DPMS_OFF:
0345         if (dev->num_crtcs > radeon_crtc->crtc_id)
0346             drm_crtc_vblank_off(crtc);
0347         if (radeon_crtc->crtc_id)
0348             WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
0349         else {
0350             WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
0351                                             RADEON_CRTC_DISP_REQ_EN_B));
0352             WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl));
0353         }
0354         radeon_crtc->enabled = false;
0355         /* adjust pm to dpms changes AFTER disabling crtcs */
0356         radeon_pm_compute_clocks(rdev);
0357         break;
0358     }
0359 }
0360 
0361 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
0362              struct drm_framebuffer *old_fb)
0363 {
0364     return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
0365 }
0366 
0367 int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
0368                 struct drm_framebuffer *fb,
0369                 int x, int y, enum mode_set_atomic state)
0370 {
0371     return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
0372 }
0373 
0374 int radeon_crtc_do_set_base(struct drm_crtc *crtc,
0375              struct drm_framebuffer *fb,
0376              int x, int y, int atomic)
0377 {
0378     struct drm_device *dev = crtc->dev;
0379     struct radeon_device *rdev = dev->dev_private;
0380     struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
0381     struct drm_framebuffer *target_fb;
0382     struct drm_gem_object *obj;
0383     struct radeon_bo *rbo;
0384     uint64_t base;
0385     uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
0386     uint32_t crtc_pitch, pitch_pixels;
0387     uint32_t tiling_flags;
0388     int format;
0389     uint32_t gen_cntl_reg, gen_cntl_val;
0390     int r;
0391 
0392     DRM_DEBUG_KMS("\n");
0393     /* no fb bound */
0394     if (!atomic && !crtc->primary->fb) {
0395         DRM_DEBUG_KMS("No FB bound\n");
0396         return 0;
0397     }
0398 
0399     if (atomic)
0400         target_fb = fb;
0401     else
0402         target_fb = crtc->primary->fb;
0403 
0404     switch (target_fb->format->cpp[0] * 8) {
0405     case 8:
0406         format = 2;
0407         break;
0408     case 15:      /*  555 */
0409         format = 3;
0410         break;
0411     case 16:      /*  565 */
0412         format = 4;
0413         break;
0414     case 24:      /*  RGB */
0415         format = 5;
0416         break;
0417     case 32:      /* xRGB */
0418         format = 6;
0419         break;
0420     default:
0421         return false;
0422     }
0423 
0424     /* Pin framebuffer & get tilling informations */
0425     obj = target_fb->obj[0];
0426     rbo = gem_to_radeon_bo(obj);
0427 retry:
0428     r = radeon_bo_reserve(rbo, false);
0429     if (unlikely(r != 0))
0430         return r;
0431     /* Only 27 bit offset for legacy CRTC */
0432     r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27,
0433                      &base);
0434     if (unlikely(r != 0)) {
0435         radeon_bo_unreserve(rbo);
0436 
0437         /* On old GPU like RN50 with little vram pining can fails because
0438          * current fb is taking all space needed. So instead of unpining
0439          * the old buffer after pining the new one, first unpin old one
0440          * and then retry pining new one.
0441          *
0442          * As only master can set mode only master can pin and it is
0443          * unlikely the master client will race with itself especialy
0444          * on those old gpu with single crtc.
0445          *
0446          * We don't shutdown the display controller because new buffer
0447          * will end up in same spot.
0448          */
0449         if (!atomic && fb && fb != crtc->primary->fb) {
0450             struct radeon_bo *old_rbo;
0451             unsigned long nsize, osize;
0452 
0453             old_rbo = gem_to_radeon_bo(fb->obj[0]);
0454             osize = radeon_bo_size(old_rbo);
0455             nsize = radeon_bo_size(rbo);
0456             if (nsize <= osize && !radeon_bo_reserve(old_rbo, false)) {
0457                 radeon_bo_unpin(old_rbo);
0458                 radeon_bo_unreserve(old_rbo);
0459                 fb = NULL;
0460                 goto retry;
0461             }
0462         }
0463         return -EINVAL;
0464     }
0465     radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
0466     radeon_bo_unreserve(rbo);
0467     if (tiling_flags & RADEON_TILING_MICRO)
0468         DRM_ERROR("trying to scanout microtiled buffer\n");
0469 
0470     /* if scanout was in GTT this really wouldn't work */
0471     /* crtc offset is from display base addr not FB location */
0472     radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
0473 
0474     base -= radeon_crtc->legacy_display_base_addr;
0475 
0476     crtc_offset_cntl = 0;
0477 
0478     pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
0479     crtc_pitch = DIV_ROUND_UP(pitch_pixels * target_fb->format->cpp[0] * 8,
0480                   target_fb->format->cpp[0] * 8 * 8);
0481     crtc_pitch |= crtc_pitch << 16;
0482 
0483     crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
0484     if (tiling_flags & RADEON_TILING_MACRO) {
0485         if (ASIC_IS_R300(rdev))
0486             crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
0487                          R300_CRTC_MICRO_TILE_BUFFER_DIS |
0488                          R300_CRTC_MACRO_TILE_EN);
0489         else
0490             crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
0491     } else {
0492         if (ASIC_IS_R300(rdev))
0493             crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
0494                           R300_CRTC_MICRO_TILE_BUFFER_DIS |
0495                           R300_CRTC_MACRO_TILE_EN);
0496         else
0497             crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
0498     }
0499 
0500     if (tiling_flags & RADEON_TILING_MACRO) {
0501         if (ASIC_IS_R300(rdev)) {
0502             crtc_tile_x0_y0 = x | (y << 16);
0503             base &= ~0x7ff;
0504         } else {
0505             int byteshift = target_fb->format->cpp[0] * 8 >> 4;
0506             int tile_addr = (((y >> 3) * pitch_pixels +  x) >> (8 - byteshift)) << 11;
0507             base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
0508             crtc_offset_cntl |= (y % 16);
0509         }
0510     } else {
0511         int offset = y * pitch_pixels + x;
0512         switch (target_fb->format->cpp[0] * 8) {
0513         case 8:
0514             offset *= 1;
0515             break;
0516         case 15:
0517         case 16:
0518             offset *= 2;
0519             break;
0520         case 24:
0521             offset *= 3;
0522             break;
0523         case 32:
0524             offset *= 4;
0525             break;
0526         default:
0527             return false;
0528         }
0529         base += offset;
0530     }
0531 
0532     base &= ~7;
0533 
0534     if (radeon_crtc->crtc_id == 1)
0535         gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
0536     else
0537         gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
0538 
0539     gen_cntl_val = RREG32(gen_cntl_reg);
0540     gen_cntl_val &= ~(0xf << 8);
0541     gen_cntl_val |= (format << 8);
0542     gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK;
0543     WREG32(gen_cntl_reg, gen_cntl_val);
0544 
0545     crtc_offset = (u32)base;
0546 
0547     WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
0548 
0549     if (ASIC_IS_R300(rdev)) {
0550         if (radeon_crtc->crtc_id)
0551             WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
0552         else
0553             WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
0554     }
0555     WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
0556     WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
0557     WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
0558 
0559     if (!atomic && fb && fb != crtc->primary->fb) {
0560         rbo = gem_to_radeon_bo(fb->obj[0]);
0561         r = radeon_bo_reserve(rbo, false);
0562         if (unlikely(r != 0))
0563             return r;
0564         radeon_bo_unpin(rbo);
0565         radeon_bo_unreserve(rbo);
0566     }
0567 
0568     /* Bytes per pixel may have changed */
0569     radeon_bandwidth_update(rdev);
0570 
0571     return 0;
0572 }
0573 
0574 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
0575 {
0576     struct drm_device *dev = crtc->dev;
0577     struct radeon_device *rdev = dev->dev_private;
0578     struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
0579     const struct drm_framebuffer *fb = crtc->primary->fb;
0580     struct drm_encoder *encoder;
0581     int format;
0582     int hsync_start;
0583     int hsync_wid;
0584     int vsync_wid;
0585     uint32_t crtc_h_total_disp;
0586     uint32_t crtc_h_sync_strt_wid;
0587     uint32_t crtc_v_total_disp;
0588     uint32_t crtc_v_sync_strt_wid;
0589     bool is_tv = false;
0590 
0591     DRM_DEBUG_KMS("\n");
0592     list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
0593         if (encoder->crtc == crtc) {
0594             struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0595             if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
0596                 is_tv = true;
0597                 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
0598                 break;
0599             }
0600         }
0601     }
0602 
0603     switch (fb->format->cpp[0] * 8) {
0604     case 8:
0605         format = 2;
0606         break;
0607     case 15:      /*  555 */
0608         format = 3;
0609         break;
0610     case 16:      /*  565 */
0611         format = 4;
0612         break;
0613     case 24:      /*  RGB */
0614         format = 5;
0615         break;
0616     case 32:      /* xRGB */
0617         format = 6;
0618         break;
0619     default:
0620         return false;
0621     }
0622 
0623     crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
0624                  | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
0625 
0626     hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
0627     if (!hsync_wid)
0628         hsync_wid = 1;
0629     hsync_start = mode->crtc_hsync_start - 8;
0630 
0631     crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
0632                 | ((hsync_wid & 0x3f) << 16)
0633                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
0634                    ? RADEON_CRTC_H_SYNC_POL
0635                    : 0));
0636 
0637     /* This works for double scan mode. */
0638     crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
0639                  | ((mode->crtc_vdisplay - 1) << 16));
0640 
0641     vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
0642     if (!vsync_wid)
0643         vsync_wid = 1;
0644 
0645     crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
0646                 | ((vsync_wid & 0x1f) << 16)
0647                 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
0648                    ? RADEON_CRTC_V_SYNC_POL
0649                    : 0));
0650 
0651     if (radeon_crtc->crtc_id) {
0652         uint32_t crtc2_gen_cntl;
0653         uint32_t disp2_merge_cntl;
0654 
0655         /* if TV DAC is enabled for another crtc and keep it enabled */
0656         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
0657         crtc2_gen_cntl |= ((format << 8)
0658                    | RADEON_CRTC2_VSYNC_DIS
0659                    | RADEON_CRTC2_HSYNC_DIS
0660                    | RADEON_CRTC2_DISP_DIS
0661                    | RADEON_CRTC2_DISP_REQ_EN_B
0662                    | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
0663                       ? RADEON_CRTC2_DBL_SCAN_EN
0664                       : 0)
0665                    | ((mode->flags & DRM_MODE_FLAG_CSYNC)
0666                       ? RADEON_CRTC2_CSYNC_EN
0667                       : 0)
0668                    | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
0669                       ? RADEON_CRTC2_INTERLACE_EN
0670                       : 0));
0671 
0672         /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
0673         if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
0674             crtc2_gen_cntl |= RADEON_CRTC2_EN;
0675 
0676         disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
0677         disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
0678 
0679         WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
0680         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
0681 
0682         WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
0683         WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
0684     } else {
0685         uint32_t crtc_gen_cntl;
0686         uint32_t crtc_ext_cntl;
0687         uint32_t disp_merge_cntl;
0688 
0689         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
0690         crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
0691                  | (format << 8)
0692                  | RADEON_CRTC_DISP_REQ_EN_B
0693                  | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
0694                     ? RADEON_CRTC_DBL_SCAN_EN
0695                     : 0)
0696                  | ((mode->flags & DRM_MODE_FLAG_CSYNC)
0697                     ? RADEON_CRTC_CSYNC_EN
0698                     : 0)
0699                  | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
0700                     ? RADEON_CRTC_INTERLACE_EN
0701                     : 0));
0702 
0703         /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
0704         if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
0705             crtc_gen_cntl |= RADEON_CRTC_EN;
0706 
0707         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
0708         crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
0709                   RADEON_CRTC_VSYNC_DIS |
0710                   RADEON_CRTC_HSYNC_DIS |
0711                   RADEON_CRTC_DISPLAY_DIS);
0712 
0713         disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
0714         disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
0715 
0716         WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
0717         WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
0718         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
0719     }
0720 
0721     if (is_tv)
0722         radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
0723                          &crtc_h_sync_strt_wid, &crtc_v_total_disp,
0724                          &crtc_v_sync_strt_wid);
0725 
0726     WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
0727     WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
0728     WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
0729     WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
0730 
0731     return true;
0732 }
0733 
0734 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
0735 {
0736     struct drm_device *dev = crtc->dev;
0737     struct radeon_device *rdev = dev->dev_private;
0738     struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
0739     struct drm_encoder *encoder;
0740     uint32_t feedback_div = 0;
0741     uint32_t frac_fb_div = 0;
0742     uint32_t reference_div = 0;
0743     uint32_t post_divider = 0;
0744     uint32_t freq = 0;
0745     uint8_t pll_gain;
0746     bool use_bios_divs = false;
0747     /* PLL registers */
0748     uint32_t pll_ref_div = 0;
0749     uint32_t pll_fb_post_div = 0;
0750     uint32_t htotal_cntl = 0;
0751     bool is_tv = false;
0752     struct radeon_pll *pll;
0753 
0754     struct {
0755         int divider;
0756         int bitvalue;
0757     } *post_div, post_divs[]   = {
0758         /* From RAGE 128 VR/RAGE 128 GL Register
0759          * Reference Manual (Technical Reference
0760          * Manual P/N RRG-G04100-C Rev. 0.04), page
0761          * 3-17 (PLL_DIV_[3:0]).
0762          */
0763         {  1, 0 },              /* VCLK_SRC                 */
0764         {  2, 1 },              /* VCLK_SRC/2               */
0765         {  4, 2 },              /* VCLK_SRC/4               */
0766         {  8, 3 },              /* VCLK_SRC/8               */
0767         {  3, 4 },              /* VCLK_SRC/3               */
0768         { 16, 5 },              /* VCLK_SRC/16              */
0769         {  6, 6 },              /* VCLK_SRC/6               */
0770         { 12, 7 },              /* VCLK_SRC/12              */
0771         {  0, 0 }
0772     };
0773 
0774     if (radeon_crtc->crtc_id)
0775         pll = &rdev->clock.p2pll;
0776     else
0777         pll = &rdev->clock.p1pll;
0778 
0779     pll->flags = RADEON_PLL_LEGACY;
0780 
0781     if (mode->clock > 200000) /* range limits??? */
0782         pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
0783     else
0784         pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
0785 
0786     list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
0787         if (encoder->crtc == crtc) {
0788             struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0789 
0790             if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
0791                 is_tv = true;
0792                 break;
0793             }
0794 
0795             if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
0796                 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
0797             if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
0798                 if (!rdev->is_atom_bios) {
0799                     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0800                     struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
0801                     if (lvds) {
0802                         if (lvds->use_bios_dividers) {
0803                             pll_ref_div = lvds->panel_ref_divider;
0804                             pll_fb_post_div   = (lvds->panel_fb_divider |
0805                                          (lvds->panel_post_divider << 16));
0806                             htotal_cntl  = 0;
0807                             use_bios_divs = true;
0808                         }
0809                     }
0810                 }
0811                 pll->flags |= RADEON_PLL_USE_REF_DIV;
0812             }
0813         }
0814     }
0815 
0816     DRM_DEBUG_KMS("\n");
0817 
0818     if (!use_bios_divs) {
0819         radeon_compute_pll_legacy(pll, mode->clock,
0820                       &freq, &feedback_div, &frac_fb_div,
0821                       &reference_div, &post_divider);
0822 
0823         for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
0824             if (post_div->divider == post_divider)
0825                 break;
0826         }
0827 
0828         if (!post_div->divider)
0829             post_div = &post_divs[0];
0830 
0831         DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n",
0832               (unsigned)freq,
0833               feedback_div,
0834               reference_div,
0835               post_divider);
0836 
0837         pll_ref_div   = reference_div;
0838 #if defined(__powerpc__) && (0) /* TODO */
0839         /* apparently programming this otherwise causes a hang??? */
0840         if (info->MacModel == RADEON_MAC_IBOOK)
0841             pll_fb_post_div = 0x000600ad;
0842         else
0843 #endif
0844             pll_fb_post_div     = (feedback_div | (post_div->bitvalue << 16));
0845 
0846         htotal_cntl    = mode->htotal & 0x7;
0847 
0848     }
0849 
0850     pll_gain = radeon_compute_pll_gain(pll->reference_freq,
0851                        pll_ref_div & 0x3ff,
0852                        pll_fb_post_div & 0x7ff);
0853 
0854     if (radeon_crtc->crtc_id) {
0855         uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
0856                       ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
0857                      RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
0858 
0859         if (is_tv) {
0860             radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
0861                              &pll_ref_div, &pll_fb_post_div,
0862                              &pixclks_cntl);
0863         }
0864 
0865         WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
0866                  RADEON_PIX2CLK_SRC_SEL_CPUCLK,
0867                  ~(RADEON_PIX2CLK_SRC_SEL_MASK));
0868 
0869         WREG32_PLL_P(RADEON_P2PLL_CNTL,
0870                  RADEON_P2PLL_RESET
0871                  | RADEON_P2PLL_ATOMIC_UPDATE_EN
0872                  | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
0873                  ~(RADEON_P2PLL_RESET
0874                    | RADEON_P2PLL_ATOMIC_UPDATE_EN
0875                    | RADEON_P2PLL_PVG_MASK));
0876 
0877         WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
0878                  pll_ref_div,
0879                  ~RADEON_P2PLL_REF_DIV_MASK);
0880 
0881         WREG32_PLL_P(RADEON_P2PLL_DIV_0,
0882                  pll_fb_post_div,
0883                  ~RADEON_P2PLL_FB0_DIV_MASK);
0884 
0885         WREG32_PLL_P(RADEON_P2PLL_DIV_0,
0886                  pll_fb_post_div,
0887                  ~RADEON_P2PLL_POST0_DIV_MASK);
0888 
0889         radeon_pll2_write_update(dev);
0890         radeon_pll2_wait_for_read_update_complete(dev);
0891 
0892         WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
0893 
0894         WREG32_PLL_P(RADEON_P2PLL_CNTL,
0895                  0,
0896                  ~(RADEON_P2PLL_RESET
0897                    | RADEON_P2PLL_SLEEP
0898                    | RADEON_P2PLL_ATOMIC_UPDATE_EN));
0899 
0900         DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
0901               (unsigned)pll_ref_div,
0902               (unsigned)pll_fb_post_div,
0903               (unsigned)htotal_cntl,
0904               RREG32_PLL(RADEON_P2PLL_CNTL));
0905         DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n",
0906               (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
0907               (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
0908               (unsigned)((pll_fb_post_div &
0909                       RADEON_P2PLL_POST0_DIV_MASK) >> 16));
0910 
0911         mdelay(50); /* Let the clock to lock */
0912 
0913         WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
0914                  RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
0915                  ~(RADEON_PIX2CLK_SRC_SEL_MASK));
0916 
0917         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
0918     } else {
0919         uint32_t pixclks_cntl;
0920 
0921 
0922         if (is_tv) {
0923             pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
0924             radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
0925                              &pll_fb_post_div, &pixclks_cntl);
0926         }
0927 
0928         if (rdev->flags & RADEON_IS_MOBILITY) {
0929             /* A temporal workaround for the occasional blanking on certain laptop panels.
0930                This appears to related to the PLL divider registers (fail to lock?).
0931                It occurs even when all dividers are the same with their old settings.
0932                In this case we really don't need to fiddle with PLL registers.
0933                By doing this we can avoid the blanking problem with some panels.
0934             */
0935             if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
0936                 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
0937                          (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
0938                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
0939                      RADEON_PLL_DIV_SEL,
0940                      ~(RADEON_PLL_DIV_SEL));
0941                 r100_pll_errata_after_index(rdev);
0942                 return;
0943             }
0944         }
0945 
0946         WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
0947                  RADEON_VCLK_SRC_SEL_CPUCLK,
0948                  ~(RADEON_VCLK_SRC_SEL_MASK));
0949         WREG32_PLL_P(RADEON_PPLL_CNTL,
0950                  RADEON_PPLL_RESET
0951                  | RADEON_PPLL_ATOMIC_UPDATE_EN
0952                  | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
0953                  | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
0954                  ~(RADEON_PPLL_RESET
0955                    | RADEON_PPLL_ATOMIC_UPDATE_EN
0956                    | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
0957                    | RADEON_PPLL_PVG_MASK));
0958 
0959         WREG32_P(RADEON_CLOCK_CNTL_INDEX,
0960              RADEON_PLL_DIV_SEL,
0961              ~(RADEON_PLL_DIV_SEL));
0962         r100_pll_errata_after_index(rdev);
0963 
0964         if (ASIC_IS_R300(rdev) ||
0965             (rdev->family == CHIP_RS300) ||
0966             (rdev->family == CHIP_RS400) ||
0967             (rdev->family == CHIP_RS480)) {
0968             if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
0969                 /* When restoring console mode, use saved PPLL_REF_DIV
0970                  * setting.
0971                  */
0972                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
0973                          pll_ref_div,
0974                          0);
0975             } else {
0976                 /* R300 uses ref_div_acc field as real ref divider */
0977                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
0978                          (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
0979                          ~R300_PPLL_REF_DIV_ACC_MASK);
0980             }
0981         } else
0982             WREG32_PLL_P(RADEON_PPLL_REF_DIV,
0983                      pll_ref_div,
0984                      ~RADEON_PPLL_REF_DIV_MASK);
0985 
0986         WREG32_PLL_P(RADEON_PPLL_DIV_3,
0987                  pll_fb_post_div,
0988                  ~RADEON_PPLL_FB3_DIV_MASK);
0989 
0990         WREG32_PLL_P(RADEON_PPLL_DIV_3,
0991                  pll_fb_post_div,
0992                  ~RADEON_PPLL_POST3_DIV_MASK);
0993 
0994         radeon_pll_write_update(dev);
0995         radeon_pll_wait_for_read_update_complete(dev);
0996 
0997         WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
0998 
0999         WREG32_PLL_P(RADEON_PPLL_CNTL,
1000                  0,
1001                  ~(RADEON_PPLL_RESET
1002                    | RADEON_PPLL_SLEEP
1003                    | RADEON_PPLL_ATOMIC_UPDATE_EN
1004                    | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
1005 
1006         DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
1007               pll_ref_div,
1008               pll_fb_post_div,
1009               (unsigned)htotal_cntl,
1010               RREG32_PLL(RADEON_PPLL_CNTL));
1011         DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n",
1012               pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
1013               pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
1014               (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
1015 
1016         mdelay(50); /* Let the clock to lock */
1017 
1018         WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
1019                  RADEON_VCLK_SRC_SEL_PPLLCLK,
1020                  ~(RADEON_VCLK_SRC_SEL_MASK));
1021 
1022         if (is_tv)
1023             WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1024     }
1025 }
1026 
1027 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
1028                    const struct drm_display_mode *mode,
1029                    struct drm_display_mode *adjusted_mode)
1030 {
1031     if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1032         return false;
1033     return true;
1034 }
1035 
1036 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1037                  struct drm_display_mode *mode,
1038                  struct drm_display_mode *adjusted_mode,
1039                  int x, int y, struct drm_framebuffer *old_fb)
1040 {
1041     struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1042 
1043     /* TODO TV */
1044     radeon_crtc_set_base(crtc, x, y, old_fb);
1045     radeon_set_crtc_timing(crtc, adjusted_mode);
1046     radeon_set_pll(crtc, adjusted_mode);
1047     radeon_overscan_setup(crtc, adjusted_mode);
1048     if (radeon_crtc->crtc_id == 0) {
1049         radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
1050     } else {
1051         if (radeon_crtc->rmx_type != RMX_OFF) {
1052             /* FIXME: only first crtc has rmx what should we
1053              * do ?
1054              */
1055             DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1056         }
1057     }
1058     radeon_cursor_reset(crtc);
1059     return 0;
1060 }
1061 
1062 static void radeon_crtc_prepare(struct drm_crtc *crtc)
1063 {
1064     struct drm_device *dev = crtc->dev;
1065     struct drm_crtc *crtci;
1066 
1067     /*
1068     * The hardware wedges sometimes if you reconfigure one CRTC
1069     * whilst another is running (see fdo bug #24611).
1070     */
1071     list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
1072         radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
1073 }
1074 
1075 static void radeon_crtc_commit(struct drm_crtc *crtc)
1076 {
1077     struct drm_device *dev = crtc->dev;
1078     struct drm_crtc *crtci;
1079 
1080     /*
1081     * Reenable the CRTCs that should be running.
1082     */
1083     list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1084         if (crtci->enabled)
1085             radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1086     }
1087 }
1088 
1089 static void radeon_crtc_disable(struct drm_crtc *crtc)
1090 {
1091     radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1092     if (crtc->primary->fb) {
1093         int r;
1094         struct radeon_bo *rbo;
1095 
1096         rbo = gem_to_radeon_bo(crtc->primary->fb->obj[0]);
1097         r = radeon_bo_reserve(rbo, false);
1098         if (unlikely(r))
1099             DRM_ERROR("failed to reserve rbo before unpin\n");
1100         else {
1101             radeon_bo_unpin(rbo);
1102             radeon_bo_unreserve(rbo);
1103         }
1104     }
1105 }
1106 
1107 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1108     .dpms = radeon_crtc_dpms,
1109     .mode_fixup = radeon_crtc_mode_fixup,
1110     .mode_set = radeon_crtc_mode_set,
1111     .mode_set_base = radeon_crtc_set_base,
1112     .mode_set_base_atomic = radeon_crtc_set_base_atomic,
1113     .prepare = radeon_crtc_prepare,
1114     .commit = radeon_crtc_commit,
1115     .disable = radeon_crtc_disable,
1116     .get_scanout_position = radeon_get_crtc_scanout_position,
1117 };
1118 
1119 
1120 void radeon_legacy_init_crtc(struct drm_device *dev,
1121                    struct radeon_crtc *radeon_crtc)
1122 {
1123     if (radeon_crtc->crtc_id == 1)
1124         radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1125     drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1126 }
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