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0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  * Copyright 2009 Jerome Glisse.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors: Dave Airlie
0025  *          Alex Deucher
0026  *          Jerome Glisse
0027  */
0028 
0029 #include <linux/pci.h>
0030 #include <linux/pm_runtime.h>
0031 #include <linux/slab.h>
0032 #include <linux/uaccess.h>
0033 #include <linux/vga_switcheroo.h>
0034 
0035 #include <drm/drm_fb_helper.h>
0036 #include <drm/drm_file.h>
0037 #include <drm/drm_ioctl.h>
0038 #include <drm/radeon_drm.h>
0039 
0040 #include "radeon.h"
0041 #include "radeon_asic.h"
0042 #include "radeon_drv.h"
0043 #include "radeon_kms.h"
0044 
0045 #if defined(CONFIG_VGA_SWITCHEROO)
0046 bool radeon_has_atpx(void);
0047 #else
0048 static inline bool radeon_has_atpx(void) { return false; }
0049 #endif
0050 
0051 /**
0052  * radeon_driver_unload_kms - Main unload function for KMS.
0053  *
0054  * @dev: drm dev pointer
0055  *
0056  * This is the main unload function for KMS (all asics).
0057  * It calls radeon_modeset_fini() to tear down the
0058  * displays, and radeon_device_fini() to tear down
0059  * the rest of the device (CP, writeback, etc.).
0060  * Returns 0 on success.
0061  */
0062 void radeon_driver_unload_kms(struct drm_device *dev)
0063 {
0064     struct radeon_device *rdev = dev->dev_private;
0065 
0066     if (rdev == NULL)
0067         return;
0068 
0069     if (rdev->rmmio == NULL)
0070         goto done_free;
0071 
0072     if (radeon_is_px(dev)) {
0073         pm_runtime_get_sync(dev->dev);
0074         pm_runtime_forbid(dev->dev);
0075     }
0076 
0077     radeon_acpi_fini(rdev);
0078 
0079     radeon_modeset_fini(rdev);
0080     radeon_device_fini(rdev);
0081 
0082     if (rdev->agp)
0083         arch_phys_wc_del(rdev->agp->agp_mtrr);
0084     kfree(rdev->agp);
0085     rdev->agp = NULL;
0086 
0087 done_free:
0088     kfree(rdev);
0089     dev->dev_private = NULL;
0090 }
0091 
0092 /**
0093  * radeon_driver_load_kms - Main load function for KMS.
0094  *
0095  * @dev: drm dev pointer
0096  * @flags: device flags
0097  *
0098  * This is the main load function for KMS (all asics).
0099  * It calls radeon_device_init() to set up the non-display
0100  * parts of the chip (asic init, CP, writeback, etc.), and
0101  * radeon_modeset_init() to set up the display parts
0102  * (crtcs, encoders, hotplug detect, etc.).
0103  * Returns 0 on success, error on failure.
0104  */
0105 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
0106 {
0107     struct pci_dev *pdev = to_pci_dev(dev->dev);
0108     struct radeon_device *rdev;
0109     int r, acpi_status;
0110 
0111     rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
0112     if (rdev == NULL) {
0113         return -ENOMEM;
0114     }
0115     dev->dev_private = (void *)rdev;
0116 
0117 #ifdef __alpha__
0118     rdev->hose = pdev->sysdata;
0119 #endif
0120 
0121     if (pci_find_capability(pdev, PCI_CAP_ID_AGP))
0122         rdev->agp = radeon_agp_head_init(dev);
0123     if (rdev->agp) {
0124         rdev->agp->agp_mtrr = arch_phys_wc_add(
0125             rdev->agp->agp_info.aper_base,
0126             rdev->agp->agp_info.aper_size *
0127             1024 * 1024);
0128     }
0129 
0130     /* update BUS flag */
0131     if (pci_find_capability(pdev, PCI_CAP_ID_AGP)) {
0132         flags |= RADEON_IS_AGP;
0133     } else if (pci_is_pcie(pdev)) {
0134         flags |= RADEON_IS_PCIE;
0135     } else {
0136         flags |= RADEON_IS_PCI;
0137     }
0138 
0139     if ((radeon_runtime_pm != 0) &&
0140         radeon_has_atpx() &&
0141         ((flags & RADEON_IS_IGP) == 0) &&
0142         !pci_is_thunderbolt_attached(pdev))
0143         flags |= RADEON_IS_PX;
0144 
0145     /* radeon_device_init should report only fatal error
0146      * like memory allocation failure or iomapping failure,
0147      * or memory manager initialization failure, it must
0148      * properly initialize the GPU MC controller and permit
0149      * VRAM allocation
0150      */
0151     r = radeon_device_init(rdev, dev, pdev, flags);
0152     if (r) {
0153         dev_err(dev->dev, "Fatal error during GPU init\n");
0154         goto out;
0155     }
0156 
0157     /* Again modeset_init should fail only on fatal error
0158      * otherwise it should provide enough functionalities
0159      * for shadowfb to run
0160      */
0161     r = radeon_modeset_init(rdev);
0162     if (r)
0163         dev_err(dev->dev, "Fatal error during modeset init\n");
0164 
0165     /* Call ACPI methods: require modeset init
0166      * but failure is not fatal
0167      */
0168     if (!r) {
0169         acpi_status = radeon_acpi_init(rdev);
0170         if (acpi_status)
0171             dev_dbg(dev->dev, "Error during ACPI methods call\n");
0172     }
0173 
0174     if (radeon_is_px(dev)) {
0175         dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
0176         pm_runtime_use_autosuspend(dev->dev);
0177         pm_runtime_set_autosuspend_delay(dev->dev, 5000);
0178         pm_runtime_set_active(dev->dev);
0179         pm_runtime_allow(dev->dev);
0180         pm_runtime_mark_last_busy(dev->dev);
0181         pm_runtime_put_autosuspend(dev->dev);
0182     }
0183 
0184 out:
0185     if (r)
0186         radeon_driver_unload_kms(dev);
0187 
0188 
0189     return r;
0190 }
0191 
0192 /**
0193  * radeon_set_filp_rights - Set filp right.
0194  *
0195  * @dev: drm dev pointer
0196  * @owner: drm file
0197  * @applier: drm file
0198  * @value: value
0199  *
0200  * Sets the filp rights for the device (all asics).
0201  */
0202 static void radeon_set_filp_rights(struct drm_device *dev,
0203                    struct drm_file **owner,
0204                    struct drm_file *applier,
0205                    uint32_t *value)
0206 {
0207     struct radeon_device *rdev = dev->dev_private;
0208 
0209     mutex_lock(&rdev->gem.mutex);
0210     if (*value == 1) {
0211         /* wants rights */
0212         if (!*owner)
0213             *owner = applier;
0214     } else if (*value == 0) {
0215         /* revokes rights */
0216         if (*owner == applier)
0217             *owner = NULL;
0218     }
0219     *value = *owner == applier ? 1 : 0;
0220     mutex_unlock(&rdev->gem.mutex);
0221 }
0222 
0223 /*
0224  * Userspace get information ioctl
0225  */
0226 /**
0227  * radeon_info_ioctl - answer a device specific request.
0228  *
0229  * @dev: drm device pointer
0230  * @data: request object
0231  * @filp: drm filp
0232  *
0233  * This function is used to pass device specific parameters to the userspace
0234  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
0235  * etc. (all asics).
0236  * Returns 0 on success, -EINVAL on failure.
0237  */
0238 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
0239 {
0240     struct radeon_device *rdev = dev->dev_private;
0241     struct drm_radeon_info *info = data;
0242     struct radeon_mode_info *minfo = &rdev->mode_info;
0243     uint32_t *value, value_tmp, *value_ptr, value_size;
0244     struct ttm_resource_manager *man;
0245     uint64_t value64;
0246     struct drm_crtc *crtc;
0247     int i, found;
0248 
0249     value_ptr = (uint32_t *)((unsigned long)info->value);
0250     value = &value_tmp;
0251     value_size = sizeof(uint32_t);
0252 
0253     switch (info->request) {
0254     case RADEON_INFO_DEVICE_ID:
0255         *value = to_pci_dev(dev->dev)->device;
0256         break;
0257     case RADEON_INFO_NUM_GB_PIPES:
0258         *value = rdev->num_gb_pipes;
0259         break;
0260     case RADEON_INFO_NUM_Z_PIPES:
0261         *value = rdev->num_z_pipes;
0262         break;
0263     case RADEON_INFO_ACCEL_WORKING:
0264         /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
0265         if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
0266             *value = false;
0267         else
0268             *value = rdev->accel_working;
0269         break;
0270     case RADEON_INFO_CRTC_FROM_ID:
0271         if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
0272             DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
0273             return -EFAULT;
0274         }
0275         for (i = 0, found = 0; i < rdev->num_crtc; i++) {
0276             crtc = (struct drm_crtc *)minfo->crtcs[i];
0277             if (crtc && crtc->base.id == *value) {
0278                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
0279                 *value = radeon_crtc->crtc_id;
0280                 found = 1;
0281                 break;
0282             }
0283         }
0284         if (!found) {
0285             DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
0286             return -EINVAL;
0287         }
0288         break;
0289     case RADEON_INFO_ACCEL_WORKING2:
0290         if (rdev->family == CHIP_HAWAII) {
0291             if (rdev->accel_working) {
0292                 if (rdev->new_fw)
0293                     *value = 3;
0294                 else
0295                     *value = 2;
0296             } else {
0297                 *value = 0;
0298             }
0299         } else {
0300             *value = rdev->accel_working;
0301         }
0302         break;
0303     case RADEON_INFO_TILING_CONFIG:
0304         if (rdev->family >= CHIP_BONAIRE)
0305             *value = rdev->config.cik.tile_config;
0306         else if (rdev->family >= CHIP_TAHITI)
0307             *value = rdev->config.si.tile_config;
0308         else if (rdev->family >= CHIP_CAYMAN)
0309             *value = rdev->config.cayman.tile_config;
0310         else if (rdev->family >= CHIP_CEDAR)
0311             *value = rdev->config.evergreen.tile_config;
0312         else if (rdev->family >= CHIP_RV770)
0313             *value = rdev->config.rv770.tile_config;
0314         else if (rdev->family >= CHIP_R600)
0315             *value = rdev->config.r600.tile_config;
0316         else {
0317             DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
0318             return -EINVAL;
0319         }
0320         break;
0321     case RADEON_INFO_WANT_HYPERZ:
0322         /* The "value" here is both an input and output parameter.
0323          * If the input value is 1, filp requests hyper-z access.
0324          * If the input value is 0, filp revokes its hyper-z access.
0325          *
0326          * When returning, the value is 1 if filp owns hyper-z access,
0327          * 0 otherwise. */
0328         if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
0329             DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
0330             return -EFAULT;
0331         }
0332         if (*value >= 2) {
0333             DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
0334             return -EINVAL;
0335         }
0336         radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
0337         break;
0338     case RADEON_INFO_WANT_CMASK:
0339         /* The same logic as Hyper-Z. */
0340         if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
0341             DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
0342             return -EFAULT;
0343         }
0344         if (*value >= 2) {
0345             DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
0346             return -EINVAL;
0347         }
0348         radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
0349         break;
0350     case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
0351         /* return clock value in KHz */
0352         if (rdev->asic->get_xclk)
0353             *value = radeon_get_xclk(rdev) * 10;
0354         else
0355             *value = rdev->clock.spll.reference_freq * 10;
0356         break;
0357     case RADEON_INFO_NUM_BACKENDS:
0358         if (rdev->family >= CHIP_BONAIRE)
0359             *value = rdev->config.cik.max_backends_per_se *
0360                 rdev->config.cik.max_shader_engines;
0361         else if (rdev->family >= CHIP_TAHITI)
0362             *value = rdev->config.si.max_backends_per_se *
0363                 rdev->config.si.max_shader_engines;
0364         else if (rdev->family >= CHIP_CAYMAN)
0365             *value = rdev->config.cayman.max_backends_per_se *
0366                 rdev->config.cayman.max_shader_engines;
0367         else if (rdev->family >= CHIP_CEDAR)
0368             *value = rdev->config.evergreen.max_backends;
0369         else if (rdev->family >= CHIP_RV770)
0370             *value = rdev->config.rv770.max_backends;
0371         else if (rdev->family >= CHIP_R600)
0372             *value = rdev->config.r600.max_backends;
0373         else {
0374             return -EINVAL;
0375         }
0376         break;
0377     case RADEON_INFO_NUM_TILE_PIPES:
0378         if (rdev->family >= CHIP_BONAIRE)
0379             *value = rdev->config.cik.max_tile_pipes;
0380         else if (rdev->family >= CHIP_TAHITI)
0381             *value = rdev->config.si.max_tile_pipes;
0382         else if (rdev->family >= CHIP_CAYMAN)
0383             *value = rdev->config.cayman.max_tile_pipes;
0384         else if (rdev->family >= CHIP_CEDAR)
0385             *value = rdev->config.evergreen.max_tile_pipes;
0386         else if (rdev->family >= CHIP_RV770)
0387             *value = rdev->config.rv770.max_tile_pipes;
0388         else if (rdev->family >= CHIP_R600)
0389             *value = rdev->config.r600.max_tile_pipes;
0390         else {
0391             return -EINVAL;
0392         }
0393         break;
0394     case RADEON_INFO_FUSION_GART_WORKING:
0395         *value = 1;
0396         break;
0397     case RADEON_INFO_BACKEND_MAP:
0398         if (rdev->family >= CHIP_BONAIRE)
0399             *value = rdev->config.cik.backend_map;
0400         else if (rdev->family >= CHIP_TAHITI)
0401             *value = rdev->config.si.backend_map;
0402         else if (rdev->family >= CHIP_CAYMAN)
0403             *value = rdev->config.cayman.backend_map;
0404         else if (rdev->family >= CHIP_CEDAR)
0405             *value = rdev->config.evergreen.backend_map;
0406         else if (rdev->family >= CHIP_RV770)
0407             *value = rdev->config.rv770.backend_map;
0408         else if (rdev->family >= CHIP_R600)
0409             *value = rdev->config.r600.backend_map;
0410         else {
0411             return -EINVAL;
0412         }
0413         break;
0414     case RADEON_INFO_VA_START:
0415         /* this is where we report if vm is supported or not */
0416         if (rdev->family < CHIP_CAYMAN)
0417             return -EINVAL;
0418         *value = RADEON_VA_RESERVED_SIZE;
0419         break;
0420     case RADEON_INFO_IB_VM_MAX_SIZE:
0421         /* this is where we report if vm is supported or not */
0422         if (rdev->family < CHIP_CAYMAN)
0423             return -EINVAL;
0424         *value = RADEON_IB_VM_MAX_SIZE;
0425         break;
0426     case RADEON_INFO_MAX_PIPES:
0427         if (rdev->family >= CHIP_BONAIRE)
0428             *value = rdev->config.cik.max_cu_per_sh;
0429         else if (rdev->family >= CHIP_TAHITI)
0430             *value = rdev->config.si.max_cu_per_sh;
0431         else if (rdev->family >= CHIP_CAYMAN)
0432             *value = rdev->config.cayman.max_pipes_per_simd;
0433         else if (rdev->family >= CHIP_CEDAR)
0434             *value = rdev->config.evergreen.max_pipes;
0435         else if (rdev->family >= CHIP_RV770)
0436             *value = rdev->config.rv770.max_pipes;
0437         else if (rdev->family >= CHIP_R600)
0438             *value = rdev->config.r600.max_pipes;
0439         else {
0440             return -EINVAL;
0441         }
0442         break;
0443     case RADEON_INFO_TIMESTAMP:
0444         if (rdev->family < CHIP_R600) {
0445             DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
0446             return -EINVAL;
0447         }
0448         value = (uint32_t*)&value64;
0449         value_size = sizeof(uint64_t);
0450         value64 = radeon_get_gpu_clock_counter(rdev);
0451         break;
0452     case RADEON_INFO_MAX_SE:
0453         if (rdev->family >= CHIP_BONAIRE)
0454             *value = rdev->config.cik.max_shader_engines;
0455         else if (rdev->family >= CHIP_TAHITI)
0456             *value = rdev->config.si.max_shader_engines;
0457         else if (rdev->family >= CHIP_CAYMAN)
0458             *value = rdev->config.cayman.max_shader_engines;
0459         else if (rdev->family >= CHIP_CEDAR)
0460             *value = rdev->config.evergreen.num_ses;
0461         else
0462             *value = 1;
0463         break;
0464     case RADEON_INFO_MAX_SH_PER_SE:
0465         if (rdev->family >= CHIP_BONAIRE)
0466             *value = rdev->config.cik.max_sh_per_se;
0467         else if (rdev->family >= CHIP_TAHITI)
0468             *value = rdev->config.si.max_sh_per_se;
0469         else
0470             return -EINVAL;
0471         break;
0472     case RADEON_INFO_FASTFB_WORKING:
0473         *value = rdev->fastfb_working;
0474         break;
0475     case RADEON_INFO_RING_WORKING:
0476         if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
0477             DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
0478             return -EFAULT;
0479         }
0480         switch (*value) {
0481         case RADEON_CS_RING_GFX:
0482         case RADEON_CS_RING_COMPUTE:
0483             *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
0484             break;
0485         case RADEON_CS_RING_DMA:
0486             *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
0487             *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
0488             break;
0489         case RADEON_CS_RING_UVD:
0490             *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
0491             break;
0492         case RADEON_CS_RING_VCE:
0493             *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
0494             break;
0495         default:
0496             return -EINVAL;
0497         }
0498         break;
0499     case RADEON_INFO_SI_TILE_MODE_ARRAY:
0500         if (rdev->family >= CHIP_BONAIRE) {
0501             value = rdev->config.cik.tile_mode_array;
0502             value_size = sizeof(uint32_t)*32;
0503         } else if (rdev->family >= CHIP_TAHITI) {
0504             value = rdev->config.si.tile_mode_array;
0505             value_size = sizeof(uint32_t)*32;
0506         } else {
0507             DRM_DEBUG_KMS("tile mode array is si+ only!\n");
0508             return -EINVAL;
0509         }
0510         break;
0511     case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
0512         if (rdev->family >= CHIP_BONAIRE) {
0513             value = rdev->config.cik.macrotile_mode_array;
0514             value_size = sizeof(uint32_t)*16;
0515         } else {
0516             DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
0517             return -EINVAL;
0518         }
0519         break;
0520     case RADEON_INFO_SI_CP_DMA_COMPUTE:
0521         *value = 1;
0522         break;
0523     case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
0524         if (rdev->family >= CHIP_BONAIRE) {
0525             *value = rdev->config.cik.backend_enable_mask;
0526         } else if (rdev->family >= CHIP_TAHITI) {
0527             *value = rdev->config.si.backend_enable_mask;
0528         } else {
0529             DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
0530             return -EINVAL;
0531         }
0532         break;
0533     case RADEON_INFO_MAX_SCLK:
0534         if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
0535             rdev->pm.dpm_enabled)
0536             *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
0537         else
0538             *value = rdev->pm.default_sclk * 10;
0539         break;
0540     case RADEON_INFO_VCE_FW_VERSION:
0541         *value = rdev->vce.fw_version;
0542         break;
0543     case RADEON_INFO_VCE_FB_VERSION:
0544         *value = rdev->vce.fb_version;
0545         break;
0546     case RADEON_INFO_NUM_BYTES_MOVED:
0547         value = (uint32_t*)&value64;
0548         value_size = sizeof(uint64_t);
0549         value64 = atomic64_read(&rdev->num_bytes_moved);
0550         break;
0551     case RADEON_INFO_VRAM_USAGE:
0552         value = (uint32_t*)&value64;
0553         value_size = sizeof(uint64_t);
0554         man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM);
0555         value64 = ttm_resource_manager_usage(man);
0556         break;
0557     case RADEON_INFO_GTT_USAGE:
0558         value = (uint32_t*)&value64;
0559         value_size = sizeof(uint64_t);
0560         man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_TT);
0561         value64 = ttm_resource_manager_usage(man);
0562         break;
0563     case RADEON_INFO_ACTIVE_CU_COUNT:
0564         if (rdev->family >= CHIP_BONAIRE)
0565             *value = rdev->config.cik.active_cus;
0566         else if (rdev->family >= CHIP_TAHITI)
0567             *value = rdev->config.si.active_cus;
0568         else if (rdev->family >= CHIP_CAYMAN)
0569             *value = rdev->config.cayman.active_simds;
0570         else if (rdev->family >= CHIP_CEDAR)
0571             *value = rdev->config.evergreen.active_simds;
0572         else if (rdev->family >= CHIP_RV770)
0573             *value = rdev->config.rv770.active_simds;
0574         else if (rdev->family >= CHIP_R600)
0575             *value = rdev->config.r600.active_simds;
0576         else
0577             *value = 1;
0578         break;
0579     case RADEON_INFO_CURRENT_GPU_TEMP:
0580         /* get temperature in millidegrees C */
0581         if (rdev->asic->pm.get_temperature)
0582             *value = radeon_get_temperature(rdev);
0583         else
0584             *value = 0;
0585         break;
0586     case RADEON_INFO_CURRENT_GPU_SCLK:
0587         /* get sclk in Mhz */
0588         if (rdev->pm.dpm_enabled)
0589             *value = radeon_dpm_get_current_sclk(rdev) / 100;
0590         else
0591             *value = rdev->pm.current_sclk / 100;
0592         break;
0593     case RADEON_INFO_CURRENT_GPU_MCLK:
0594         /* get mclk in Mhz */
0595         if (rdev->pm.dpm_enabled)
0596             *value = radeon_dpm_get_current_mclk(rdev) / 100;
0597         else
0598             *value = rdev->pm.current_mclk / 100;
0599         break;
0600     case RADEON_INFO_READ_REG:
0601         if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
0602             DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
0603             return -EFAULT;
0604         }
0605         if (radeon_get_allowed_info_register(rdev, *value, value))
0606             return -EINVAL;
0607         break;
0608     case RADEON_INFO_VA_UNMAP_WORKING:
0609         *value = true;
0610         break;
0611     case RADEON_INFO_GPU_RESET_COUNTER:
0612         *value = atomic_read(&rdev->gpu_reset_counter);
0613         break;
0614     default:
0615         DRM_DEBUG_KMS("Invalid request %d\n", info->request);
0616         return -EINVAL;
0617     }
0618     if (copy_to_user(value_ptr, (char*)value, value_size)) {
0619         DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
0620         return -EFAULT;
0621     }
0622     return 0;
0623 }
0624 
0625 
0626 /*
0627  * Outdated mess for old drm with Xorg being in charge (void function now).
0628  */
0629 /**
0630  * radeon_driver_lastclose_kms - drm callback for last close
0631  *
0632  * @dev: drm dev pointer
0633  *
0634  * Switch vga_switcheroo state after last close (all asics).
0635  */
0636 void radeon_driver_lastclose_kms(struct drm_device *dev)
0637 {
0638     drm_fb_helper_lastclose(dev);
0639     vga_switcheroo_process_delayed_switch();
0640 }
0641 
0642 /**
0643  * radeon_driver_open_kms - drm callback for open
0644  *
0645  * @dev: drm dev pointer
0646  * @file_priv: drm file
0647  *
0648  * On device open, init vm on cayman+ (all asics).
0649  * Returns 0 on success, error on failure.
0650  */
0651 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
0652 {
0653     struct radeon_device *rdev = dev->dev_private;
0654     struct radeon_fpriv *fpriv;
0655     struct radeon_vm *vm;
0656     int r;
0657 
0658     file_priv->driver_priv = NULL;
0659 
0660     r = pm_runtime_get_sync(dev->dev);
0661     if (r < 0) {
0662         pm_runtime_put_autosuspend(dev->dev);
0663         return r;
0664     }
0665 
0666     /* new gpu have virtual address space support */
0667     if (rdev->family >= CHIP_CAYMAN) {
0668 
0669         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
0670         if (unlikely(!fpriv)) {
0671             r = -ENOMEM;
0672             goto err_suspend;
0673         }
0674 
0675         if (rdev->accel_working) {
0676             vm = &fpriv->vm;
0677             r = radeon_vm_init(rdev, vm);
0678             if (r)
0679                 goto err_fpriv;
0680 
0681             r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
0682             if (r)
0683                 goto err_vm_fini;
0684 
0685             /* map the ib pool buffer read only into
0686              * virtual address space */
0687             vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
0688                             rdev->ring_tmp_bo.bo);
0689             if (!vm->ib_bo_va) {
0690                 r = -ENOMEM;
0691                 goto err_vm_fini;
0692             }
0693 
0694             r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
0695                           RADEON_VA_IB_OFFSET,
0696                           RADEON_VM_PAGE_READABLE |
0697                           RADEON_VM_PAGE_SNOOPED);
0698             if (r)
0699                 goto err_vm_fini;
0700         }
0701         file_priv->driver_priv = fpriv;
0702     }
0703 
0704     pm_runtime_mark_last_busy(dev->dev);
0705     pm_runtime_put_autosuspend(dev->dev);
0706     return 0;
0707 
0708 err_vm_fini:
0709     radeon_vm_fini(rdev, vm);
0710 err_fpriv:
0711     kfree(fpriv);
0712 
0713 err_suspend:
0714     pm_runtime_mark_last_busy(dev->dev);
0715     pm_runtime_put_autosuspend(dev->dev);
0716     return r;
0717 }
0718 
0719 /**
0720  * radeon_driver_postclose_kms - drm callback for post close
0721  *
0722  * @dev: drm dev pointer
0723  * @file_priv: drm file
0724  *
0725  * On device close, tear down hyperz and cmask filps on r1xx-r5xx
0726  * (all asics).  And tear down vm on cayman+ (all asics).
0727  */
0728 void radeon_driver_postclose_kms(struct drm_device *dev,
0729                  struct drm_file *file_priv)
0730 {
0731     struct radeon_device *rdev = dev->dev_private;
0732 
0733     pm_runtime_get_sync(dev->dev);
0734 
0735     mutex_lock(&rdev->gem.mutex);
0736     if (rdev->hyperz_filp == file_priv)
0737         rdev->hyperz_filp = NULL;
0738     if (rdev->cmask_filp == file_priv)
0739         rdev->cmask_filp = NULL;
0740     mutex_unlock(&rdev->gem.mutex);
0741 
0742     radeon_uvd_free_handles(rdev, file_priv);
0743     radeon_vce_free_handles(rdev, file_priv);
0744 
0745     /* new gpu have virtual address space support */
0746     if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
0747         struct radeon_fpriv *fpriv = file_priv->driver_priv;
0748         struct radeon_vm *vm = &fpriv->vm;
0749         int r;
0750 
0751         if (rdev->accel_working) {
0752             r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
0753             if (!r) {
0754                 if (vm->ib_bo_va)
0755                     radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
0756                 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
0757             }
0758             radeon_vm_fini(rdev, vm);
0759         }
0760 
0761         kfree(fpriv);
0762         file_priv->driver_priv = NULL;
0763     }
0764     pm_runtime_mark_last_busy(dev->dev);
0765     pm_runtime_put_autosuspend(dev->dev);
0766 }
0767 
0768 /*
0769  * VBlank related functions.
0770  */
0771 /**
0772  * radeon_get_vblank_counter_kms - get frame count
0773  *
0774  * @crtc: crtc to get the frame count from
0775  *
0776  * Gets the frame count on the requested crtc (all asics).
0777  * Returns frame count on success, -EINVAL on failure.
0778  */
0779 u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc)
0780 {
0781     struct drm_device *dev = crtc->dev;
0782     unsigned int pipe = crtc->index;
0783     int vpos, hpos, stat;
0784     u32 count;
0785     struct radeon_device *rdev = dev->dev_private;
0786 
0787     if (pipe >= rdev->num_crtc) {
0788         DRM_ERROR("Invalid crtc %u\n", pipe);
0789         return -EINVAL;
0790     }
0791 
0792     /* The hw increments its frame counter at start of vsync, not at start
0793      * of vblank, as is required by DRM core vblank counter handling.
0794      * Cook the hw count here to make it appear to the caller as if it
0795      * incremented at start of vblank. We measure distance to start of
0796      * vblank in vpos. vpos therefore will be >= 0 between start of vblank
0797      * and start of vsync, so vpos >= 0 means to bump the hw frame counter
0798      * result by 1 to give the proper appearance to caller.
0799      */
0800     if (rdev->mode_info.crtcs[pipe]) {
0801         /* Repeat readout if needed to provide stable result if
0802          * we cross start of vsync during the queries.
0803          */
0804         do {
0805             count = radeon_get_vblank_counter(rdev, pipe);
0806             /* Ask radeon_get_crtc_scanoutpos to return vpos as
0807              * distance to start of vblank, instead of regular
0808              * vertical scanout pos.
0809              */
0810             stat = radeon_get_crtc_scanoutpos(
0811                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
0812                 &vpos, &hpos, NULL, NULL,
0813                 &rdev->mode_info.crtcs[pipe]->base.hwmode);
0814         } while (count != radeon_get_vblank_counter(rdev, pipe));
0815 
0816         if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
0817             (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
0818             DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
0819         }
0820         else {
0821             DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n",
0822                       pipe, vpos);
0823 
0824             /* Bump counter if we are at >= leading edge of vblank,
0825              * but before vsync where vpos would turn negative and
0826              * the hw counter really increments.
0827              */
0828             if (vpos >= 0)
0829                 count++;
0830         }
0831     }
0832     else {
0833         /* Fallback to use value as is. */
0834         count = radeon_get_vblank_counter(rdev, pipe);
0835         DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
0836     }
0837 
0838     return count;
0839 }
0840 
0841 /**
0842  * radeon_enable_vblank_kms - enable vblank interrupt
0843  *
0844  * @crtc: crtc to enable vblank interrupt for
0845  *
0846  * Enable the interrupt on the requested crtc (all asics).
0847  * Returns 0 on success, -EINVAL on failure.
0848  */
0849 int radeon_enable_vblank_kms(struct drm_crtc *crtc)
0850 {
0851     struct drm_device *dev = crtc->dev;
0852     unsigned int pipe = crtc->index;
0853     struct radeon_device *rdev = dev->dev_private;
0854     unsigned long irqflags;
0855     int r;
0856 
0857     if (pipe >= rdev->num_crtc) {
0858         DRM_ERROR("Invalid crtc %d\n", pipe);
0859         return -EINVAL;
0860     }
0861 
0862     spin_lock_irqsave(&rdev->irq.lock, irqflags);
0863     rdev->irq.crtc_vblank_int[pipe] = true;
0864     r = radeon_irq_set(rdev);
0865     spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
0866     return r;
0867 }
0868 
0869 /**
0870  * radeon_disable_vblank_kms - disable vblank interrupt
0871  *
0872  * @crtc: crtc to disable vblank interrupt for
0873  *
0874  * Disable the interrupt on the requested crtc (all asics).
0875  */
0876 void radeon_disable_vblank_kms(struct drm_crtc *crtc)
0877 {
0878     struct drm_device *dev = crtc->dev;
0879     unsigned int pipe = crtc->index;
0880     struct radeon_device *rdev = dev->dev_private;
0881     unsigned long irqflags;
0882 
0883     if (pipe >= rdev->num_crtc) {
0884         DRM_ERROR("Invalid crtc %d\n", pipe);
0885         return;
0886     }
0887 
0888     spin_lock_irqsave(&rdev->irq.lock, irqflags);
0889     rdev->irq.crtc_vblank_int[pipe] = false;
0890     radeon_irq_set(rdev);
0891     spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
0892 }
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