drm/radeon/radeon_ib.c

0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  * Copyright 2009 Jerome Glisse.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors: Dave Airlie
0025  *          Alex Deucher
0026  *          Jerome Glisse
0027  *          Christian König
0028  */
0029
0030 #include <drm/drm_file.h>
0031
0032 #include "radeon.h"
0033
0034 /*
0035  * IB
0036  * IBs (Indirect Buffers) and areas of GPU accessible memory where
0037  * commands are stored.  You can put a pointer to the IB in the
0038  * command ring and the hw will fetch the commands from the IB
0039  * and execute them.  Generally userspace acceleration drivers
0040  * produce command buffers which are send to the kernel and
0041  * put in IBs for execution by the requested ring.
0042  */
0043 static void radeon_debugfs_sa_init(struct radeon_device *rdev);
0044
0045 /**
0046  * radeon_ib_get - request an IB (Indirect Buffer)
0047  *
0048  * @rdev: radeon_device pointer
0049  * @ring: ring index the IB is associated with
0050  * @vm: requested vm
0051  * @ib: IB object returned
0052  * @size: requested IB size
0053  *
0054  * Request an IB (all asics).  IBs are allocated using the
0055  * suballocator.
0056  * Returns 0 on success, error on failure.
0057  */
0058 int radeon_ib_get(struct radeon_device *rdev, int ring,
0059           struct radeon_ib *ib, struct radeon_vm *vm,
0060           unsigned size)
0061 {
0062     int r;
0063
0064     r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256);
0065     if (r) {
0066         dev_err(rdev->dev, "failed to get a new IB (%d)\n", r);
0067         return r;
0068     }
0069
0070     radeon_sync_create(&ib->sync);
0071
0072     ib->ring = ring;
0073     ib->fence = NULL;
0074     ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);
0075     ib->vm = vm;
0076     if (vm) {
0077         /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address
0078          * space and soffset is the offset inside the pool bo
0079          */
0080         ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET;
0081     } else {
0082         ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
0083     }
0084     ib->is_const_ib = false;
0085
0086     return 0;
0087 }
0088
0089 /**
0090  * radeon_ib_free - free an IB (Indirect Buffer)
0091  *
0092  * @rdev: radeon_device pointer
0093  * @ib: IB object to free
0094  *
0095  * Free an IB (all asics).
0096  */
0097 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
0098 {
0099     radeon_sync_free(rdev, &ib->sync, ib->fence);
0100     radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);
0101     radeon_fence_unref(&ib->fence);
0102 }
0103
0104 /**
0105  * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
0106  *
0107  * @rdev: radeon_device pointer
0108  * @ib: IB object to schedule
0109  * @const_ib: Const IB to schedule (SI only)
0110  * @hdp_flush: Whether or not to perform an HDP cache flush
0111  *
0112  * Schedule an IB on the associated ring (all asics).
0113  * Returns 0 on success, error on failure.
0114  *
0115  * On SI, there are two parallel engines fed from the primary ring,
0116  * the CE (Constant Engine) and the DE (Drawing Engine).  Since
0117  * resource descriptors have moved to memory, the CE allows you to
0118  * prime the caches while the DE is updating register state so that
0119  * the resource descriptors will be already in cache when the draw is
0120  * processed.  To accomplish this, the userspace driver submits two
0121  * IBs, one for the CE and one for the DE.  If there is a CE IB (called
0122  * a CONST_IB), it will be put on the ring prior to the DE IB.  Prior
0123  * to SI there was just a DE IB.
0124  */
0125 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
0126                struct radeon_ib *const_ib, bool hdp_flush)
0127 {
0128     struct radeon_ring *ring = &rdev->ring[ib->ring];
0129     int r = 0;
0130
0131     if (!ib->length_dw || !ring->ready) {
0132         /* TODO: Nothings in the ib we should report. */
0133         dev_err(rdev->dev, "couldn't schedule ib\n");
0134         return -EINVAL;
0135     }
0136
0137     /* 64 dwords should be enough for fence too */
0138     r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_SYNCS * 8);
0139     if (r) {
0140         dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);
0141         return r;
0142     }
0143
0144     /* grab a vm id if necessary */
0145     if (ib->vm) {
0146         struct radeon_fence *vm_id_fence;
0147         vm_id_fence = radeon_vm_grab_id(rdev, ib->vm, ib->ring);
0148         radeon_sync_fence(&ib->sync, vm_id_fence);
0149     }
0150
0151     /* sync with other rings */
0152     r = radeon_sync_rings(rdev, &ib->sync, ib->ring);
0153     if (r) {
0154         dev_err(rdev->dev, "failed to sync rings (%d)\n", r);
0155         radeon_ring_unlock_undo(rdev, ring);
0156         return r;
0157     }
0158
0159     if (ib->vm)
0160         radeon_vm_flush(rdev, ib->vm, ib->ring,
0161                 ib->sync.last_vm_update);
0162
0163     if (const_ib) {
0164         radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);
0165         radeon_sync_free(rdev, &const_ib->sync, NULL);
0166     }
0167     radeon_ring_ib_execute(rdev, ib->ring, ib);
0168     r = radeon_fence_emit(rdev, &ib->fence, ib->ring);
0169     if (r) {
0170         dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r);
0171         radeon_ring_unlock_undo(rdev, ring);
0172         return r;
0173     }
0174     if (const_ib) {
0175         const_ib->fence = radeon_fence_ref(ib->fence);
0176     }
0177
0178     if (ib->vm)
0179         radeon_vm_fence(rdev, ib->vm, ib->fence);
0180
0181     radeon_ring_unlock_commit(rdev, ring, hdp_flush);
0182     return 0;
0183 }
0184
0185 /**
0186  * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool
0187  *
0188  * @rdev: radeon_device pointer
0189  *
0190  * Initialize the suballocator to manage a pool of memory
0191  * for use as IBs (all asics).
0192  * Returns 0 on success, error on failure.
0193  */
0194 int radeon_ib_pool_init(struct radeon_device *rdev)
0195 {
0196     int r;
0197
0198     if (rdev->ib_pool_ready) {
0199         return 0;
0200     }
0201
0202     if (rdev->family >= CHIP_BONAIRE) {
0203         r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
0204                           RADEON_IB_POOL_SIZE*64*1024,
0205                           RADEON_GPU_PAGE_SIZE,
0206                           RADEON_GEM_DOMAIN_GTT,
0207                           RADEON_GEM_GTT_WC);
0208     } else {
0209         /* Before CIK, it's better to stick to cacheable GTT due
0210          * to the command stream checking
0211          */
0212         r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
0213                           RADEON_IB_POOL_SIZE*64*1024,
0214                           RADEON_GPU_PAGE_SIZE,
0215                           RADEON_GEM_DOMAIN_GTT, 0);
0216     }
0217     if (r) {
0218         return r;
0219     }
0220
0221     r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo);
0222     if (r) {
0223         return r;
0224     }
0225
0226     rdev->ib_pool_ready = true;
0227     radeon_debugfs_sa_init(rdev);
0228     return 0;
0229 }
0230
0231 /**
0232  * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool
0233  *
0234  * @rdev: radeon_device pointer
0235  *
0236  * Tear down the suballocator managing the pool of memory
0237  * for use as IBs (all asics).
0238  */
0239 void radeon_ib_pool_fini(struct radeon_device *rdev)
0240 {
0241     if (rdev->ib_pool_ready) {
0242         radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo);
0243         radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo);
0244         rdev->ib_pool_ready = false;
0245     }
0246 }
0247
0248 /**
0249  * radeon_ib_ring_tests - test IBs on the rings
0250  *
0251  * @rdev: radeon_device pointer
0252  *
0253  * Test an IB (Indirect Buffer) on each ring.
0254  * If the test fails, disable the ring.
0255  * Returns 0 on success, error if the primary GFX ring
0256  * IB test fails.
0257  */
0258 int radeon_ib_ring_tests(struct radeon_device *rdev)
0259 {
0260     unsigned i;
0261     int r;
0262
0263     for (i = 0; i < RADEON_NUM_RINGS; ++i) {
0264         struct radeon_ring *ring = &rdev->ring[i];
0265
0266         if (!ring->ready)
0267             continue;
0268
0269         r = radeon_ib_test(rdev, i, ring);
0270         if (r) {
0271             radeon_fence_driver_force_completion(rdev, i);
0272             ring->ready = false;
0273             rdev->needs_reset = false;
0274
0275             if (i == RADEON_RING_TYPE_GFX_INDEX) {
0276                 /* oh, oh, that's really bad */
0277                 DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r);
0278                 rdev->accel_working = false;
0279                 return r;
0280
0281             } else {
0282                 /* still not good, but we can live with it */
0283                 DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);
0284             }
0285         }
0286     }
0287     return 0;
0288 }
0289
0290 /*
0291  * Debugfs info
0292  */
0293 #if defined(CONFIG_DEBUG_FS)
0294
0295 static int radeon_debugfs_sa_info_show(struct seq_file *m, void *unused)
0296 {
0297     struct radeon_device *rdev = (struct radeon_device *)m->private;
0298
0299     radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);
0300
0301     return 0;
0302
0303 }
0304
0305 DEFINE_SHOW_ATTRIBUTE(radeon_debugfs_sa_info);
0306
0307 #endif
0308
0309 static void radeon_debugfs_sa_init(struct radeon_device *rdev)
0310 {
0311 #if defined(CONFIG_DEBUG_FS)
0312     struct dentry *root = rdev->ddev->primary->debugfs_root;
0313
0314     debugfs_create_file("radeon_sa_info", 0444, root, rdev,
0315                 &radeon_debugfs_sa_info_fops);
0316 #endif
0317 }