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0001 /*
0002  * Copyright 2007-8 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors: Dave Airlie
0024  *          Alex Deucher
0025  */
0026 
0027 #include <linux/export.h>
0028 #include <linux/pci.h>
0029 
0030 #include <drm/drm_device.h>
0031 #include <drm/drm_edid.h>
0032 #include <drm/radeon_drm.h>
0033 
0034 #include "radeon.h"
0035 #include "atom.h"
0036 
0037 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux)
0038 {
0039     u8 out = 0x0;
0040     u8 buf[8];
0041     int ret;
0042     struct i2c_msg msgs[] = {
0043         {
0044             .addr = DDC_ADDR,
0045             .flags = 0,
0046             .len = 1,
0047             .buf = &out,
0048         },
0049         {
0050             .addr = DDC_ADDR,
0051             .flags = I2C_M_RD,
0052             .len = 8,
0053             .buf = buf,
0054         }
0055     };
0056 
0057     /* on hw with routers, select right port */
0058     if (radeon_connector->router.ddc_valid)
0059         radeon_router_select_ddc_port(radeon_connector);
0060 
0061     if (use_aux) {
0062         ret = i2c_transfer(&radeon_connector->ddc_bus->aux.ddc, msgs, 2);
0063     } else {
0064         ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
0065     }
0066 
0067     if (ret != 2)
0068         /* Couldn't find an accessible DDC on this connector */
0069         return false;
0070     /* Probe also for valid EDID header
0071      * EDID header starts with:
0072      * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
0073      * Only the first 6 bytes must be valid as
0074      * drm_edid_block_valid() can fix the last 2 bytes */
0075     if (drm_edid_header_is_valid(buf) < 6) {
0076         /* Couldn't find an accessible EDID on this
0077          * connector */
0078         return false;
0079     }
0080     return true;
0081 }
0082 
0083 /* bit banging i2c */
0084 
0085 static int pre_xfer(struct i2c_adapter *i2c_adap)
0086 {
0087     struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
0088     struct radeon_device *rdev = i2c->dev->dev_private;
0089     struct radeon_i2c_bus_rec *rec = &i2c->rec;
0090     uint32_t temp;
0091 
0092     mutex_lock(&i2c->mutex);
0093 
0094     /* RV410 appears to have a bug where the hw i2c in reset
0095      * holds the i2c port in a bad state - switch hw i2c away before
0096      * doing DDC - do this for all r200s/r300s/r400s for safety sake
0097      */
0098     if (rec->hw_capable) {
0099         if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
0100             u32 reg;
0101 
0102             if (rdev->family >= CHIP_RV350)
0103                 reg = RADEON_GPIO_MONID;
0104             else if ((rdev->family == CHIP_R300) ||
0105                  (rdev->family == CHIP_R350))
0106                 reg = RADEON_GPIO_DVI_DDC;
0107             else
0108                 reg = RADEON_GPIO_CRT2_DDC;
0109 
0110             mutex_lock(&rdev->dc_hw_i2c_mutex);
0111             if (rec->a_clk_reg == reg) {
0112                 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
0113                                    R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
0114             } else {
0115                 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
0116                                    R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
0117             }
0118             mutex_unlock(&rdev->dc_hw_i2c_mutex);
0119         }
0120     }
0121 
0122     /* switch the pads to ddc mode */
0123     if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
0124         temp = RREG32(rec->mask_clk_reg);
0125         temp &= ~(1 << 16);
0126         WREG32(rec->mask_clk_reg, temp);
0127     }
0128 
0129     /* clear the output pin values */
0130     temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
0131     WREG32(rec->a_clk_reg, temp);
0132 
0133     temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
0134     WREG32(rec->a_data_reg, temp);
0135 
0136     /* set the pins to input */
0137     temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
0138     WREG32(rec->en_clk_reg, temp);
0139 
0140     temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
0141     WREG32(rec->en_data_reg, temp);
0142 
0143     /* mask the gpio pins for software use */
0144     temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
0145     WREG32(rec->mask_clk_reg, temp);
0146     temp = RREG32(rec->mask_clk_reg);
0147 
0148     temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
0149     WREG32(rec->mask_data_reg, temp);
0150     temp = RREG32(rec->mask_data_reg);
0151 
0152     return 0;
0153 }
0154 
0155 static void post_xfer(struct i2c_adapter *i2c_adap)
0156 {
0157     struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
0158     struct radeon_device *rdev = i2c->dev->dev_private;
0159     struct radeon_i2c_bus_rec *rec = &i2c->rec;
0160     uint32_t temp;
0161 
0162     /* unmask the gpio pins for software use */
0163     temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
0164     WREG32(rec->mask_clk_reg, temp);
0165     temp = RREG32(rec->mask_clk_reg);
0166 
0167     temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
0168     WREG32(rec->mask_data_reg, temp);
0169     temp = RREG32(rec->mask_data_reg);
0170 
0171     mutex_unlock(&i2c->mutex);
0172 }
0173 
0174 static int get_clock(void *i2c_priv)
0175 {
0176     struct radeon_i2c_chan *i2c = i2c_priv;
0177     struct radeon_device *rdev = i2c->dev->dev_private;
0178     struct radeon_i2c_bus_rec *rec = &i2c->rec;
0179     uint32_t val;
0180 
0181     /* read the value off the pin */
0182     val = RREG32(rec->y_clk_reg);
0183     val &= rec->y_clk_mask;
0184 
0185     return (val != 0);
0186 }
0187 
0188 
0189 static int get_data(void *i2c_priv)
0190 {
0191     struct radeon_i2c_chan *i2c = i2c_priv;
0192     struct radeon_device *rdev = i2c->dev->dev_private;
0193     struct radeon_i2c_bus_rec *rec = &i2c->rec;
0194     uint32_t val;
0195 
0196     /* read the value off the pin */
0197     val = RREG32(rec->y_data_reg);
0198     val &= rec->y_data_mask;
0199 
0200     return (val != 0);
0201 }
0202 
0203 static void set_clock(void *i2c_priv, int clock)
0204 {
0205     struct radeon_i2c_chan *i2c = i2c_priv;
0206     struct radeon_device *rdev = i2c->dev->dev_private;
0207     struct radeon_i2c_bus_rec *rec = &i2c->rec;
0208     uint32_t val;
0209 
0210     /* set pin direction */
0211     val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
0212     val |= clock ? 0 : rec->en_clk_mask;
0213     WREG32(rec->en_clk_reg, val);
0214 }
0215 
0216 static void set_data(void *i2c_priv, int data)
0217 {
0218     struct radeon_i2c_chan *i2c = i2c_priv;
0219     struct radeon_device *rdev = i2c->dev->dev_private;
0220     struct radeon_i2c_bus_rec *rec = &i2c->rec;
0221     uint32_t val;
0222 
0223     /* set pin direction */
0224     val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
0225     val |= data ? 0 : rec->en_data_mask;
0226     WREG32(rec->en_data_reg, val);
0227 }
0228 
0229 /* hw i2c */
0230 
0231 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
0232 {
0233     u32 sclk = rdev->pm.current_sclk;
0234     u32 prescale = 0;
0235     u32 nm;
0236     u8 n, m, loop;
0237     int i2c_clock;
0238 
0239     switch (rdev->family) {
0240     case CHIP_R100:
0241     case CHIP_RV100:
0242     case CHIP_RS100:
0243     case CHIP_RV200:
0244     case CHIP_RS200:
0245     case CHIP_R200:
0246     case CHIP_RV250:
0247     case CHIP_RS300:
0248     case CHIP_RV280:
0249     case CHIP_R300:
0250     case CHIP_R350:
0251     case CHIP_RV350:
0252         i2c_clock = 60;
0253         nm = (sclk * 10) / (i2c_clock * 4);
0254         for (loop = 1; loop < 255; loop++) {
0255             if ((nm / loop) < loop)
0256                 break;
0257         }
0258         n = loop - 1;
0259         m = loop - 2;
0260         prescale = m | (n << 8);
0261         break;
0262     case CHIP_RV380:
0263     case CHIP_RS400:
0264     case CHIP_RS480:
0265     case CHIP_R420:
0266     case CHIP_R423:
0267     case CHIP_RV410:
0268         prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
0269         break;
0270     case CHIP_RS600:
0271     case CHIP_RS690:
0272     case CHIP_RS740:
0273         /* todo */
0274         break;
0275     case CHIP_RV515:
0276     case CHIP_R520:
0277     case CHIP_RV530:
0278     case CHIP_RV560:
0279     case CHIP_RV570:
0280     case CHIP_R580:
0281         i2c_clock = 50;
0282         if (rdev->family == CHIP_R520)
0283             prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
0284         else
0285             prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
0286         break;
0287     case CHIP_R600:
0288     case CHIP_RV610:
0289     case CHIP_RV630:
0290     case CHIP_RV670:
0291         /* todo */
0292         break;
0293     case CHIP_RV620:
0294     case CHIP_RV635:
0295     case CHIP_RS780:
0296     case CHIP_RS880:
0297     case CHIP_RV770:
0298     case CHIP_RV730:
0299     case CHIP_RV710:
0300     case CHIP_RV740:
0301         /* todo */
0302         break;
0303     case CHIP_CEDAR:
0304     case CHIP_REDWOOD:
0305     case CHIP_JUNIPER:
0306     case CHIP_CYPRESS:
0307     case CHIP_HEMLOCK:
0308         /* todo */
0309         break;
0310     default:
0311         DRM_ERROR("i2c: unhandled radeon chip\n");
0312         break;
0313     }
0314     return prescale;
0315 }
0316 
0317 
0318 /* hw i2c engine for r1xx-4xx hardware
0319  * hw can buffer up to 15 bytes
0320  */
0321 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
0322                 struct i2c_msg *msgs, int num)
0323 {
0324     struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
0325     struct radeon_device *rdev = i2c->dev->dev_private;
0326     struct radeon_i2c_bus_rec *rec = &i2c->rec;
0327     struct i2c_msg *p;
0328     int i, j, k, ret = num;
0329     u32 prescale;
0330     u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
0331     u32 tmp, reg;
0332 
0333     mutex_lock(&rdev->dc_hw_i2c_mutex);
0334     /* take the pm lock since we need a constant sclk */
0335     mutex_lock(&rdev->pm.mutex);
0336 
0337     prescale = radeon_get_i2c_prescale(rdev);
0338 
0339     reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
0340            RADEON_I2C_DRIVE_EN |
0341            RADEON_I2C_START |
0342            RADEON_I2C_STOP |
0343            RADEON_I2C_GO);
0344 
0345     if (rdev->is_atom_bios) {
0346         tmp = RREG32(RADEON_BIOS_6_SCRATCH);
0347         WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
0348     }
0349 
0350     if (rec->mm_i2c) {
0351         i2c_cntl_0 = RADEON_I2C_CNTL_0;
0352         i2c_cntl_1 = RADEON_I2C_CNTL_1;
0353         i2c_data = RADEON_I2C_DATA;
0354     } else {
0355         i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
0356         i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
0357         i2c_data = RADEON_DVI_I2C_DATA;
0358 
0359         switch (rdev->family) {
0360         case CHIP_R100:
0361         case CHIP_RV100:
0362         case CHIP_RS100:
0363         case CHIP_RV200:
0364         case CHIP_RS200:
0365         case CHIP_RS300:
0366             switch (rec->mask_clk_reg) {
0367             case RADEON_GPIO_DVI_DDC:
0368                 /* no gpio select bit */
0369                 break;
0370             default:
0371                 DRM_ERROR("gpio not supported with hw i2c\n");
0372                 ret = -EINVAL;
0373                 goto done;
0374             }
0375             break;
0376         case CHIP_R200:
0377             /* only bit 4 on r200 */
0378             switch (rec->mask_clk_reg) {
0379             case RADEON_GPIO_DVI_DDC:
0380                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
0381                 break;
0382             case RADEON_GPIO_MONID:
0383                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
0384                 break;
0385             default:
0386                 DRM_ERROR("gpio not supported with hw i2c\n");
0387                 ret = -EINVAL;
0388                 goto done;
0389             }
0390             break;
0391         case CHIP_RV250:
0392         case CHIP_RV280:
0393             /* bits 3 and 4 */
0394             switch (rec->mask_clk_reg) {
0395             case RADEON_GPIO_DVI_DDC:
0396                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
0397                 break;
0398             case RADEON_GPIO_VGA_DDC:
0399                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
0400                 break;
0401             case RADEON_GPIO_CRT2_DDC:
0402                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
0403                 break;
0404             default:
0405                 DRM_ERROR("gpio not supported with hw i2c\n");
0406                 ret = -EINVAL;
0407                 goto done;
0408             }
0409             break;
0410         case CHIP_R300:
0411         case CHIP_R350:
0412             /* only bit 4 on r300/r350 */
0413             switch (rec->mask_clk_reg) {
0414             case RADEON_GPIO_VGA_DDC:
0415                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
0416                 break;
0417             case RADEON_GPIO_DVI_DDC:
0418                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
0419                 break;
0420             default:
0421                 DRM_ERROR("gpio not supported with hw i2c\n");
0422                 ret = -EINVAL;
0423                 goto done;
0424             }
0425             break;
0426         case CHIP_RV350:
0427         case CHIP_RV380:
0428         case CHIP_R420:
0429         case CHIP_R423:
0430         case CHIP_RV410:
0431         case CHIP_RS400:
0432         case CHIP_RS480:
0433             /* bits 3 and 4 */
0434             switch (rec->mask_clk_reg) {
0435             case RADEON_GPIO_VGA_DDC:
0436                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
0437                 break;
0438             case RADEON_GPIO_DVI_DDC:
0439                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
0440                 break;
0441             case RADEON_GPIO_MONID:
0442                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
0443                 break;
0444             default:
0445                 DRM_ERROR("gpio not supported with hw i2c\n");
0446                 ret = -EINVAL;
0447                 goto done;
0448             }
0449             break;
0450         default:
0451             DRM_ERROR("unsupported asic\n");
0452             ret = -EINVAL;
0453             goto done;
0454             break;
0455         }
0456     }
0457 
0458     /* check for bus probe */
0459     p = &msgs[0];
0460     if ((num == 1) && (p->len == 0)) {
0461         WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
0462                     RADEON_I2C_NACK |
0463                     RADEON_I2C_HALT |
0464                     RADEON_I2C_SOFT_RST));
0465         WREG32(i2c_data, (p->addr << 1) & 0xff);
0466         WREG32(i2c_data, 0);
0467         WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
0468                     (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
0469                     RADEON_I2C_EN |
0470                     (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
0471         WREG32(i2c_cntl_0, reg);
0472         for (k = 0; k < 32; k++) {
0473             udelay(10);
0474             tmp = RREG32(i2c_cntl_0);
0475             if (tmp & RADEON_I2C_GO)
0476                 continue;
0477             tmp = RREG32(i2c_cntl_0);
0478             if (tmp & RADEON_I2C_DONE)
0479                 break;
0480             else {
0481                 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
0482                 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
0483                 ret = -EIO;
0484                 goto done;
0485             }
0486         }
0487         goto done;
0488     }
0489 
0490     for (i = 0; i < num; i++) {
0491         p = &msgs[i];
0492         for (j = 0; j < p->len; j++) {
0493             if (p->flags & I2C_M_RD) {
0494                 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
0495                             RADEON_I2C_NACK |
0496                             RADEON_I2C_HALT |
0497                             RADEON_I2C_SOFT_RST));
0498                 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
0499                 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
0500                             (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
0501                             RADEON_I2C_EN |
0502                             (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
0503                 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
0504                 for (k = 0; k < 32; k++) {
0505                     udelay(10);
0506                     tmp = RREG32(i2c_cntl_0);
0507                     if (tmp & RADEON_I2C_GO)
0508                         continue;
0509                     tmp = RREG32(i2c_cntl_0);
0510                     if (tmp & RADEON_I2C_DONE)
0511                         break;
0512                     else {
0513                         DRM_DEBUG("i2c read error 0x%08x\n", tmp);
0514                         WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
0515                         ret = -EIO;
0516                         goto done;
0517                     }
0518                 }
0519                 p->buf[j] = RREG32(i2c_data) & 0xff;
0520             } else {
0521                 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
0522                             RADEON_I2C_NACK |
0523                             RADEON_I2C_HALT |
0524                             RADEON_I2C_SOFT_RST));
0525                 WREG32(i2c_data, (p->addr << 1) & 0xff);
0526                 WREG32(i2c_data, p->buf[j]);
0527                 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
0528                             (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
0529                             RADEON_I2C_EN |
0530                             (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
0531                 WREG32(i2c_cntl_0, reg);
0532                 for (k = 0; k < 32; k++) {
0533                     udelay(10);
0534                     tmp = RREG32(i2c_cntl_0);
0535                     if (tmp & RADEON_I2C_GO)
0536                         continue;
0537                     tmp = RREG32(i2c_cntl_0);
0538                     if (tmp & RADEON_I2C_DONE)
0539                         break;
0540                     else {
0541                         DRM_DEBUG("i2c write error 0x%08x\n", tmp);
0542                         WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
0543                         ret = -EIO;
0544                         goto done;
0545                     }
0546                 }
0547             }
0548         }
0549     }
0550 
0551 done:
0552     WREG32(i2c_cntl_0, 0);
0553     WREG32(i2c_cntl_1, 0);
0554     WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
0555                 RADEON_I2C_NACK |
0556                 RADEON_I2C_HALT |
0557                 RADEON_I2C_SOFT_RST));
0558 
0559     if (rdev->is_atom_bios) {
0560         tmp = RREG32(RADEON_BIOS_6_SCRATCH);
0561         tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
0562         WREG32(RADEON_BIOS_6_SCRATCH, tmp);
0563     }
0564 
0565     mutex_unlock(&rdev->pm.mutex);
0566     mutex_unlock(&rdev->dc_hw_i2c_mutex);
0567 
0568     return ret;
0569 }
0570 
0571 /* hw i2c engine for r5xx hardware
0572  * hw can buffer up to 15 bytes
0573  */
0574 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
0575                 struct i2c_msg *msgs, int num)
0576 {
0577     struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
0578     struct radeon_device *rdev = i2c->dev->dev_private;
0579     struct radeon_i2c_bus_rec *rec = &i2c->rec;
0580     struct i2c_msg *p;
0581     int i, j, remaining, current_count, buffer_offset, ret = num;
0582     u32 prescale;
0583     u32 tmp, reg;
0584     u32 saved1, saved2;
0585 
0586     mutex_lock(&rdev->dc_hw_i2c_mutex);
0587     /* take the pm lock since we need a constant sclk */
0588     mutex_lock(&rdev->pm.mutex);
0589 
0590     prescale = radeon_get_i2c_prescale(rdev);
0591 
0592     /* clear gpio mask bits */
0593     tmp = RREG32(rec->mask_clk_reg);
0594     tmp &= ~rec->mask_clk_mask;
0595     WREG32(rec->mask_clk_reg, tmp);
0596     tmp = RREG32(rec->mask_clk_reg);
0597 
0598     tmp = RREG32(rec->mask_data_reg);
0599     tmp &= ~rec->mask_data_mask;
0600     WREG32(rec->mask_data_reg, tmp);
0601     tmp = RREG32(rec->mask_data_reg);
0602 
0603     /* clear pin values */
0604     tmp = RREG32(rec->a_clk_reg);
0605     tmp &= ~rec->a_clk_mask;
0606     WREG32(rec->a_clk_reg, tmp);
0607     tmp = RREG32(rec->a_clk_reg);
0608 
0609     tmp = RREG32(rec->a_data_reg);
0610     tmp &= ~rec->a_data_mask;
0611     WREG32(rec->a_data_reg, tmp);
0612     tmp = RREG32(rec->a_data_reg);
0613 
0614     /* set the pins to input */
0615     tmp = RREG32(rec->en_clk_reg);
0616     tmp &= ~rec->en_clk_mask;
0617     WREG32(rec->en_clk_reg, tmp);
0618     tmp = RREG32(rec->en_clk_reg);
0619 
0620     tmp = RREG32(rec->en_data_reg);
0621     tmp &= ~rec->en_data_mask;
0622     WREG32(rec->en_data_reg, tmp);
0623     tmp = RREG32(rec->en_data_reg);
0624 
0625     /* */
0626     tmp = RREG32(RADEON_BIOS_6_SCRATCH);
0627     WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
0628     saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
0629     saved2 = RREG32(0x494);
0630     WREG32(0x494, saved2 | 0x1);
0631 
0632     WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
0633     for (i = 0; i < 50; i++) {
0634         udelay(1);
0635         if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
0636             break;
0637     }
0638     if (i == 50) {
0639         DRM_ERROR("failed to get i2c bus\n");
0640         ret = -EBUSY;
0641         goto done;
0642     }
0643 
0644     reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
0645     switch (rec->mask_clk_reg) {
0646     case AVIVO_DC_GPIO_DDC1_MASK:
0647         reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
0648         break;
0649     case AVIVO_DC_GPIO_DDC2_MASK:
0650         reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
0651         break;
0652     case AVIVO_DC_GPIO_DDC3_MASK:
0653         reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
0654         break;
0655     default:
0656         DRM_ERROR("gpio not supported with hw i2c\n");
0657         ret = -EINVAL;
0658         goto done;
0659     }
0660 
0661     /* check for bus probe */
0662     p = &msgs[0];
0663     if ((num == 1) && (p->len == 0)) {
0664         WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
0665                           AVIVO_DC_I2C_NACK |
0666                           AVIVO_DC_I2C_HALT));
0667         WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
0668         udelay(1);
0669         WREG32(AVIVO_DC_I2C_RESET, 0);
0670 
0671         WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
0672         WREG32(AVIVO_DC_I2C_DATA, 0);
0673 
0674         WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
0675         WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
0676                            AVIVO_DC_I2C_DATA_COUNT(1) |
0677                            (prescale << 16)));
0678         WREG32(AVIVO_DC_I2C_CONTROL1, reg);
0679         WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
0680         for (j = 0; j < 200; j++) {
0681             udelay(50);
0682             tmp = RREG32(AVIVO_DC_I2C_STATUS1);
0683             if (tmp & AVIVO_DC_I2C_GO)
0684                 continue;
0685             tmp = RREG32(AVIVO_DC_I2C_STATUS1);
0686             if (tmp & AVIVO_DC_I2C_DONE)
0687                 break;
0688             else {
0689                 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
0690                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
0691                 ret = -EIO;
0692                 goto done;
0693             }
0694         }
0695         goto done;
0696     }
0697 
0698     for (i = 0; i < num; i++) {
0699         p = &msgs[i];
0700         remaining = p->len;
0701         buffer_offset = 0;
0702         if (p->flags & I2C_M_RD) {
0703             while (remaining) {
0704                 if (remaining > 15)
0705                     current_count = 15;
0706                 else
0707                     current_count = remaining;
0708                 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
0709                                   AVIVO_DC_I2C_NACK |
0710                                   AVIVO_DC_I2C_HALT));
0711                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
0712                 udelay(1);
0713                 WREG32(AVIVO_DC_I2C_RESET, 0);
0714 
0715                 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
0716                 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
0717                 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
0718                                    AVIVO_DC_I2C_DATA_COUNT(current_count) |
0719                                    (prescale << 16)));
0720                 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
0721                 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
0722                 for (j = 0; j < 200; j++) {
0723                     udelay(50);
0724                     tmp = RREG32(AVIVO_DC_I2C_STATUS1);
0725                     if (tmp & AVIVO_DC_I2C_GO)
0726                         continue;
0727                     tmp = RREG32(AVIVO_DC_I2C_STATUS1);
0728                     if (tmp & AVIVO_DC_I2C_DONE)
0729                         break;
0730                     else {
0731                         DRM_DEBUG("i2c read error 0x%08x\n", tmp);
0732                         WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
0733                         ret = -EIO;
0734                         goto done;
0735                     }
0736                 }
0737                 for (j = 0; j < current_count; j++)
0738                     p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
0739                 remaining -= current_count;
0740                 buffer_offset += current_count;
0741             }
0742         } else {
0743             while (remaining) {
0744                 if (remaining > 15)
0745                     current_count = 15;
0746                 else
0747                     current_count = remaining;
0748                 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
0749                                   AVIVO_DC_I2C_NACK |
0750                                   AVIVO_DC_I2C_HALT));
0751                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
0752                 udelay(1);
0753                 WREG32(AVIVO_DC_I2C_RESET, 0);
0754 
0755                 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
0756                 for (j = 0; j < current_count; j++)
0757                     WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
0758 
0759                 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
0760                 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
0761                                    AVIVO_DC_I2C_DATA_COUNT(current_count) |
0762                                    (prescale << 16)));
0763                 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
0764                 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
0765                 for (j = 0; j < 200; j++) {
0766                     udelay(50);
0767                     tmp = RREG32(AVIVO_DC_I2C_STATUS1);
0768                     if (tmp & AVIVO_DC_I2C_GO)
0769                         continue;
0770                     tmp = RREG32(AVIVO_DC_I2C_STATUS1);
0771                     if (tmp & AVIVO_DC_I2C_DONE)
0772                         break;
0773                     else {
0774                         DRM_DEBUG("i2c write error 0x%08x\n", tmp);
0775                         WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
0776                         ret = -EIO;
0777                         goto done;
0778                     }
0779                 }
0780                 remaining -= current_count;
0781                 buffer_offset += current_count;
0782             }
0783         }
0784     }
0785 
0786 done:
0787     WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
0788                       AVIVO_DC_I2C_NACK |
0789                       AVIVO_DC_I2C_HALT));
0790     WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
0791     udelay(1);
0792     WREG32(AVIVO_DC_I2C_RESET, 0);
0793 
0794     WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
0795     WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
0796     WREG32(0x494, saved2);
0797     tmp = RREG32(RADEON_BIOS_6_SCRATCH);
0798     tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
0799     WREG32(RADEON_BIOS_6_SCRATCH, tmp);
0800 
0801     mutex_unlock(&rdev->pm.mutex);
0802     mutex_unlock(&rdev->dc_hw_i2c_mutex);
0803 
0804     return ret;
0805 }
0806 
0807 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
0808                   struct i2c_msg *msgs, int num)
0809 {
0810     struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
0811     struct radeon_device *rdev = i2c->dev->dev_private;
0812     struct radeon_i2c_bus_rec *rec = &i2c->rec;
0813     int ret = 0;
0814 
0815     mutex_lock(&i2c->mutex);
0816 
0817     switch (rdev->family) {
0818     case CHIP_R100:
0819     case CHIP_RV100:
0820     case CHIP_RS100:
0821     case CHIP_RV200:
0822     case CHIP_RS200:
0823     case CHIP_R200:
0824     case CHIP_RV250:
0825     case CHIP_RS300:
0826     case CHIP_RV280:
0827     case CHIP_R300:
0828     case CHIP_R350:
0829     case CHIP_RV350:
0830     case CHIP_RV380:
0831     case CHIP_R420:
0832     case CHIP_R423:
0833     case CHIP_RV410:
0834     case CHIP_RS400:
0835     case CHIP_RS480:
0836         ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
0837         break;
0838     case CHIP_RS600:
0839     case CHIP_RS690:
0840     case CHIP_RS740:
0841         /* XXX fill in hw i2c implementation */
0842         break;
0843     case CHIP_RV515:
0844     case CHIP_R520:
0845     case CHIP_RV530:
0846     case CHIP_RV560:
0847     case CHIP_RV570:
0848     case CHIP_R580:
0849         if (rec->mm_i2c)
0850             ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
0851         else
0852             ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
0853         break;
0854     case CHIP_R600:
0855     case CHIP_RV610:
0856     case CHIP_RV630:
0857     case CHIP_RV670:
0858         /* XXX fill in hw i2c implementation */
0859         break;
0860     case CHIP_RV620:
0861     case CHIP_RV635:
0862     case CHIP_RS780:
0863     case CHIP_RS880:
0864     case CHIP_RV770:
0865     case CHIP_RV730:
0866     case CHIP_RV710:
0867     case CHIP_RV740:
0868         /* XXX fill in hw i2c implementation */
0869         break;
0870     case CHIP_CEDAR:
0871     case CHIP_REDWOOD:
0872     case CHIP_JUNIPER:
0873     case CHIP_CYPRESS:
0874     case CHIP_HEMLOCK:
0875         /* XXX fill in hw i2c implementation */
0876         break;
0877     default:
0878         DRM_ERROR("i2c: unhandled radeon chip\n");
0879         ret = -EIO;
0880         break;
0881     }
0882 
0883     mutex_unlock(&i2c->mutex);
0884 
0885     return ret;
0886 }
0887 
0888 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)
0889 {
0890     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
0891 }
0892 
0893 static const struct i2c_algorithm radeon_i2c_algo = {
0894     .master_xfer = radeon_hw_i2c_xfer,
0895     .functionality = radeon_hw_i2c_func,
0896 };
0897 
0898 static const struct i2c_algorithm radeon_atom_i2c_algo = {
0899     .master_xfer = radeon_atom_hw_i2c_xfer,
0900     .functionality = radeon_atom_hw_i2c_func,
0901 };
0902 
0903 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
0904                       struct radeon_i2c_bus_rec *rec,
0905                       const char *name)
0906 {
0907     struct radeon_device *rdev = dev->dev_private;
0908     struct radeon_i2c_chan *i2c;
0909     int ret;
0910 
0911     /* don't add the mm_i2c bus unless hw_i2c is enabled */
0912     if (rec->mm_i2c && (radeon_hw_i2c == 0))
0913         return NULL;
0914 
0915     i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
0916     if (i2c == NULL)
0917         return NULL;
0918 
0919     i2c->rec = *rec;
0920     i2c->adapter.owner = THIS_MODULE;
0921     i2c->adapter.class = I2C_CLASS_DDC;
0922     i2c->adapter.dev.parent = dev->dev;
0923     i2c->dev = dev;
0924     i2c_set_adapdata(&i2c->adapter, i2c);
0925     mutex_init(&i2c->mutex);
0926     if (rec->mm_i2c ||
0927         (rec->hw_capable &&
0928          radeon_hw_i2c &&
0929          ((rdev->family <= CHIP_RS480) ||
0930           ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
0931         /* set the radeon hw i2c adapter */
0932         snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
0933              "Radeon i2c hw bus %s", name);
0934         i2c->adapter.algo = &radeon_i2c_algo;
0935         ret = i2c_add_adapter(&i2c->adapter);
0936         if (ret)
0937             goto out_free;
0938     } else if (rec->hw_capable &&
0939            radeon_hw_i2c &&
0940            ASIC_IS_DCE3(rdev)) {
0941         /* hw i2c using atom */
0942         snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
0943              "Radeon i2c hw bus %s", name);
0944         i2c->adapter.algo = &radeon_atom_i2c_algo;
0945         ret = i2c_add_adapter(&i2c->adapter);
0946         if (ret)
0947             goto out_free;
0948     } else {
0949         /* set the radeon bit adapter */
0950         snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
0951              "Radeon i2c bit bus %s", name);
0952         i2c->adapter.algo_data = &i2c->bit;
0953         i2c->bit.pre_xfer = pre_xfer;
0954         i2c->bit.post_xfer = post_xfer;
0955         i2c->bit.setsda = set_data;
0956         i2c->bit.setscl = set_clock;
0957         i2c->bit.getsda = get_data;
0958         i2c->bit.getscl = get_clock;
0959         i2c->bit.udelay = 10;
0960         i2c->bit.timeout = usecs_to_jiffies(2200);  /* from VESA */
0961         i2c->bit.data = i2c;
0962         ret = i2c_bit_add_bus(&i2c->adapter);
0963         if (ret) {
0964             DRM_ERROR("Failed to register bit i2c %s\n", name);
0965             goto out_free;
0966         }
0967     }
0968 
0969     return i2c;
0970 out_free:
0971     kfree(i2c);
0972     return NULL;
0973 
0974 }
0975 
0976 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
0977 {
0978     if (!i2c)
0979         return;
0980     WARN_ON(i2c->has_aux);
0981     i2c_del_adapter(&i2c->adapter);
0982     kfree(i2c);
0983 }
0984 
0985 /* Add the default buses */
0986 void radeon_i2c_init(struct radeon_device *rdev)
0987 {
0988     if (radeon_hw_i2c)
0989         DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n");
0990 
0991     if (rdev->is_atom_bios)
0992         radeon_atombios_i2c_init(rdev);
0993     else
0994         radeon_combios_i2c_init(rdev);
0995 }
0996 
0997 /* remove all the buses */
0998 void radeon_i2c_fini(struct radeon_device *rdev)
0999 {
1000     int i;
1001 
1002     for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1003         if (rdev->i2c_bus[i]) {
1004             radeon_i2c_destroy(rdev->i2c_bus[i]);
1005             rdev->i2c_bus[i] = NULL;
1006         }
1007     }
1008 }
1009 
1010 /* Add additional buses */
1011 void radeon_i2c_add(struct radeon_device *rdev,
1012             struct radeon_i2c_bus_rec *rec,
1013             const char *name)
1014 {
1015     struct drm_device *dev = rdev->ddev;
1016     int i;
1017 
1018     for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1019         if (!rdev->i2c_bus[i]) {
1020             rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name);
1021             return;
1022         }
1023     }
1024 }
1025 
1026 /* looks up bus based on id */
1027 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
1028                       struct radeon_i2c_bus_rec *i2c_bus)
1029 {
1030     int i;
1031 
1032     for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1033         if (rdev->i2c_bus[i] &&
1034             (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
1035             return rdev->i2c_bus[i];
1036         }
1037     }
1038     return NULL;
1039 }
1040 
1041 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
1042              u8 slave_addr,
1043              u8 addr,
1044              u8 *val)
1045 {
1046     u8 out_buf[2];
1047     u8 in_buf[2];
1048     struct i2c_msg msgs[] = {
1049         {
1050             .addr = slave_addr,
1051             .flags = 0,
1052             .len = 1,
1053             .buf = out_buf,
1054         },
1055         {
1056             .addr = slave_addr,
1057             .flags = I2C_M_RD,
1058             .len = 1,
1059             .buf = in_buf,
1060         }
1061     };
1062 
1063     out_buf[0] = addr;
1064     out_buf[1] = 0;
1065 
1066     if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
1067         *val = in_buf[0];
1068         DRM_DEBUG("val = 0x%02x\n", *val);
1069     } else {
1070         DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
1071               addr, *val);
1072     }
1073 }
1074 
1075 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1076              u8 slave_addr,
1077              u8 addr,
1078              u8 val)
1079 {
1080     uint8_t out_buf[2];
1081     struct i2c_msg msg = {
1082         .addr = slave_addr,
1083         .flags = 0,
1084         .len = 2,
1085         .buf = out_buf,
1086     };
1087 
1088     out_buf[0] = addr;
1089     out_buf[1] = val;
1090 
1091     if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
1092         DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
1093               addr, val);
1094 }
1095 
1096 /* ddc router switching */
1097 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector)
1098 {
1099     u8 val;
1100 
1101     if (!radeon_connector->router.ddc_valid)
1102         return;
1103 
1104     if (!radeon_connector->router_bus)
1105         return;
1106 
1107     radeon_i2c_get_byte(radeon_connector->router_bus,
1108                 radeon_connector->router.i2c_addr,
1109                 0x3, &val);
1110     val &= ~radeon_connector->router.ddc_mux_control_pin;
1111     radeon_i2c_put_byte(radeon_connector->router_bus,
1112                 radeon_connector->router.i2c_addr,
1113                 0x3, val);
1114     radeon_i2c_get_byte(radeon_connector->router_bus,
1115                 radeon_connector->router.i2c_addr,
1116                 0x1, &val);
1117     val &= ~radeon_connector->router.ddc_mux_control_pin;
1118     val |= radeon_connector->router.ddc_mux_state;
1119     radeon_i2c_put_byte(radeon_connector->router_bus,
1120                 radeon_connector->router.i2c_addr,
1121                 0x1, val);
1122 }
1123 
1124 /* clock/data router switching */
1125 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector)
1126 {
1127     u8 val;
1128 
1129     if (!radeon_connector->router.cd_valid)
1130         return;
1131 
1132     if (!radeon_connector->router_bus)
1133         return;
1134 
1135     radeon_i2c_get_byte(radeon_connector->router_bus,
1136                 radeon_connector->router.i2c_addr,
1137                 0x3, &val);
1138     val &= ~radeon_connector->router.cd_mux_control_pin;
1139     radeon_i2c_put_byte(radeon_connector->router_bus,
1140                 radeon_connector->router.i2c_addr,
1141                 0x3, val);
1142     radeon_i2c_get_byte(radeon_connector->router_bus,
1143                 radeon_connector->router.i2c_addr,
1144                 0x1, &val);
1145     val &= ~radeon_connector->router.cd_mux_control_pin;
1146     val |= radeon_connector->router.cd_mux_state;
1147     radeon_i2c_put_byte(radeon_connector->router_bus,
1148                 radeon_connector->router.i2c_addr,
1149                 0x1, val);
1150 }
1151
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