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0001 /*
0002  * \file radeon_drv.c
0003  * ATI Radeon driver
0004  *
0005  * \author Gareth Hughes <gareth@valinux.com>
0006  */
0007 
0008 /*
0009  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
0010  * All Rights Reserved.
0011  *
0012  * Permission is hereby granted, free of charge, to any person obtaining a
0013  * copy of this software and associated documentation files (the "Software"),
0014  * to deal in the Software without restriction, including without limitation
0015  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0016  * and/or sell copies of the Software, and to permit persons to whom the
0017  * Software is furnished to do so, subject to the following conditions:
0018  *
0019  * The above copyright notice and this permission notice (including the next
0020  * paragraph) shall be included in all copies or substantial portions of the
0021  * Software.
0022  *
0023  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0024  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0025  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0026  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
0027  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0028  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0029  * OTHER DEALINGS IN THE SOFTWARE.
0030  */
0031 
0032 
0033 #include <linux/compat.h>
0034 #include <linux/module.h>
0035 #include <linux/pm_runtime.h>
0036 #include <linux/vga_switcheroo.h>
0037 #include <linux/mmu_notifier.h>
0038 #include <linux/pci.h>
0039 
0040 #include <drm/drm_aperture.h>
0041 #include <drm/drm_crtc_helper.h>
0042 #include <drm/drm_drv.h>
0043 #include <drm/drm_fb_helper.h>
0044 #include <drm/drm_file.h>
0045 #include <drm/drm_gem.h>
0046 #include <drm/drm_ioctl.h>
0047 #include <drm/drm_pciids.h>
0048 #include <drm/drm_probe_helper.h>
0049 #include <drm/drm_vblank.h>
0050 #include <drm/radeon_drm.h>
0051 
0052 #include "radeon_drv.h"
0053 #include "radeon.h"
0054 #include "radeon_kms.h"
0055 #include "radeon_ttm.h"
0056 #include "radeon_device.h"
0057 #include "radeon_prime.h"
0058 
0059 /*
0060  * KMS wrapper.
0061  * - 2.0.0 - initial interface
0062  * - 2.1.0 - add square tiling interface
0063  * - 2.2.0 - add r6xx/r7xx const buffer support
0064  * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
0065  * - 2.4.0 - add crtc id query
0066  * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
0067  * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
0068  *   2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
0069  *   2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
0070  *   2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
0071  *   2.10.0 - fusion 2D tiling
0072  *   2.11.0 - backend map, initial compute support for the CS checker
0073  *   2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
0074  *   2.13.0 - virtual memory support, streamout
0075  *   2.14.0 - add evergreen tiling informations
0076  *   2.15.0 - add max_pipes query
0077  *   2.16.0 - fix evergreen 2D tiled surface calculation
0078  *   2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
0079  *   2.18.0 - r600-eg: allow "invalid" DB formats
0080  *   2.19.0 - r600-eg: MSAA textures
0081  *   2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
0082  *   2.21.0 - r600-r700: FMASK and CMASK
0083  *   2.22.0 - r600 only: RESOLVE_BOX allowed
0084  *   2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
0085  *   2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
0086  *   2.25.0 - eg+: new info request for num SE and num SH
0087  *   2.26.0 - r600-eg: fix htile size computation
0088  *   2.27.0 - r600-SI: Add CS ioctl support for async DMA
0089  *   2.28.0 - r600-eg: Add MEM_WRITE packet support
0090  *   2.29.0 - R500 FP16 color clear registers
0091  *   2.30.0 - fix for FMASK texturing
0092  *   2.31.0 - Add fastfb support for rs690
0093  *   2.32.0 - new info request for rings working
0094  *   2.33.0 - Add SI tiling mode array query
0095  *   2.34.0 - Add CIK tiling mode array query
0096  *   2.35.0 - Add CIK macrotile mode array query
0097  *   2.36.0 - Fix CIK DCE tiling setup
0098  *   2.37.0 - allow GS ring setup on r6xx/r7xx
0099  *   2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
0100  *            CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
0101  *   2.39.0 - Add INFO query for number of active CUs
0102  *   2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
0103  *            CS to GPU on >= r600
0104  *   2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
0105  *   2.42.0 - Add VCE/VUI (Video Usability Information) support
0106  *   2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
0107  *   2.44.0 - SET_APPEND_CNT packet3 support
0108  *   2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
0109  *   2.46.0 - Add PFP_SYNC_ME support on evergreen
0110  *   2.47.0 - Add UVD_NO_OP register support
0111  *   2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
0112  *   2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values
0113  *   2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL)
0114  */
0115 #define KMS_DRIVER_MAJOR    2
0116 #define KMS_DRIVER_MINOR    50
0117 #define KMS_DRIVER_PATCHLEVEL   0
0118 int radeon_suspend_kms(struct drm_device *dev, bool suspend,
0119                bool fbcon, bool freeze);
0120 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
0121 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
0122                       unsigned int flags, int *vpos, int *hpos,
0123                       ktime_t *stime, ktime_t *etime,
0124                       const struct drm_display_mode *mode);
0125 extern bool radeon_is_px(struct drm_device *dev);
0126 int radeon_mode_dumb_mmap(struct drm_file *filp,
0127               struct drm_device *dev,
0128               uint32_t handle, uint64_t *offset_p);
0129 int radeon_mode_dumb_create(struct drm_file *file_priv,
0130                 struct drm_device *dev,
0131                 struct drm_mode_create_dumb *args);
0132 
0133 /* atpx handler */
0134 #if defined(CONFIG_VGA_SWITCHEROO)
0135 void radeon_register_atpx_handler(void);
0136 void radeon_unregister_atpx_handler(void);
0137 bool radeon_has_atpx_dgpu_power_cntl(void);
0138 bool radeon_is_atpx_hybrid(void);
0139 #else
0140 static inline void radeon_register_atpx_handler(void) {}
0141 static inline void radeon_unregister_atpx_handler(void) {}
0142 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
0143 static inline bool radeon_is_atpx_hybrid(void) { return false; }
0144 #endif
0145 
0146 int radeon_no_wb;
0147 int radeon_modeset = -1;
0148 int radeon_dynclks = -1;
0149 int radeon_r4xx_atom = 0;
0150 int radeon_agpmode = -1;
0151 int radeon_vram_limit = 0;
0152 int radeon_gart_size = -1; /* auto */
0153 int radeon_benchmarking = 0;
0154 int radeon_testing = 0;
0155 int radeon_connector_table = 0;
0156 int radeon_tv = 1;
0157 int radeon_audio = -1;
0158 int radeon_disp_priority = 0;
0159 int radeon_hw_i2c = 0;
0160 int radeon_pcie_gen2 = -1;
0161 int radeon_msi = -1;
0162 int radeon_lockup_timeout = 10000;
0163 int radeon_fastfb = 0;
0164 int radeon_dpm = -1;
0165 int radeon_aspm = -1;
0166 int radeon_runtime_pm = -1;
0167 int radeon_hard_reset = 0;
0168 int radeon_vm_size = 8;
0169 int radeon_vm_block_size = -1;
0170 int radeon_deep_color = 0;
0171 int radeon_use_pflipirq = 2;
0172 int radeon_bapm = -1;
0173 int radeon_backlight = -1;
0174 int radeon_auxch = -1;
0175 int radeon_mst = 0;
0176 int radeon_uvd = 1;
0177 int radeon_vce = 1;
0178 
0179 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
0180 module_param_named(no_wb, radeon_no_wb, int, 0444);
0181 
0182 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
0183 module_param_named(modeset, radeon_modeset, int, 0400);
0184 
0185 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
0186 module_param_named(dynclks, radeon_dynclks, int, 0444);
0187 
0188 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
0189 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
0190 
0191 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
0192 module_param_named(vramlimit, radeon_vram_limit, int, 0600);
0193 
0194 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
0195 module_param_named(agpmode, radeon_agpmode, int, 0444);
0196 
0197 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
0198 module_param_named(gartsize, radeon_gart_size, int, 0600);
0199 
0200 MODULE_PARM_DESC(benchmark, "Run benchmark");
0201 module_param_named(benchmark, radeon_benchmarking, int, 0444);
0202 
0203 MODULE_PARM_DESC(test, "Run tests");
0204 module_param_named(test, radeon_testing, int, 0444);
0205 
0206 MODULE_PARM_DESC(connector_table, "Force connector table");
0207 module_param_named(connector_table, radeon_connector_table, int, 0444);
0208 
0209 MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
0210 module_param_named(tv, radeon_tv, int, 0444);
0211 
0212 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
0213 module_param_named(audio, radeon_audio, int, 0444);
0214 
0215 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
0216 module_param_named(disp_priority, radeon_disp_priority, int, 0444);
0217 
0218 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
0219 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
0220 
0221 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
0222 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
0223 
0224 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
0225 module_param_named(msi, radeon_msi, int, 0444);
0226 
0227 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
0228 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
0229 
0230 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
0231 module_param_named(fastfb, radeon_fastfb, int, 0444);
0232 
0233 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
0234 module_param_named(dpm, radeon_dpm, int, 0444);
0235 
0236 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
0237 module_param_named(aspm, radeon_aspm, int, 0444);
0238 
0239 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
0240 module_param_named(runpm, radeon_runtime_pm, int, 0444);
0241 
0242 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
0243 module_param_named(hard_reset, radeon_hard_reset, int, 0444);
0244 
0245 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
0246 module_param_named(vm_size, radeon_vm_size, int, 0444);
0247 
0248 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
0249 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
0250 
0251 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
0252 module_param_named(deep_color, radeon_deep_color, int, 0444);
0253 
0254 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
0255 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
0256 
0257 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
0258 module_param_named(bapm, radeon_bapm, int, 0444);
0259 
0260 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
0261 module_param_named(backlight, radeon_backlight, int, 0444);
0262 
0263 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
0264 module_param_named(auxch, radeon_auxch, int, 0444);
0265 
0266 MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
0267 module_param_named(mst, radeon_mst, int, 0444);
0268 
0269 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
0270 module_param_named(uvd, radeon_uvd, int, 0444);
0271 
0272 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
0273 module_param_named(vce, radeon_vce, int, 0444);
0274 
0275 int radeon_si_support = 1;
0276 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
0277 module_param_named(si_support, radeon_si_support, int, 0444);
0278 
0279 int radeon_cik_support = 1;
0280 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
0281 module_param_named(cik_support, radeon_cik_support, int, 0444);
0282 
0283 static struct pci_device_id pciidlist[] = {
0284     radeon_PCI_IDS
0285 };
0286 
0287 MODULE_DEVICE_TABLE(pci, pciidlist);
0288 
0289 static const struct drm_driver kms_driver;
0290 
0291 static int radeon_pci_probe(struct pci_dev *pdev,
0292                 const struct pci_device_id *ent)
0293 {
0294     unsigned long flags = 0;
0295     struct drm_device *dev;
0296     int ret;
0297 
0298     if (!ent)
0299         return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */
0300 
0301     flags = ent->driver_data;
0302 
0303     if (!radeon_si_support) {
0304         switch (flags & RADEON_FAMILY_MASK) {
0305         case CHIP_TAHITI:
0306         case CHIP_PITCAIRN:
0307         case CHIP_VERDE:
0308         case CHIP_OLAND:
0309         case CHIP_HAINAN:
0310             dev_info(&pdev->dev,
0311                  "SI support disabled by module param\n");
0312             return -ENODEV;
0313         }
0314     }
0315     if (!radeon_cik_support) {
0316         switch (flags & RADEON_FAMILY_MASK) {
0317         case CHIP_KAVERI:
0318         case CHIP_BONAIRE:
0319         case CHIP_HAWAII:
0320         case CHIP_KABINI:
0321         case CHIP_MULLINS:
0322             dev_info(&pdev->dev,
0323                  "CIK support disabled by module param\n");
0324             return -ENODEV;
0325         }
0326     }
0327 
0328     if (vga_switcheroo_client_probe_defer(pdev))
0329         return -EPROBE_DEFER;
0330 
0331     /* Get rid of things like offb */
0332     ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &kms_driver);
0333     if (ret)
0334         return ret;
0335 
0336     dev = drm_dev_alloc(&kms_driver, &pdev->dev);
0337     if (IS_ERR(dev))
0338         return PTR_ERR(dev);
0339 
0340     ret = pci_enable_device(pdev);
0341     if (ret)
0342         goto err_free;
0343 
0344     pci_set_drvdata(pdev, dev);
0345 
0346     ret = drm_dev_register(dev, ent->driver_data);
0347     if (ret)
0348         goto err_agp;
0349 
0350     return 0;
0351 
0352 err_agp:
0353     pci_disable_device(pdev);
0354 err_free:
0355     drm_dev_put(dev);
0356     return ret;
0357 }
0358 
0359 static void
0360 radeon_pci_remove(struct pci_dev *pdev)
0361 {
0362     struct drm_device *dev = pci_get_drvdata(pdev);
0363 
0364     drm_put_dev(dev);
0365 }
0366 
0367 static void
0368 radeon_pci_shutdown(struct pci_dev *pdev)
0369 {
0370     /* if we are running in a VM, make sure the device
0371      * torn down properly on reboot/shutdown
0372      */
0373     if (radeon_device_is_virtual())
0374         radeon_pci_remove(pdev);
0375 
0376 #if defined(CONFIG_PPC64) || defined(CONFIG_MACH_LOONGSON64)
0377     /*
0378      * Some adapters need to be suspended before a
0379      * shutdown occurs in order to prevent an error
0380      * during kexec, shutdown or reboot.
0381      * Make this power and Loongson specific because
0382      * it breaks some other boards.
0383      */
0384     radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false);
0385 #endif
0386 }
0387 
0388 static int radeon_pmops_suspend(struct device *dev)
0389 {
0390     struct drm_device *drm_dev = dev_get_drvdata(dev);
0391     return radeon_suspend_kms(drm_dev, true, true, false);
0392 }
0393 
0394 static int radeon_pmops_resume(struct device *dev)
0395 {
0396     struct drm_device *drm_dev = dev_get_drvdata(dev);
0397 
0398     /* GPU comes up enabled by the bios on resume */
0399     if (radeon_is_px(drm_dev)) {
0400         pm_runtime_disable(dev);
0401         pm_runtime_set_active(dev);
0402         pm_runtime_enable(dev);
0403     }
0404 
0405     return radeon_resume_kms(drm_dev, true, true);
0406 }
0407 
0408 static int radeon_pmops_freeze(struct device *dev)
0409 {
0410     struct drm_device *drm_dev = dev_get_drvdata(dev);
0411     return radeon_suspend_kms(drm_dev, false, true, true);
0412 }
0413 
0414 static int radeon_pmops_thaw(struct device *dev)
0415 {
0416     struct drm_device *drm_dev = dev_get_drvdata(dev);
0417     return radeon_resume_kms(drm_dev, false, true);
0418 }
0419 
0420 static int radeon_pmops_runtime_suspend(struct device *dev)
0421 {
0422     struct pci_dev *pdev = to_pci_dev(dev);
0423     struct drm_device *drm_dev = pci_get_drvdata(pdev);
0424 
0425     if (!radeon_is_px(drm_dev)) {
0426         pm_runtime_forbid(dev);
0427         return -EBUSY;
0428     }
0429 
0430     drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
0431     drm_kms_helper_poll_disable(drm_dev);
0432 
0433     radeon_suspend_kms(drm_dev, false, false, false);
0434     pci_save_state(pdev);
0435     pci_disable_device(pdev);
0436     pci_ignore_hotplug(pdev);
0437     if (radeon_is_atpx_hybrid())
0438         pci_set_power_state(pdev, PCI_D3cold);
0439     else if (!radeon_has_atpx_dgpu_power_cntl())
0440         pci_set_power_state(pdev, PCI_D3hot);
0441     drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
0442 
0443     return 0;
0444 }
0445 
0446 static int radeon_pmops_runtime_resume(struct device *dev)
0447 {
0448     struct pci_dev *pdev = to_pci_dev(dev);
0449     struct drm_device *drm_dev = pci_get_drvdata(pdev);
0450     int ret;
0451 
0452     if (!radeon_is_px(drm_dev))
0453         return -EINVAL;
0454 
0455     drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
0456 
0457     if (radeon_is_atpx_hybrid() ||
0458         !radeon_has_atpx_dgpu_power_cntl())
0459         pci_set_power_state(pdev, PCI_D0);
0460     pci_restore_state(pdev);
0461     ret = pci_enable_device(pdev);
0462     if (ret)
0463         return ret;
0464     pci_set_master(pdev);
0465 
0466     ret = radeon_resume_kms(drm_dev, false, false);
0467     drm_kms_helper_poll_enable(drm_dev);
0468     drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
0469     return 0;
0470 }
0471 
0472 static int radeon_pmops_runtime_idle(struct device *dev)
0473 {
0474     struct drm_device *drm_dev = dev_get_drvdata(dev);
0475     struct drm_crtc *crtc;
0476 
0477     if (!radeon_is_px(drm_dev)) {
0478         pm_runtime_forbid(dev);
0479         return -EBUSY;
0480     }
0481 
0482     list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
0483         if (crtc->enabled) {
0484             DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
0485             return -EBUSY;
0486         }
0487     }
0488 
0489     pm_runtime_mark_last_busy(dev);
0490     pm_runtime_autosuspend(dev);
0491     /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
0492     return 1;
0493 }
0494 
0495 long radeon_drm_ioctl(struct file *filp,
0496               unsigned int cmd, unsigned long arg)
0497 {
0498     struct drm_file *file_priv = filp->private_data;
0499     struct drm_device *dev;
0500     long ret;
0501     dev = file_priv->minor->dev;
0502     ret = pm_runtime_get_sync(dev->dev);
0503     if (ret < 0) {
0504         pm_runtime_put_autosuspend(dev->dev);
0505         return ret;
0506     }
0507 
0508     ret = drm_ioctl(filp, cmd, arg);
0509 
0510     pm_runtime_mark_last_busy(dev->dev);
0511     pm_runtime_put_autosuspend(dev->dev);
0512     return ret;
0513 }
0514 
0515 #ifdef CONFIG_COMPAT
0516 static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
0517 {
0518     unsigned int nr = DRM_IOCTL_NR(cmd);
0519     int ret;
0520 
0521     if (nr < DRM_COMMAND_BASE)
0522         return drm_compat_ioctl(filp, cmd, arg);
0523 
0524     ret = radeon_drm_ioctl(filp, cmd, arg);
0525 
0526     return ret;
0527 }
0528 #endif
0529 
0530 static const struct dev_pm_ops radeon_pm_ops = {
0531     .suspend = radeon_pmops_suspend,
0532     .resume = radeon_pmops_resume,
0533     .freeze = radeon_pmops_freeze,
0534     .thaw = radeon_pmops_thaw,
0535     .poweroff = radeon_pmops_freeze,
0536     .restore = radeon_pmops_resume,
0537     .runtime_suspend = radeon_pmops_runtime_suspend,
0538     .runtime_resume = radeon_pmops_runtime_resume,
0539     .runtime_idle = radeon_pmops_runtime_idle,
0540 };
0541 
0542 static const struct file_operations radeon_driver_kms_fops = {
0543     .owner = THIS_MODULE,
0544     .open = drm_open,
0545     .release = drm_release,
0546     .unlocked_ioctl = radeon_drm_ioctl,
0547     .mmap = drm_gem_mmap,
0548     .poll = drm_poll,
0549     .read = drm_read,
0550 #ifdef CONFIG_COMPAT
0551     .compat_ioctl = radeon_kms_compat_ioctl,
0552 #endif
0553 };
0554 
0555 static const struct drm_ioctl_desc radeon_ioctls_kms[] = {
0556     DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
0557     DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
0558     DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
0559     DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
0560     DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
0561     DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
0562     DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
0563     DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
0564     DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
0565     DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
0566     DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
0567     DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
0568     DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
0569     DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
0570     DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
0571     DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
0572     DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
0573     DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
0574     DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
0575     DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
0576     DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
0577     DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
0578     DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
0579     DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
0580     DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
0581     DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
0582     DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
0583     /* KMS */
0584     DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
0585     DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
0586     DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
0587     DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
0588     DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
0589     DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
0590     DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
0591     DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
0592     DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
0593     DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
0594     DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
0595     DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
0596     DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
0597     DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
0598     DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
0599 };
0600 
0601 static const struct drm_driver kms_driver = {
0602     .driver_features =
0603         DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET,
0604     .load = radeon_driver_load_kms,
0605     .open = radeon_driver_open_kms,
0606     .postclose = radeon_driver_postclose_kms,
0607     .lastclose = radeon_driver_lastclose_kms,
0608     .unload = radeon_driver_unload_kms,
0609     .ioctls = radeon_ioctls_kms,
0610     .num_ioctls = ARRAY_SIZE(radeon_ioctls_kms),
0611     .dumb_create = radeon_mode_dumb_create,
0612     .dumb_map_offset = radeon_mode_dumb_mmap,
0613     .fops = &radeon_driver_kms_fops,
0614 
0615     .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
0616     .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
0617     .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
0618     .gem_prime_mmap = drm_gem_prime_mmap,
0619 
0620     .name = DRIVER_NAME,
0621     .desc = DRIVER_DESC,
0622     .date = DRIVER_DATE,
0623     .major = KMS_DRIVER_MAJOR,
0624     .minor = KMS_DRIVER_MINOR,
0625     .patchlevel = KMS_DRIVER_PATCHLEVEL,
0626 };
0627 
0628 static struct pci_driver radeon_kms_pci_driver = {
0629     .name = DRIVER_NAME,
0630     .id_table = pciidlist,
0631     .probe = radeon_pci_probe,
0632     .remove = radeon_pci_remove,
0633     .shutdown = radeon_pci_shutdown,
0634     .driver.pm = &radeon_pm_ops,
0635 };
0636 
0637 static int __init radeon_module_init(void)
0638 {
0639     if (drm_firmware_drivers_only() && radeon_modeset == -1)
0640         radeon_modeset = 0;
0641 
0642     if (radeon_modeset == 0)
0643         return -EINVAL;
0644 
0645     DRM_INFO("radeon kernel modesetting enabled.\n");
0646     radeon_register_atpx_handler();
0647 
0648     return pci_register_driver(&radeon_kms_pci_driver);
0649 }
0650 
0651 static void __exit radeon_module_exit(void)
0652 {
0653     pci_unregister_driver(&radeon_kms_pci_driver);
0654     radeon_unregister_atpx_handler();
0655     mmu_notifier_synchronize();
0656 }
0657 
0658 module_init(radeon_module_init);
0659 module_exit(radeon_module_exit);
0660 
0661 MODULE_AUTHOR(DRIVER_AUTHOR);
0662 MODULE_DESCRIPTION(DRIVER_DESC);
0663 MODULE_LICENSE("GPL and additional rights");
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