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0001 // SPDX-License-Identifier: MIT
0002 
0003 #include <drm/display/drm_dp_mst_helper.h>
0004 #include <drm/drm_fb_helper.h>
0005 #include <drm/drm_file.h>
0006 #include <drm/drm_probe_helper.h>
0007 
0008 #include "atom.h"
0009 #include "ni_reg.h"
0010 #include "radeon.h"
0011 
0012 static struct radeon_encoder *radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector);
0013 
0014 static int radeon_atom_set_enc_offset(int id)
0015 {
0016     static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET,
0017                        EVERGREEN_CRTC1_REGISTER_OFFSET,
0018                        EVERGREEN_CRTC2_REGISTER_OFFSET,
0019                        EVERGREEN_CRTC3_REGISTER_OFFSET,
0020                        EVERGREEN_CRTC4_REGISTER_OFFSET,
0021                        EVERGREEN_CRTC5_REGISTER_OFFSET,
0022                        0x13830 - 0x7030 };
0023 
0024     return offsets[id];
0025 }
0026 
0027 static int radeon_dp_mst_set_be_cntl(struct radeon_encoder *primary,
0028                      struct radeon_encoder_mst *mst_enc,
0029                      enum radeon_hpd_id hpd, bool enable)
0030 {
0031     struct drm_device *dev = primary->base.dev;
0032     struct radeon_device *rdev = dev->dev_private;
0033     uint32_t reg;
0034     int retries = 0;
0035     uint32_t temp;
0036 
0037     reg = RREG32(NI_DIG_BE_CNTL + primary->offset);
0038 
0039     /* set MST mode */
0040     reg &= ~NI_DIG_FE_DIG_MODE(7);
0041     reg |= NI_DIG_FE_DIG_MODE(NI_DIG_MODE_DP_MST);
0042 
0043     if (enable)
0044         reg |= NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
0045     else
0046         reg &= ~NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
0047 
0048     reg |= NI_DIG_HPD_SELECT(hpd);
0049     DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg);
0050     WREG32(NI_DIG_BE_CNTL + primary->offset, reg);
0051 
0052     if (enable) {
0053         uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
0054 
0055         do {
0056             temp = RREG32(NI_DIG_FE_CNTL + offset);
0057         } while ((temp & NI_DIG_SYMCLK_FE_ON) && retries++ < 10000);
0058         if (retries == 10000)
0059             DRM_ERROR("timed out waiting for FE %d %d\n", primary->offset, mst_enc->fe);
0060     }
0061     return 0;
0062 }
0063 
0064 static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary,
0065                        int stream_number,
0066                        int fe,
0067                        int slots)
0068 {
0069     struct drm_device *dev = primary->base.dev;
0070     struct radeon_device *rdev = dev->dev_private;
0071     u32 temp, val;
0072     int retries  = 0;
0073     int satreg, satidx;
0074 
0075     satreg = stream_number >> 1;
0076     satidx = stream_number & 1;
0077 
0078     temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset);
0079 
0080     val = NI_DP_MSE_SAT_SLOT_COUNT0(slots) | NI_DP_MSE_SAT_SRC0(fe);
0081 
0082     val <<= (16 * satidx);
0083 
0084     temp &= ~(0xffff << (16 * satidx));
0085 
0086     temp |= val;
0087 
0088     DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
0089     WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
0090 
0091     WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1);
0092 
0093     do {
0094         unsigned value1, value2;
0095         udelay(10);
0096         temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset);
0097 
0098         value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK;
0099         value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT;
0100 
0101         if (!value1 && !value2)
0102             break;
0103     } while (retries++ < 50);
0104 
0105     if (retries == 10000)
0106         DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset);
0107 
0108     /* MTP 16 ? */
0109     return 0;
0110 }
0111 
0112 static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn,
0113                            struct radeon_encoder *primary)
0114 {
0115     struct drm_device *dev = mst_conn->base.dev;
0116     struct stream_attribs new_attribs[6];
0117     int i;
0118     int idx = 0;
0119     struct radeon_connector *radeon_connector;
0120     struct drm_connector *connector;
0121 
0122     memset(new_attribs, 0, sizeof(new_attribs));
0123     list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
0124         struct radeon_encoder *subenc;
0125         struct radeon_encoder_mst *mst_enc;
0126 
0127         radeon_connector = to_radeon_connector(connector);
0128         if (!radeon_connector->is_mst_connector)
0129             continue;
0130 
0131         if (radeon_connector->mst_port != mst_conn)
0132             continue;
0133 
0134         subenc = radeon_connector->mst_encoder;
0135         mst_enc = subenc->enc_priv;
0136 
0137         if (!mst_enc->enc_active)
0138             continue;
0139 
0140         new_attribs[idx].fe = mst_enc->fe;
0141         new_attribs[idx].slots = drm_dp_mst_get_vcpi_slots(&mst_conn->mst_mgr, mst_enc->port);
0142         idx++;
0143     }
0144 
0145     for (i = 0; i < idx; i++) {
0146         if (new_attribs[i].fe != mst_conn->cur_stream_attribs[i].fe ||
0147             new_attribs[i].slots != mst_conn->cur_stream_attribs[i].slots) {
0148             radeon_dp_mst_set_stream_attrib(primary, i, new_attribs[i].fe, new_attribs[i].slots);
0149             mst_conn->cur_stream_attribs[i].fe = new_attribs[i].fe;
0150             mst_conn->cur_stream_attribs[i].slots = new_attribs[i].slots;
0151         }
0152     }
0153 
0154     for (i = idx; i < mst_conn->enabled_attribs; i++) {
0155         radeon_dp_mst_set_stream_attrib(primary, i, 0, 0);
0156         mst_conn->cur_stream_attribs[i].fe = 0;
0157         mst_conn->cur_stream_attribs[i].slots = 0;
0158     }
0159     mst_conn->enabled_attribs = idx;
0160     return 0;
0161 }
0162 
0163 static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp)
0164 {
0165     struct drm_device *dev = mst->base.dev;
0166     struct radeon_device *rdev = dev->dev_private;
0167     struct radeon_encoder_mst *mst_enc = mst->enc_priv;
0168     uint32_t val, temp;
0169     uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
0170     int retries = 0;
0171     uint32_t x = drm_fixp2int(avg_time_slots_per_mtp);
0172     uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26);
0173 
0174     val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y);
0175 
0176     WREG32(NI_DP_MSE_RATE_CNTL + offset, val);
0177 
0178     do {
0179         temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset);
0180         udelay(10);
0181     } while ((temp & 0x1) && (retries++ < 10000));
0182 
0183     if (retries >= 10000)
0184         DRM_ERROR("timed out wait for rate cntl %d\n", mst_enc->fe);
0185     return 0;
0186 }
0187 
0188 static int radeon_dp_mst_get_ddc_modes(struct drm_connector *connector)
0189 {
0190     struct radeon_connector *radeon_connector = to_radeon_connector(connector);
0191     struct radeon_connector *master = radeon_connector->mst_port;
0192     struct edid *edid;
0193     int ret = 0;
0194 
0195     edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, radeon_connector->port);
0196     radeon_connector->edid = edid;
0197     DRM_DEBUG_KMS("edid retrieved %p\n", edid);
0198     if (radeon_connector->edid) {
0199         drm_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
0200         ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
0201         return ret;
0202     }
0203     drm_connector_update_edid_property(&radeon_connector->base, NULL);
0204 
0205     return ret;
0206 }
0207 
0208 static int radeon_dp_mst_get_modes(struct drm_connector *connector)
0209 {
0210     return radeon_dp_mst_get_ddc_modes(connector);
0211 }
0212 
0213 static enum drm_mode_status
0214 radeon_dp_mst_mode_valid(struct drm_connector *connector,
0215             struct drm_display_mode *mode)
0216 {
0217     /* TODO - validate mode against available PBN for link */
0218     if (mode->clock < 10000)
0219         return MODE_CLOCK_LOW;
0220 
0221     if (mode->flags & DRM_MODE_FLAG_DBLCLK)
0222         return MODE_H_ILLEGAL;
0223 
0224     return MODE_OK;
0225 }
0226 
0227 static struct
0228 drm_encoder *radeon_mst_best_encoder(struct drm_connector *connector)
0229 {
0230     struct radeon_connector *radeon_connector = to_radeon_connector(connector);
0231 
0232     return &radeon_connector->mst_encoder->base;
0233 }
0234 
0235 static int
0236 radeon_dp_mst_detect(struct drm_connector *connector,
0237              struct drm_modeset_acquire_ctx *ctx,
0238              bool force)
0239 {
0240     struct radeon_connector *radeon_connector =
0241         to_radeon_connector(connector);
0242     struct radeon_connector *master = radeon_connector->mst_port;
0243 
0244     if (drm_connector_is_unregistered(connector))
0245         return connector_status_disconnected;
0246 
0247     return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
0248                       radeon_connector->port);
0249 }
0250 
0251 static const struct drm_connector_helper_funcs radeon_dp_mst_connector_helper_funcs = {
0252     .get_modes = radeon_dp_mst_get_modes,
0253     .mode_valid = radeon_dp_mst_mode_valid,
0254     .best_encoder = radeon_mst_best_encoder,
0255     .detect_ctx = radeon_dp_mst_detect,
0256 };
0257 
0258 static void
0259 radeon_dp_mst_connector_destroy(struct drm_connector *connector)
0260 {
0261     struct radeon_connector *radeon_connector = to_radeon_connector(connector);
0262     struct radeon_encoder *radeon_encoder = radeon_connector->mst_encoder;
0263 
0264     drm_encoder_cleanup(&radeon_encoder->base);
0265     kfree(radeon_encoder);
0266     drm_connector_cleanup(connector);
0267     kfree(radeon_connector);
0268 }
0269 
0270 static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = {
0271     .dpms = drm_helper_connector_dpms,
0272     .fill_modes = drm_helper_probe_single_connector_modes,
0273     .destroy = radeon_dp_mst_connector_destroy,
0274 };
0275 
0276 static struct drm_connector *radeon_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
0277                              struct drm_dp_mst_port *port,
0278                              const char *pathprop)
0279 {
0280     struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
0281     struct drm_device *dev = master->base.dev;
0282     struct radeon_connector *radeon_connector;
0283     struct drm_connector *connector;
0284 
0285     radeon_connector = kzalloc(sizeof(*radeon_connector), GFP_KERNEL);
0286     if (!radeon_connector)
0287         return NULL;
0288 
0289     radeon_connector->is_mst_connector = true;
0290     connector = &radeon_connector->base;
0291     radeon_connector->port = port;
0292     radeon_connector->mst_port = master;
0293     DRM_DEBUG_KMS("\n");
0294 
0295     drm_connector_init(dev, connector, &radeon_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort);
0296     drm_connector_helper_add(connector, &radeon_dp_mst_connector_helper_funcs);
0297     radeon_connector->mst_encoder = radeon_dp_create_fake_mst_encoder(master);
0298 
0299     drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0);
0300     drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0);
0301     drm_connector_set_path_property(connector, pathprop);
0302 
0303     return connector;
0304 }
0305 
0306 static const struct drm_dp_mst_topology_cbs mst_cbs = {
0307     .add_connector = radeon_dp_add_mst_connector,
0308 };
0309 
0310 static struct
0311 radeon_connector *radeon_mst_find_connector(struct drm_encoder *encoder)
0312 {
0313     struct drm_device *dev = encoder->dev;
0314     struct drm_connector *connector;
0315 
0316     list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
0317         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
0318         if (!connector->encoder)
0319             continue;
0320         if (!radeon_connector->is_mst_connector)
0321             continue;
0322 
0323         DRM_DEBUG_KMS("checking %p vs %p\n", connector->encoder, encoder);
0324         if (connector->encoder == encoder)
0325             return radeon_connector;
0326     }
0327     return NULL;
0328 }
0329 
0330 void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
0331 {
0332     struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
0333     struct drm_device *dev = crtc->dev;
0334     struct radeon_device *rdev = dev->dev_private;
0335     struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder);
0336     struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
0337     struct radeon_connector *radeon_connector = radeon_mst_find_connector(&radeon_encoder->base);
0338     int dp_clock;
0339     struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
0340 
0341     if (radeon_connector) {
0342         radeon_connector->pixelclock_for_modeset = mode->clock;
0343         if (radeon_connector->base.display_info.bpc)
0344             radeon_crtc->bpc = radeon_connector->base.display_info.bpc;
0345         else
0346             radeon_crtc->bpc = 8;
0347     }
0348 
0349     DRM_DEBUG_KMS("dp_clock %p %d\n", dig_connector, dig_connector->dp_clock);
0350     dp_clock = dig_connector->dp_clock;
0351     radeon_crtc->ss_enabled =
0352         radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
0353                          ASIC_INTERNAL_SS_ON_DP,
0354                          dp_clock);
0355 }
0356 
0357 static void
0358 radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
0359 {
0360     struct drm_device *dev = encoder->dev;
0361     struct radeon_device *rdev = dev->dev_private;
0362     struct radeon_encoder *radeon_encoder, *primary;
0363     struct radeon_encoder_mst *mst_enc;
0364     struct radeon_encoder_atom_dig *dig_enc;
0365     struct radeon_connector *radeon_connector;
0366     struct drm_crtc *crtc;
0367     struct radeon_crtc *radeon_crtc;
0368     int slots;
0369     s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp;
0370     if (!ASIC_IS_DCE5(rdev)) {
0371         DRM_ERROR("got mst dpms on non-DCE5\n");
0372         return;
0373     }
0374 
0375     radeon_connector = radeon_mst_find_connector(encoder);
0376     if (!radeon_connector)
0377         return;
0378 
0379     radeon_encoder = to_radeon_encoder(encoder);
0380 
0381     mst_enc = radeon_encoder->enc_priv;
0382 
0383     primary = mst_enc->primary;
0384 
0385     dig_enc = primary->enc_priv;
0386 
0387     crtc = encoder->crtc;
0388     DRM_DEBUG_KMS("got connector %d\n", dig_enc->active_mst_links);
0389 
0390     switch (mode) {
0391     case DRM_MODE_DPMS_ON:
0392         dig_enc->active_mst_links++;
0393 
0394         radeon_crtc = to_radeon_crtc(crtc);
0395 
0396         if (dig_enc->active_mst_links == 1) {
0397             mst_enc->fe = dig_enc->dig_encoder;
0398             mst_enc->fe_from_be = true;
0399             atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
0400 
0401             atombios_dig_encoder_setup(&primary->base, ATOM_ENCODER_CMD_SETUP, 0);
0402             atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE,
0403                             0, 0, dig_enc->dig_encoder);
0404 
0405             if (radeon_dp_needs_link_train(mst_enc->connector) ||
0406                 dig_enc->active_mst_links == 1) {
0407                 radeon_dp_link_train(&primary->base, &mst_enc->connector->base);
0408             }
0409 
0410         } else {
0411             mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id);
0412             if (mst_enc->fe == -1)
0413                 DRM_ERROR("failed to get frontend for dig encoder\n");
0414             mst_enc->fe_from_be = false;
0415             atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
0416         }
0417 
0418         DRM_DEBUG_KMS("dig encoder is %d %d %d\n", dig_enc->dig_encoder,
0419                   dig_enc->linkb, radeon_crtc->crtc_id);
0420 
0421         slots = drm_dp_find_vcpi_slots(&radeon_connector->mst_port->mst_mgr,
0422                            mst_enc->pbn);
0423         drm_dp_mst_allocate_vcpi(&radeon_connector->mst_port->mst_mgr,
0424                      radeon_connector->port,
0425                      mst_enc->pbn, slots);
0426         drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr, 1);
0427 
0428         radeon_dp_mst_set_be_cntl(primary, mst_enc,
0429                       radeon_connector->mst_port->hpd.hpd, true);
0430 
0431         mst_enc->enc_active = true;
0432         radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
0433 
0434         fixed_pbn = drm_int2fixp(mst_enc->pbn);
0435         fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div);
0436         avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot);
0437         radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp);
0438 
0439         atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0,
0440                         mst_enc->fe);
0441         drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
0442 
0443         drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
0444 
0445         break;
0446     case DRM_MODE_DPMS_STANDBY:
0447     case DRM_MODE_DPMS_SUSPEND:
0448     case DRM_MODE_DPMS_OFF:
0449         DRM_ERROR("DPMS OFF %d\n", dig_enc->active_mst_links);
0450 
0451         if (!mst_enc->enc_active)
0452             return;
0453 
0454         drm_dp_mst_reset_vcpi_slots(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
0455         drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr, 1);
0456 
0457         drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
0458         /* and this can also fail */
0459         drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
0460 
0461         drm_dp_mst_deallocate_vcpi(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
0462 
0463         mst_enc->enc_active = false;
0464         radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
0465 
0466         radeon_dp_mst_set_be_cntl(primary, mst_enc,
0467                       radeon_connector->mst_port->hpd.hpd, false);
0468         atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0,
0469                         mst_enc->fe);
0470 
0471         if (!mst_enc->fe_from_be)
0472             radeon_atom_release_dig_encoder(rdev, mst_enc->fe);
0473 
0474         mst_enc->fe_from_be = false;
0475         dig_enc->active_mst_links--;
0476         if (dig_enc->active_mst_links == 0) {
0477             /* drop link */
0478         }
0479 
0480         break;
0481     }
0482 
0483 }
0484 
0485 static bool radeon_mst_mode_fixup(struct drm_encoder *encoder,
0486                    const struct drm_display_mode *mode,
0487                    struct drm_display_mode *adjusted_mode)
0488 {
0489     struct radeon_encoder_mst *mst_enc;
0490     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
0491     struct radeon_connector_atom_dig *dig_connector;
0492     int bpp = 24;
0493 
0494     mst_enc = radeon_encoder->enc_priv;
0495 
0496     mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp, false);
0497 
0498     mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices;
0499     DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
0500               mst_enc->primary->active_device, mst_enc->primary->devices,
0501               mst_enc->connector->devices, mst_enc->primary->base.encoder_type);
0502 
0503 
0504     drm_mode_set_crtcinfo(adjusted_mode, 0);
0505     dig_connector = mst_enc->connector->con_priv;
0506     dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd);
0507     dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd);
0508     DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector,
0509               dig_connector->dp_lane_count, dig_connector->dp_clock);
0510     return true;
0511 }
0512 
0513 static void radeon_mst_encoder_prepare(struct drm_encoder *encoder)
0514 {
0515     struct radeon_connector *radeon_connector;
0516     struct radeon_encoder *radeon_encoder, *primary;
0517     struct radeon_encoder_mst *mst_enc;
0518     struct radeon_encoder_atom_dig *dig_enc;
0519 
0520     radeon_connector = radeon_mst_find_connector(encoder);
0521     if (!radeon_connector) {
0522         DRM_DEBUG_KMS("failed to find connector %p\n", encoder);
0523         return;
0524     }
0525     radeon_encoder = to_radeon_encoder(encoder);
0526 
0527     radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
0528 
0529     mst_enc = radeon_encoder->enc_priv;
0530 
0531     primary = mst_enc->primary;
0532 
0533     dig_enc = primary->enc_priv;
0534 
0535     mst_enc->port = radeon_connector->port;
0536 
0537     if (dig_enc->dig_encoder == -1) {
0538         dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1);
0539         primary->offset = radeon_atom_set_enc_offset(dig_enc->dig_encoder);
0540         atombios_set_mst_encoder_crtc_source(encoder, dig_enc->dig_encoder);
0541 
0542 
0543     }
0544     DRM_DEBUG_KMS("%d %d\n", dig_enc->dig_encoder, primary->offset);
0545 }
0546 
0547 static void
0548 radeon_mst_encoder_mode_set(struct drm_encoder *encoder,
0549                  struct drm_display_mode *mode,
0550                  struct drm_display_mode *adjusted_mode)
0551 {
0552     DRM_DEBUG_KMS("\n");
0553 }
0554 
0555 static void radeon_mst_encoder_commit(struct drm_encoder *encoder)
0556 {
0557     radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
0558     DRM_DEBUG_KMS("\n");
0559 }
0560 
0561 static const struct drm_encoder_helper_funcs radeon_mst_helper_funcs = {
0562     .dpms = radeon_mst_encoder_dpms,
0563     .mode_fixup = radeon_mst_mode_fixup,
0564     .prepare = radeon_mst_encoder_prepare,
0565     .mode_set = radeon_mst_encoder_mode_set,
0566     .commit = radeon_mst_encoder_commit,
0567 };
0568 
0569 static void radeon_dp_mst_encoder_destroy(struct drm_encoder *encoder)
0570 {
0571     drm_encoder_cleanup(encoder);
0572     kfree(encoder);
0573 }
0574 
0575 static const struct drm_encoder_funcs radeon_dp_mst_enc_funcs = {
0576     .destroy = radeon_dp_mst_encoder_destroy,
0577 };
0578 
0579 static struct radeon_encoder *
0580 radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector)
0581 {
0582     struct drm_device *dev = connector->base.dev;
0583     struct radeon_device *rdev = dev->dev_private;
0584     struct radeon_encoder *radeon_encoder;
0585     struct radeon_encoder_mst *mst_enc;
0586     struct drm_encoder *encoder;
0587     const struct drm_connector_helper_funcs *connector_funcs = connector->base.helper_private;
0588     struct drm_encoder *enc_master = connector_funcs->best_encoder(&connector->base);
0589 
0590     DRM_DEBUG_KMS("enc master is %p\n", enc_master);
0591     radeon_encoder = kzalloc(sizeof(*radeon_encoder), GFP_KERNEL);
0592     if (!radeon_encoder)
0593         return NULL;
0594 
0595     radeon_encoder->enc_priv = kzalloc(sizeof(*mst_enc), GFP_KERNEL);
0596     if (!radeon_encoder->enc_priv) {
0597         kfree(radeon_encoder);
0598         return NULL;
0599     }
0600     encoder = &radeon_encoder->base;
0601     switch (rdev->num_crtc) {
0602     case 1:
0603         encoder->possible_crtcs = 0x1;
0604         break;
0605     case 2:
0606     default:
0607         encoder->possible_crtcs = 0x3;
0608         break;
0609     case 4:
0610         encoder->possible_crtcs = 0xf;
0611         break;
0612     case 6:
0613         encoder->possible_crtcs = 0x3f;
0614         break;
0615     }
0616 
0617     drm_encoder_init(dev, &radeon_encoder->base, &radeon_dp_mst_enc_funcs,
0618              DRM_MODE_ENCODER_DPMST, NULL);
0619     drm_encoder_helper_add(encoder, &radeon_mst_helper_funcs);
0620 
0621     mst_enc = radeon_encoder->enc_priv;
0622     mst_enc->connector = connector;
0623     mst_enc->primary = to_radeon_encoder(enc_master);
0624     radeon_encoder->is_mst_encoder = true;
0625     return radeon_encoder;
0626 }
0627 
0628 int
0629 radeon_dp_mst_init(struct radeon_connector *radeon_connector)
0630 {
0631     struct drm_device *dev = radeon_connector->base.dev;
0632     int max_link_rate;
0633 
0634     if (!radeon_connector->ddc_bus->has_aux)
0635         return 0;
0636 
0637     if (radeon_connector_is_dp12_capable(&radeon_connector->base))
0638         max_link_rate = 0x14;
0639     else
0640         max_link_rate = 0x0a;
0641 
0642     radeon_connector->mst_mgr.cbs = &mst_cbs;
0643     return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev,
0644                         &radeon_connector->ddc_bus->aux, 16, 6,
0645                         4, drm_dp_bw_code_to_link_rate(max_link_rate),
0646                         radeon_connector->base.base.id);
0647 }
0648 
0649 int
0650 radeon_dp_mst_probe(struct radeon_connector *radeon_connector)
0651 {
0652     struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
0653     struct drm_device *dev = radeon_connector->base.dev;
0654     struct radeon_device *rdev = dev->dev_private;
0655     int ret;
0656     u8 msg[1];
0657 
0658     if (!radeon_mst)
0659         return 0;
0660 
0661     if (!ASIC_IS_DCE5(rdev))
0662         return 0;
0663 
0664     if (dig_connector->dpcd[DP_DPCD_REV] < 0x12)
0665         return 0;
0666 
0667     ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_MSTM_CAP, msg,
0668                    1);
0669     if (ret) {
0670         if (msg[0] & DP_MST_CAP) {
0671             DRM_DEBUG_KMS("Sink is MST capable\n");
0672             dig_connector->is_mst = true;
0673         } else {
0674             DRM_DEBUG_KMS("Sink is not MST capable\n");
0675             dig_connector->is_mst = false;
0676         }
0677 
0678     }
0679     drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
0680                     dig_connector->is_mst);
0681     return dig_connector->is_mst;
0682 }
0683 
0684 int
0685 radeon_dp_mst_check_status(struct radeon_connector *radeon_connector)
0686 {
0687     struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
0688     int retry;
0689 
0690     if (dig_connector->is_mst) {
0691         u8 esi[16] = { 0 };
0692         int dret;
0693         int ret = 0;
0694         bool handled;
0695 
0696         dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
0697                        DP_SINK_COUNT_ESI, esi, 8);
0698 go_again:
0699         if (dret == 8) {
0700             DRM_DEBUG_KMS("got esi %3ph\n", esi);
0701             ret = drm_dp_mst_hpd_irq(&radeon_connector->mst_mgr, esi, &handled);
0702 
0703             if (handled) {
0704                 for (retry = 0; retry < 3; retry++) {
0705                     int wret;
0706                     wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux,
0707                                  DP_SINK_COUNT_ESI + 1, &esi[1], 3);
0708                     if (wret == 3)
0709                         break;
0710                 }
0711 
0712                 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
0713                             DP_SINK_COUNT_ESI, esi, 8);
0714                 if (dret == 8) {
0715                     DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0716                     goto go_again;
0717                 }
0718             } else
0719                 ret = 0;
0720 
0721             return ret;
0722         } else {
0723             DRM_DEBUG_KMS("failed to get ESI - device may have failed %d\n", ret);
0724             dig_connector->is_mst = false;
0725             drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
0726                             dig_connector->is_mst);
0727             /* send a hotplug event */
0728         }
0729     }
0730     return -EINVAL;
0731 }
0732 
0733 #if defined(CONFIG_DEBUG_FS)
0734 
0735 static int radeon_debugfs_mst_info_show(struct seq_file *m, void *unused)
0736 {
0737     struct radeon_device *rdev = (struct radeon_device *)m->private;
0738     struct drm_device *dev = rdev->ddev;
0739     struct drm_connector *connector;
0740     struct radeon_connector *radeon_connector;
0741     struct radeon_connector_atom_dig *dig_connector;
0742     int i;
0743 
0744     drm_modeset_lock_all(dev);
0745     list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
0746         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
0747             continue;
0748 
0749         radeon_connector = to_radeon_connector(connector);
0750         dig_connector = radeon_connector->con_priv;
0751         if (radeon_connector->is_mst_connector)
0752             continue;
0753         if (!dig_connector->is_mst)
0754             continue;
0755         drm_dp_mst_dump_topology(m, &radeon_connector->mst_mgr);
0756 
0757         for (i = 0; i < radeon_connector->enabled_attribs; i++)
0758             seq_printf(m, "attrib %d: %d %d\n", i,
0759                    radeon_connector->cur_stream_attribs[i].fe,
0760                    radeon_connector->cur_stream_attribs[i].slots);
0761     }
0762     drm_modeset_unlock_all(dev);
0763     return 0;
0764 }
0765 
0766 DEFINE_SHOW_ATTRIBUTE(radeon_debugfs_mst_info);
0767 #endif
0768 
0769 void radeon_mst_debugfs_init(struct radeon_device *rdev)
0770 {
0771 #if defined(CONFIG_DEBUG_FS)
0772     struct dentry *root = rdev->ddev->primary->debugfs_root;
0773 
0774     debugfs_create_file("radeon_mst_info", 0444, root, rdev,
0775                 &radeon_debugfs_mst_info_fops);
0776 
0777 #endif
0778 }
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