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0001 /*
0002  * Copyright 2007-8 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors: Dave Airlie
0024  *          Alex Deucher
0025  */
0026 
0027 #include <linux/pci.h>
0028 #include <linux/pm_runtime.h>
0029 #include <linux/gcd.h>
0030 
0031 #include <asm/div64.h>
0032 
0033 #include <drm/drm_crtc_helper.h>
0034 #include <drm/drm_device.h>
0035 #include <drm/drm_drv.h>
0036 #include <drm/drm_edid.h>
0037 #include <drm/drm_fb_helper.h>
0038 #include <drm/drm_fourcc.h>
0039 #include <drm/drm_framebuffer.h>
0040 #include <drm/drm_gem_framebuffer_helper.h>
0041 #include <drm/drm_plane_helper.h>
0042 #include <drm/drm_probe_helper.h>
0043 #include <drm/drm_vblank.h>
0044 #include <drm/radeon_drm.h>
0045 
0046 #include "atom.h"
0047 #include "radeon.h"
0048 #include "radeon_kms.h"
0049 
0050 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
0051 {
0052     struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
0053     struct drm_device *dev = crtc->dev;
0054     struct radeon_device *rdev = dev->dev_private;
0055     u16 *r, *g, *b;
0056     int i;
0057 
0058     DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
0059     WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
0060 
0061     WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
0062     WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
0063     WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
0064 
0065     WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
0066     WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
0067     WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
0068 
0069     WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
0070     WREG32(AVIVO_DC_LUT_RW_MODE, 0);
0071     WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
0072 
0073     WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
0074     r = crtc->gamma_store;
0075     g = r + crtc->gamma_size;
0076     b = g + crtc->gamma_size;
0077     for (i = 0; i < 256; i++) {
0078         WREG32(AVIVO_DC_LUT_30_COLOR,
0079                ((*r++ & 0xffc0) << 14) |
0080                ((*g++ & 0xffc0) << 4) |
0081                (*b++ >> 6));
0082     }
0083 
0084     /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
0085     WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
0086 }
0087 
0088 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
0089 {
0090     struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
0091     struct drm_device *dev = crtc->dev;
0092     struct radeon_device *rdev = dev->dev_private;
0093     u16 *r, *g, *b;
0094     int i;
0095 
0096     DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
0097     WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
0098 
0099     WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
0100     WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
0101     WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
0102 
0103     WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
0104     WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
0105     WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
0106 
0107     WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
0108     WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
0109 
0110     WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
0111     r = crtc->gamma_store;
0112     g = r + crtc->gamma_size;
0113     b = g + crtc->gamma_size;
0114     for (i = 0; i < 256; i++) {
0115         WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
0116                ((*r++ & 0xffc0) << 14) |
0117                ((*g++ & 0xffc0) << 4) |
0118                (*b++ >> 6));
0119     }
0120 }
0121 
0122 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
0123 {
0124     struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
0125     struct drm_device *dev = crtc->dev;
0126     struct radeon_device *rdev = dev->dev_private;
0127     u16 *r, *g, *b;
0128     int i;
0129 
0130     DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
0131 
0132     msleep(10);
0133 
0134     WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
0135            (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
0136         NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
0137     WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
0138            NI_GRPH_PRESCALE_BYPASS);
0139     WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
0140            NI_OVL_PRESCALE_BYPASS);
0141     WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
0142            (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
0143         NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
0144 
0145     WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
0146 
0147     WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
0148     WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
0149     WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
0150 
0151     WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
0152     WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
0153     WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
0154 
0155     WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
0156     WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
0157 
0158     WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
0159     r = crtc->gamma_store;
0160     g = r + crtc->gamma_size;
0161     b = g + crtc->gamma_size;
0162     for (i = 0; i < 256; i++) {
0163         WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
0164                ((*r++ & 0xffc0) << 14) |
0165                ((*g++ & 0xffc0) << 4) |
0166                (*b++ >> 6));
0167     }
0168 
0169     WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
0170            (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
0171         NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
0172         NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
0173         NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
0174     WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
0175            (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
0176         NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
0177     WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
0178            (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
0179         NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
0180     WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
0181            (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
0182         NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
0183     /* XXX match this to the depth of the crtc fmt block, move to modeset? */
0184     WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
0185     if (ASIC_IS_DCE8(rdev)) {
0186         /* XXX this only needs to be programmed once per crtc at startup,
0187          * not sure where the best place for it is
0188          */
0189         WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
0190                CIK_CURSOR_ALPHA_BLND_ENA);
0191     }
0192 }
0193 
0194 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
0195 {
0196     struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
0197     struct drm_device *dev = crtc->dev;
0198     struct radeon_device *rdev = dev->dev_private;
0199     u16 *r, *g, *b;
0200     int i;
0201     uint32_t dac2_cntl;
0202 
0203     dac2_cntl = RREG32(RADEON_DAC_CNTL2);
0204     if (radeon_crtc->crtc_id == 0)
0205         dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
0206     else
0207         dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
0208     WREG32(RADEON_DAC_CNTL2, dac2_cntl);
0209 
0210     WREG8(RADEON_PALETTE_INDEX, 0);
0211     r = crtc->gamma_store;
0212     g = r + crtc->gamma_size;
0213     b = g + crtc->gamma_size;
0214     for (i = 0; i < 256; i++) {
0215         WREG32(RADEON_PALETTE_30_DATA,
0216                ((*r++ & 0xffc0) << 14) |
0217                ((*g++ & 0xffc0) << 4) |
0218                (*b++ >> 6));
0219     }
0220 }
0221 
0222 void radeon_crtc_load_lut(struct drm_crtc *crtc)
0223 {
0224     struct drm_device *dev = crtc->dev;
0225     struct radeon_device *rdev = dev->dev_private;
0226 
0227     if (!crtc->enabled)
0228         return;
0229 
0230     if (ASIC_IS_DCE5(rdev))
0231         dce5_crtc_load_lut(crtc);
0232     else if (ASIC_IS_DCE4(rdev))
0233         dce4_crtc_load_lut(crtc);
0234     else if (ASIC_IS_AVIVO(rdev))
0235         avivo_crtc_load_lut(crtc);
0236     else
0237         legacy_crtc_load_lut(crtc);
0238 }
0239 
0240 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
0241                  u16 *blue, uint32_t size,
0242                  struct drm_modeset_acquire_ctx *ctx)
0243 {
0244     radeon_crtc_load_lut(crtc);
0245 
0246     return 0;
0247 }
0248 
0249 static void radeon_crtc_destroy(struct drm_crtc *crtc)
0250 {
0251     struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
0252 
0253     drm_crtc_cleanup(crtc);
0254     destroy_workqueue(radeon_crtc->flip_queue);
0255     kfree(radeon_crtc);
0256 }
0257 
0258 /**
0259  * radeon_unpin_work_func - unpin old buffer object
0260  *
0261  * @__work: kernel work item
0262  *
0263  * Unpin the old frame buffer object outside of the interrupt handler
0264  */
0265 static void radeon_unpin_work_func(struct work_struct *__work)
0266 {
0267     struct radeon_flip_work *work =
0268         container_of(__work, struct radeon_flip_work, unpin_work);
0269     int r;
0270 
0271     /* unpin of the old buffer */
0272     r = radeon_bo_reserve(work->old_rbo, false);
0273     if (likely(r == 0)) {
0274         radeon_bo_unpin(work->old_rbo);
0275         radeon_bo_unreserve(work->old_rbo);
0276     } else
0277         DRM_ERROR("failed to reserve buffer after flip\n");
0278 
0279     drm_gem_object_put(&work->old_rbo->tbo.base);
0280     kfree(work);
0281 }
0282 
0283 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
0284 {
0285     struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
0286     unsigned long flags;
0287     u32 update_pending;
0288     int vpos, hpos;
0289 
0290     /* can happen during initialization */
0291     if (radeon_crtc == NULL)
0292         return;
0293 
0294     /* Skip the pageflip completion check below (based on polling) on
0295      * asics which reliably support hw pageflip completion irqs. pflip
0296      * irqs are a reliable and race-free method of handling pageflip
0297      * completion detection. A use_pflipirq module parameter < 2 allows
0298      * to override this in case of asics with faulty pflip irqs.
0299      * A module parameter of 0 would only use this polling based path,
0300      * a parameter of 1 would use pflip irq only as a backup to this
0301      * path, as in Linux 3.16.
0302      */
0303     if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
0304         return;
0305 
0306     spin_lock_irqsave(&rdev->ddev->event_lock, flags);
0307     if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
0308         DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
0309                  "RADEON_FLIP_SUBMITTED(%d)\n",
0310                  radeon_crtc->flip_status,
0311                  RADEON_FLIP_SUBMITTED);
0312         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
0313         return;
0314     }
0315 
0316     update_pending = radeon_page_flip_pending(rdev, crtc_id);
0317 
0318     /* Has the pageflip already completed in crtc, or is it certain
0319      * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides
0320      * distance to start of "fudged earlier" vblank in vpos, distance to
0321      * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in
0322      * the last few scanlines before start of real vblank, where the vblank
0323      * irq can fire, so we have sampled update_pending a bit too early and
0324      * know the flip will complete at leading edge of the upcoming real
0325      * vblank. On pre-AVIVO hardware, flips also complete inside the real
0326      * vblank, not only at leading edge, so if update_pending for hpos >= 0
0327      *  == inside real vblank, the flip will complete almost immediately.
0328      * Note that this method of completion handling is still not 100% race
0329      * free, as we could execute before the radeon_flip_work_func managed
0330      * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op,
0331      * but the flip still gets programmed into hw and completed during
0332      * vblank, leading to a delayed emission of the flip completion event.
0333      * This applies at least to pre-AVIVO hardware, where flips are always
0334      * completing inside vblank, not only at leading edge of vblank.
0335      */
0336     if (update_pending &&
0337         (DRM_SCANOUTPOS_VALID &
0338          radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
0339                     GET_DISTANCE_TO_VBLANKSTART,
0340                     &vpos, &hpos, NULL, NULL,
0341                     &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
0342         ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) {
0343         /* crtc didn't flip in this target vblank interval,
0344          * but flip is pending in crtc. Based on the current
0345          * scanout position we know that the current frame is
0346          * (nearly) complete and the flip will (likely)
0347          * complete before the start of the next frame.
0348          */
0349         update_pending = 0;
0350     }
0351     spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
0352     if (!update_pending)
0353         radeon_crtc_handle_flip(rdev, crtc_id);
0354 }
0355 
0356 /**
0357  * radeon_crtc_handle_flip - page flip completed
0358  *
0359  * @rdev: radeon device pointer
0360  * @crtc_id: crtc number this event is for
0361  *
0362  * Called when we are sure that a page flip for this crtc is completed.
0363  */
0364 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
0365 {
0366     struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
0367     struct radeon_flip_work *work;
0368     unsigned long flags;
0369 
0370     /* this can happen at init */
0371     if (radeon_crtc == NULL)
0372         return;
0373 
0374     spin_lock_irqsave(&rdev->ddev->event_lock, flags);
0375     work = radeon_crtc->flip_work;
0376     if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
0377         DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
0378                  "RADEON_FLIP_SUBMITTED(%d)\n",
0379                  radeon_crtc->flip_status,
0380                  RADEON_FLIP_SUBMITTED);
0381         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
0382         return;
0383     }
0384 
0385     /* Pageflip completed. Clean up. */
0386     radeon_crtc->flip_status = RADEON_FLIP_NONE;
0387     radeon_crtc->flip_work = NULL;
0388 
0389     /* wakeup userspace */
0390     if (work->event)
0391         drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);
0392 
0393     spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
0394 
0395     drm_crtc_vblank_put(&radeon_crtc->base);
0396     radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
0397     queue_work(radeon_crtc->flip_queue, &work->unpin_work);
0398 }
0399 
0400 /**
0401  * radeon_flip_work_func - page flip framebuffer
0402  *
0403  * @__work: kernel work item
0404  *
0405  * Wait for the buffer object to become idle and do the actual page flip
0406  */
0407 static void radeon_flip_work_func(struct work_struct *__work)
0408 {
0409     struct radeon_flip_work *work =
0410         container_of(__work, struct radeon_flip_work, flip_work);
0411     struct radeon_device *rdev = work->rdev;
0412     struct drm_device *dev = rdev->ddev;
0413     struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
0414 
0415     struct drm_crtc *crtc = &radeon_crtc->base;
0416     unsigned long flags;
0417     int r;
0418     int vpos, hpos;
0419 
0420     down_read(&rdev->exclusive_lock);
0421     if (work->fence) {
0422         struct radeon_fence *fence;
0423 
0424         fence = to_radeon_fence(work->fence);
0425         if (fence && fence->rdev == rdev) {
0426             r = radeon_fence_wait(fence, false);
0427             if (r == -EDEADLK) {
0428                 up_read(&rdev->exclusive_lock);
0429                 do {
0430                     r = radeon_gpu_reset(rdev);
0431                 } while (r == -EAGAIN);
0432                 down_read(&rdev->exclusive_lock);
0433             }
0434         } else
0435             r = dma_fence_wait(work->fence, false);
0436 
0437         if (r)
0438             DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
0439 
0440         /* We continue with the page flip even if we failed to wait on
0441          * the fence, otherwise the DRM core and userspace will be
0442          * confused about which BO the CRTC is scanning out
0443          */
0444 
0445         dma_fence_put(work->fence);
0446         work->fence = NULL;
0447     }
0448 
0449     /* Wait until we're out of the vertical blank period before the one
0450      * targeted by the flip. Always wait on pre DCE4 to avoid races with
0451      * flip completion handling from vblank irq, as these old asics don't
0452      * have reliable pageflip completion interrupts.
0453      */
0454     while (radeon_crtc->enabled &&
0455         (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0,
0456                         &vpos, &hpos, NULL, NULL,
0457                         &crtc->hwmode)
0458         & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
0459         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
0460         (!ASIC_IS_AVIVO(rdev) ||
0461         ((int) (work->target_vblank -
0462         crtc->funcs->get_vblank_counter(crtc)) > 0)))
0463         usleep_range(1000, 2000);
0464 
0465     /* We borrow the event spin lock for protecting flip_status */
0466     spin_lock_irqsave(&crtc->dev->event_lock, flags);
0467 
0468     /* set the proper interrupt */
0469     radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
0470 
0471     /* do the flip (mmio) */
0472     radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);
0473 
0474     radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
0475     spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
0476     up_read(&rdev->exclusive_lock);
0477 }
0478 
0479 static int radeon_crtc_page_flip_target(struct drm_crtc *crtc,
0480                     struct drm_framebuffer *fb,
0481                     struct drm_pending_vblank_event *event,
0482                     uint32_t page_flip_flags,
0483                     uint32_t target,
0484                     struct drm_modeset_acquire_ctx *ctx)
0485 {
0486     struct drm_device *dev = crtc->dev;
0487     struct radeon_device *rdev = dev->dev_private;
0488     struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
0489     struct drm_gem_object *obj;
0490     struct radeon_flip_work *work;
0491     struct radeon_bo *new_rbo;
0492     uint32_t tiling_flags, pitch_pixels;
0493     uint64_t base;
0494     unsigned long flags;
0495     int r;
0496 
0497     work = kzalloc(sizeof *work, GFP_KERNEL);
0498     if (work == NULL)
0499         return -ENOMEM;
0500 
0501     INIT_WORK(&work->flip_work, radeon_flip_work_func);
0502     INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
0503 
0504     work->rdev = rdev;
0505     work->crtc_id = radeon_crtc->crtc_id;
0506     work->event = event;
0507     work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
0508 
0509     /* schedule unpin of the old buffer */
0510     obj = crtc->primary->fb->obj[0];
0511 
0512     /* take a reference to the old object */
0513     drm_gem_object_get(obj);
0514     work->old_rbo = gem_to_radeon_bo(obj);
0515 
0516     obj = fb->obj[0];
0517     new_rbo = gem_to_radeon_bo(obj);
0518 
0519     /* pin the new buffer */
0520     DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
0521              work->old_rbo, new_rbo);
0522 
0523     r = radeon_bo_reserve(new_rbo, false);
0524     if (unlikely(r != 0)) {
0525         DRM_ERROR("failed to reserve new rbo buffer before flip\n");
0526         goto cleanup;
0527     }
0528     /* Only 27 bit offset for legacy CRTC */
0529     r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
0530                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
0531     if (unlikely(r != 0)) {
0532         radeon_bo_unreserve(new_rbo);
0533         r = -EINVAL;
0534         DRM_ERROR("failed to pin new rbo buffer before flip\n");
0535         goto cleanup;
0536     }
0537     r = dma_resv_get_singleton(new_rbo->tbo.base.resv, DMA_RESV_USAGE_WRITE,
0538                    &work->fence);
0539     if (r) {
0540         radeon_bo_unreserve(new_rbo);
0541         DRM_ERROR("failed to get new rbo buffer fences\n");
0542         goto cleanup;
0543     }
0544     radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
0545     radeon_bo_unreserve(new_rbo);
0546 
0547     if (!ASIC_IS_AVIVO(rdev)) {
0548         /* crtc offset is from display base addr not FB location */
0549         base -= radeon_crtc->legacy_display_base_addr;
0550         pitch_pixels = fb->pitches[0] / fb->format->cpp[0];
0551 
0552         if (tiling_flags & RADEON_TILING_MACRO) {
0553             if (ASIC_IS_R300(rdev)) {
0554                 base &= ~0x7ff;
0555             } else {
0556                 int byteshift = fb->format->cpp[0] * 8 >> 4;
0557                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
0558                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
0559             }
0560         } else {
0561             int offset = crtc->y * pitch_pixels + crtc->x;
0562             switch (fb->format->cpp[0] * 8) {
0563             case 8:
0564             default:
0565                 offset *= 1;
0566                 break;
0567             case 15:
0568             case 16:
0569                 offset *= 2;
0570                 break;
0571             case 24:
0572                 offset *= 3;
0573                 break;
0574             case 32:
0575                 offset *= 4;
0576                 break;
0577             }
0578             base += offset;
0579         }
0580         base &= ~7;
0581     }
0582     work->base = base;
0583     work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
0584         crtc->funcs->get_vblank_counter(crtc);
0585 
0586     /* We borrow the event spin lock for protecting flip_work */
0587     spin_lock_irqsave(&crtc->dev->event_lock, flags);
0588 
0589     if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
0590         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
0591         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
0592         r = -EBUSY;
0593         goto pflip_cleanup;
0594     }
0595     radeon_crtc->flip_status = RADEON_FLIP_PENDING;
0596     radeon_crtc->flip_work = work;
0597 
0598     /* update crtc fb */
0599     crtc->primary->fb = fb;
0600 
0601     spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
0602 
0603     queue_work(radeon_crtc->flip_queue, &work->flip_work);
0604     return 0;
0605 
0606 pflip_cleanup:
0607     if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
0608         DRM_ERROR("failed to reserve new rbo in error path\n");
0609         goto cleanup;
0610     }
0611     radeon_bo_unpin(new_rbo);
0612     radeon_bo_unreserve(new_rbo);
0613 
0614 cleanup:
0615     drm_gem_object_put(&work->old_rbo->tbo.base);
0616     dma_fence_put(work->fence);
0617     kfree(work);
0618     return r;
0619 }
0620 
0621 static int
0622 radeon_crtc_set_config(struct drm_mode_set *set,
0623                struct drm_modeset_acquire_ctx *ctx)
0624 {
0625     struct drm_device *dev;
0626     struct radeon_device *rdev;
0627     struct drm_crtc *crtc;
0628     bool active = false;
0629     int ret;
0630 
0631     if (!set || !set->crtc)
0632         return -EINVAL;
0633 
0634     dev = set->crtc->dev;
0635 
0636     ret = pm_runtime_get_sync(dev->dev);
0637     if (ret < 0) {
0638         pm_runtime_put_autosuspend(dev->dev);
0639         return ret;
0640     }
0641 
0642     ret = drm_crtc_helper_set_config(set, ctx);
0643 
0644     list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
0645         if (crtc->enabled)
0646             active = true;
0647 
0648     pm_runtime_mark_last_busy(dev->dev);
0649 
0650     rdev = dev->dev_private;
0651     /* if we have active crtcs and we don't have a power ref,
0652        take the current one */
0653     if (active && !rdev->have_disp_power_ref) {
0654         rdev->have_disp_power_ref = true;
0655         return ret;
0656     }
0657     /* if we have no active crtcs, then drop the power ref
0658        we got before */
0659     if (!active && rdev->have_disp_power_ref) {
0660         pm_runtime_put_autosuspend(dev->dev);
0661         rdev->have_disp_power_ref = false;
0662     }
0663 
0664     /* drop the power reference we got coming in here */
0665     pm_runtime_put_autosuspend(dev->dev);
0666     return ret;
0667 }
0668 
0669 static const struct drm_crtc_funcs radeon_crtc_funcs = {
0670     .cursor_set2 = radeon_crtc_cursor_set2,
0671     .cursor_move = radeon_crtc_cursor_move,
0672     .gamma_set = radeon_crtc_gamma_set,
0673     .set_config = radeon_crtc_set_config,
0674     .destroy = radeon_crtc_destroy,
0675     .page_flip_target = radeon_crtc_page_flip_target,
0676     .get_vblank_counter = radeon_get_vblank_counter_kms,
0677     .enable_vblank = radeon_enable_vblank_kms,
0678     .disable_vblank = radeon_disable_vblank_kms,
0679     .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
0680 };
0681 
0682 static void radeon_crtc_init(struct drm_device *dev, int index)
0683 {
0684     struct radeon_device *rdev = dev->dev_private;
0685     struct radeon_crtc *radeon_crtc;
0686 
0687     radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
0688     if (radeon_crtc == NULL)
0689         return;
0690 
0691     drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
0692 
0693     drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
0694     radeon_crtc->crtc_id = index;
0695     radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);
0696     rdev->mode_info.crtcs[index] = radeon_crtc;
0697 
0698     if (rdev->family >= CHIP_BONAIRE) {
0699         radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
0700         radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
0701     } else {
0702         radeon_crtc->max_cursor_width = CURSOR_WIDTH;
0703         radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
0704     }
0705     dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
0706     dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
0707 
0708 #if 0
0709     radeon_crtc->mode_set.crtc = &radeon_crtc->base;
0710     radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
0711     radeon_crtc->mode_set.num_connectors = 0;
0712 #endif
0713 
0714     if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
0715         radeon_atombios_init_crtc(dev, radeon_crtc);
0716     else
0717         radeon_legacy_init_crtc(dev, radeon_crtc);
0718 }
0719 
0720 static const char *encoder_names[38] = {
0721     "NONE",
0722     "INTERNAL_LVDS",
0723     "INTERNAL_TMDS1",
0724     "INTERNAL_TMDS2",
0725     "INTERNAL_DAC1",
0726     "INTERNAL_DAC2",
0727     "INTERNAL_SDVOA",
0728     "INTERNAL_SDVOB",
0729     "SI170B",
0730     "CH7303",
0731     "CH7301",
0732     "INTERNAL_DVO1",
0733     "EXTERNAL_SDVOA",
0734     "EXTERNAL_SDVOB",
0735     "TITFP513",
0736     "INTERNAL_LVTM1",
0737     "VT1623",
0738     "HDMI_SI1930",
0739     "HDMI_INTERNAL",
0740     "INTERNAL_KLDSCP_TMDS1",
0741     "INTERNAL_KLDSCP_DVO1",
0742     "INTERNAL_KLDSCP_DAC1",
0743     "INTERNAL_KLDSCP_DAC2",
0744     "SI178",
0745     "MVPU_FPGA",
0746     "INTERNAL_DDI",
0747     "VT1625",
0748     "HDMI_SI1932",
0749     "DP_AN9801",
0750     "DP_DP501",
0751     "INTERNAL_UNIPHY",
0752     "INTERNAL_KLDSCP_LVTMA",
0753     "INTERNAL_UNIPHY1",
0754     "INTERNAL_UNIPHY2",
0755     "NUTMEG",
0756     "TRAVIS",
0757     "INTERNAL_VCE",
0758     "INTERNAL_UNIPHY3",
0759 };
0760 
0761 static const char *hpd_names[6] = {
0762     "HPD1",
0763     "HPD2",
0764     "HPD3",
0765     "HPD4",
0766     "HPD5",
0767     "HPD6",
0768 };
0769 
0770 static void radeon_print_display_setup(struct drm_device *dev)
0771 {
0772     struct drm_connector *connector;
0773     struct radeon_connector *radeon_connector;
0774     struct drm_encoder *encoder;
0775     struct radeon_encoder *radeon_encoder;
0776     uint32_t devices;
0777     int i = 0;
0778 
0779     DRM_INFO("Radeon Display Connectors\n");
0780     list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
0781         radeon_connector = to_radeon_connector(connector);
0782         DRM_INFO("Connector %d:\n", i);
0783         DRM_INFO("  %s\n", connector->name);
0784         if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
0785             DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
0786         if (radeon_connector->ddc_bus) {
0787             DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
0788                  radeon_connector->ddc_bus->rec.mask_clk_reg,
0789                  radeon_connector->ddc_bus->rec.mask_data_reg,
0790                  radeon_connector->ddc_bus->rec.a_clk_reg,
0791                  radeon_connector->ddc_bus->rec.a_data_reg,
0792                  radeon_connector->ddc_bus->rec.en_clk_reg,
0793                  radeon_connector->ddc_bus->rec.en_data_reg,
0794                  radeon_connector->ddc_bus->rec.y_clk_reg,
0795                  radeon_connector->ddc_bus->rec.y_data_reg);
0796             if (radeon_connector->router.ddc_valid)
0797                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
0798                      radeon_connector->router.ddc_mux_control_pin,
0799                      radeon_connector->router.ddc_mux_state);
0800             if (radeon_connector->router.cd_valid)
0801                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
0802                      radeon_connector->router.cd_mux_control_pin,
0803                      radeon_connector->router.cd_mux_state);
0804         } else {
0805             if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
0806                 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
0807                 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
0808                 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
0809                 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
0810                 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
0811                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
0812         }
0813         DRM_INFO("  Encoders:\n");
0814         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
0815             radeon_encoder = to_radeon_encoder(encoder);
0816             devices = radeon_encoder->devices & radeon_connector->devices;
0817             if (devices) {
0818                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
0819                     DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
0820                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
0821                     DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
0822                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
0823                     DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
0824                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
0825                     DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
0826                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
0827                     DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
0828                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
0829                     DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
0830                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
0831                     DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
0832                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
0833                     DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
0834                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
0835                     DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
0836                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
0837                     DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
0838                 if (devices & ATOM_DEVICE_CV_SUPPORT)
0839                     DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
0840             }
0841         }
0842         i++;
0843     }
0844 }
0845 
0846 static bool radeon_setup_enc_conn(struct drm_device *dev)
0847 {
0848     struct radeon_device *rdev = dev->dev_private;
0849     bool ret = false;
0850 
0851     if (rdev->bios) {
0852         if (rdev->is_atom_bios) {
0853             ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
0854             if (!ret)
0855                 ret = radeon_get_atom_connector_info_from_object_table(dev);
0856         } else {
0857             ret = radeon_get_legacy_connector_info_from_bios(dev);
0858             if (!ret)
0859                 ret = radeon_get_legacy_connector_info_from_table(dev);
0860         }
0861     } else {
0862         if (!ASIC_IS_AVIVO(rdev))
0863             ret = radeon_get_legacy_connector_info_from_table(dev);
0864     }
0865     if (ret) {
0866         radeon_setup_encoder_clones(dev);
0867         radeon_print_display_setup(dev);
0868     }
0869 
0870     return ret;
0871 }
0872 
0873 /* avivo */
0874 
0875 /**
0876  * avivo_reduce_ratio - fractional number reduction
0877  *
0878  * @nom: nominator
0879  * @den: denominator
0880  * @nom_min: minimum value for nominator
0881  * @den_min: minimum value for denominator
0882  *
0883  * Find the greatest common divisor and apply it on both nominator and
0884  * denominator, but make nominator and denominator are at least as large
0885  * as their minimum values.
0886  */
0887 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
0888                    unsigned nom_min, unsigned den_min)
0889 {
0890     unsigned tmp;
0891 
0892     /* reduce the numbers to a simpler ratio */
0893     tmp = gcd(*nom, *den);
0894     *nom /= tmp;
0895     *den /= tmp;
0896 
0897     /* make sure nominator is large enough */
0898     if (*nom < nom_min) {
0899         tmp = DIV_ROUND_UP(nom_min, *nom);
0900         *nom *= tmp;
0901         *den *= tmp;
0902     }
0903 
0904     /* make sure the denominator is large enough */
0905     if (*den < den_min) {
0906         tmp = DIV_ROUND_UP(den_min, *den);
0907         *nom *= tmp;
0908         *den *= tmp;
0909     }
0910 }
0911 
0912 /**
0913  * avivo_get_fb_ref_div - feedback and ref divider calculation
0914  *
0915  * @nom: nominator
0916  * @den: denominator
0917  * @post_div: post divider
0918  * @fb_div_max: feedback divider maximum
0919  * @ref_div_max: reference divider maximum
0920  * @fb_div: resulting feedback divider
0921  * @ref_div: resulting reference divider
0922  *
0923  * Calculate feedback and reference divider for a given post divider. Makes
0924  * sure we stay within the limits.
0925  */
0926 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
0927                  unsigned fb_div_max, unsigned ref_div_max,
0928                  unsigned *fb_div, unsigned *ref_div)
0929 {
0930     /* limit reference * post divider to a maximum */
0931     ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
0932 
0933     /* get matching reference and feedback divider */
0934     *ref_div = min(max(den/post_div, 1u), ref_div_max);
0935     *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
0936 
0937     /* limit fb divider to its maximum */
0938     if (*fb_div > fb_div_max) {
0939         *ref_div = (*ref_div * fb_div_max)/(*fb_div);
0940         *fb_div = fb_div_max;
0941     }
0942 }
0943 
0944 /**
0945  * radeon_compute_pll_avivo - compute PLL paramaters
0946  *
0947  * @pll: information about the PLL
0948  * @freq: target frequency
0949  * @dot_clock_p: resulting pixel clock
0950  * @fb_div_p: resulting feedback divider
0951  * @frac_fb_div_p: fractional part of the feedback divider
0952  * @ref_div_p: resulting reference divider
0953  * @post_div_p: resulting reference divider
0954  *
0955  * Try to calculate the PLL parameters to generate the given frequency:
0956  * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
0957  */
0958 void radeon_compute_pll_avivo(struct radeon_pll *pll,
0959                   u32 freq,
0960                   u32 *dot_clock_p,
0961                   u32 *fb_div_p,
0962                   u32 *frac_fb_div_p,
0963                   u32 *ref_div_p,
0964                   u32 *post_div_p)
0965 {
0966     unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
0967         freq : freq / 10;
0968 
0969     unsigned fb_div_min, fb_div_max, fb_div;
0970     unsigned post_div_min, post_div_max, post_div;
0971     unsigned ref_div_min, ref_div_max, ref_div;
0972     unsigned post_div_best, diff_best;
0973     unsigned nom, den;
0974 
0975     /* determine allowed feedback divider range */
0976     fb_div_min = pll->min_feedback_div;
0977     fb_div_max = pll->max_feedback_div;
0978 
0979     if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
0980         fb_div_min *= 10;
0981         fb_div_max *= 10;
0982     }
0983 
0984     /* determine allowed ref divider range */
0985     if (pll->flags & RADEON_PLL_USE_REF_DIV)
0986         ref_div_min = pll->reference_div;
0987     else
0988         ref_div_min = pll->min_ref_div;
0989 
0990     if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
0991         pll->flags & RADEON_PLL_USE_REF_DIV)
0992         ref_div_max = pll->reference_div;
0993     else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
0994         /* fix for problems on RS880 */
0995         ref_div_max = min(pll->max_ref_div, 7u);
0996     else
0997         ref_div_max = pll->max_ref_div;
0998 
0999     /* determine allowed post divider range */
1000     if (pll->flags & RADEON_PLL_USE_POST_DIV) {
1001         post_div_min = pll->post_div;
1002         post_div_max = pll->post_div;
1003     } else {
1004         unsigned vco_min, vco_max;
1005 
1006         if (pll->flags & RADEON_PLL_IS_LCD) {
1007             vco_min = pll->lcd_pll_out_min;
1008             vco_max = pll->lcd_pll_out_max;
1009         } else {
1010             vco_min = pll->pll_out_min;
1011             vco_max = pll->pll_out_max;
1012         }
1013 
1014         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1015             vco_min *= 10;
1016             vco_max *= 10;
1017         }
1018 
1019         post_div_min = vco_min / target_clock;
1020         if ((target_clock * post_div_min) < vco_min)
1021             ++post_div_min;
1022         if (post_div_min < pll->min_post_div)
1023             post_div_min = pll->min_post_div;
1024 
1025         post_div_max = vco_max / target_clock;
1026         if ((target_clock * post_div_max) > vco_max)
1027             --post_div_max;
1028         if (post_div_max > pll->max_post_div)
1029             post_div_max = pll->max_post_div;
1030     }
1031 
1032     /* represent the searched ratio as fractional number */
1033     nom = target_clock;
1034     den = pll->reference_freq;
1035 
1036     /* reduce the numbers to a simpler ratio */
1037     avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1038 
1039     /* now search for a post divider */
1040     if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1041         post_div_best = post_div_min;
1042     else
1043         post_div_best = post_div_max;
1044     diff_best = ~0;
1045 
1046     for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1047         unsigned diff;
1048         avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1049                      ref_div_max, &fb_div, &ref_div);
1050         diff = abs(target_clock - (pll->reference_freq * fb_div) /
1051             (ref_div * post_div));
1052 
1053         if (diff < diff_best || (diff == diff_best &&
1054             !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1055 
1056             post_div_best = post_div;
1057             diff_best = diff;
1058         }
1059     }
1060     post_div = post_div_best;
1061 
1062     /* get the feedback and reference divider for the optimal value */
1063     avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1064                  &fb_div, &ref_div);
1065 
1066     /* reduce the numbers to a simpler ratio once more */
1067     /* this also makes sure that the reference divider is large enough */
1068     avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1069 
1070     /* avoid high jitter with small fractional dividers */
1071     if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1072         fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1073         if (fb_div < fb_div_min) {
1074             unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1075             fb_div *= tmp;
1076             ref_div *= tmp;
1077         }
1078     }
1079 
1080     /* and finally save the result */
1081     if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1082         *fb_div_p = fb_div / 10;
1083         *frac_fb_div_p = fb_div % 10;
1084     } else {
1085         *fb_div_p = fb_div;
1086         *frac_fb_div_p = 0;
1087     }
1088 
1089     *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1090             (pll->reference_freq * *frac_fb_div_p)) /
1091                (ref_div * post_div * 10);
1092     *ref_div_p = ref_div;
1093     *post_div_p = post_div;
1094 
1095     DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1096               freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1097               ref_div, post_div);
1098 }
1099 
1100 /* pre-avivo */
1101 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1102 {
1103     n += d / 2;
1104 
1105     do_div(n, d);
1106     return n;
1107 }
1108 
1109 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1110                    uint64_t freq,
1111                    uint32_t *dot_clock_p,
1112                    uint32_t *fb_div_p,
1113                    uint32_t *frac_fb_div_p,
1114                    uint32_t *ref_div_p,
1115                    uint32_t *post_div_p)
1116 {
1117     uint32_t min_ref_div = pll->min_ref_div;
1118     uint32_t max_ref_div = pll->max_ref_div;
1119     uint32_t min_post_div = pll->min_post_div;
1120     uint32_t max_post_div = pll->max_post_div;
1121     uint32_t min_fractional_feed_div = 0;
1122     uint32_t max_fractional_feed_div = 0;
1123     uint32_t best_vco = pll->best_vco;
1124     uint32_t best_post_div = 1;
1125     uint32_t best_ref_div = 1;
1126     uint32_t best_feedback_div = 1;
1127     uint32_t best_frac_feedback_div = 0;
1128     uint32_t best_freq = -1;
1129     uint32_t best_error = 0xffffffff;
1130     uint32_t best_vco_diff = 1;
1131     uint32_t post_div;
1132     u32 pll_out_min, pll_out_max;
1133 
1134     DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1135     freq = freq * 1000;
1136 
1137     if (pll->flags & RADEON_PLL_IS_LCD) {
1138         pll_out_min = pll->lcd_pll_out_min;
1139         pll_out_max = pll->lcd_pll_out_max;
1140     } else {
1141         pll_out_min = pll->pll_out_min;
1142         pll_out_max = pll->pll_out_max;
1143     }
1144 
1145     if (pll_out_min > 64800)
1146         pll_out_min = 64800;
1147 
1148     if (pll->flags & RADEON_PLL_USE_REF_DIV)
1149         min_ref_div = max_ref_div = pll->reference_div;
1150     else {
1151         while (min_ref_div < max_ref_div-1) {
1152             uint32_t mid = (min_ref_div + max_ref_div) / 2;
1153             uint32_t pll_in = pll->reference_freq / mid;
1154             if (pll_in < pll->pll_in_min)
1155                 max_ref_div = mid;
1156             else if (pll_in > pll->pll_in_max)
1157                 min_ref_div = mid;
1158             else
1159                 break;
1160         }
1161     }
1162 
1163     if (pll->flags & RADEON_PLL_USE_POST_DIV)
1164         min_post_div = max_post_div = pll->post_div;
1165 
1166     if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1167         min_fractional_feed_div = pll->min_frac_feedback_div;
1168         max_fractional_feed_div = pll->max_frac_feedback_div;
1169     }
1170 
1171     for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1172         uint32_t ref_div;
1173 
1174         if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1175             continue;
1176 
1177         /* legacy radeons only have a few post_divs */
1178         if (pll->flags & RADEON_PLL_LEGACY) {
1179             if ((post_div == 5) ||
1180                 (post_div == 7) ||
1181                 (post_div == 9) ||
1182                 (post_div == 10) ||
1183                 (post_div == 11) ||
1184                 (post_div == 13) ||
1185                 (post_div == 14) ||
1186                 (post_div == 15))
1187                 continue;
1188         }
1189 
1190         for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1191             uint32_t feedback_div, current_freq = 0, error, vco_diff;
1192             uint32_t pll_in = pll->reference_freq / ref_div;
1193             uint32_t min_feed_div = pll->min_feedback_div;
1194             uint32_t max_feed_div = pll->max_feedback_div + 1;
1195 
1196             if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1197                 continue;
1198 
1199             while (min_feed_div < max_feed_div) {
1200                 uint32_t vco;
1201                 uint32_t min_frac_feed_div = min_fractional_feed_div;
1202                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1203                 uint32_t frac_feedback_div;
1204                 uint64_t tmp;
1205 
1206                 feedback_div = (min_feed_div + max_feed_div) / 2;
1207 
1208                 tmp = (uint64_t)pll->reference_freq * feedback_div;
1209                 vco = radeon_div(tmp, ref_div);
1210 
1211                 if (vco < pll_out_min) {
1212                     min_feed_div = feedback_div + 1;
1213                     continue;
1214                 } else if (vco > pll_out_max) {
1215                     max_feed_div = feedback_div;
1216                     continue;
1217                 }
1218 
1219                 while (min_frac_feed_div < max_frac_feed_div) {
1220                     frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1221                     tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1222                     tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1223                     current_freq = radeon_div(tmp, ref_div * post_div);
1224 
1225                     if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1226                         if (freq < current_freq)
1227                             error = 0xffffffff;
1228                         else
1229                             error = freq - current_freq;
1230                     } else
1231                         error = abs(current_freq - freq);
1232                     vco_diff = abs(vco - best_vco);
1233 
1234                     if ((best_vco == 0 && error < best_error) ||
1235                         (best_vco != 0 &&
1236                          ((best_error > 100 && error < best_error - 100) ||
1237                           (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1238                         best_post_div = post_div;
1239                         best_ref_div = ref_div;
1240                         best_feedback_div = feedback_div;
1241                         best_frac_feedback_div = frac_feedback_div;
1242                         best_freq = current_freq;
1243                         best_error = error;
1244                         best_vco_diff = vco_diff;
1245                     } else if (current_freq == freq) {
1246                         if (best_freq == -1) {
1247                             best_post_div = post_div;
1248                             best_ref_div = ref_div;
1249                             best_feedback_div = feedback_div;
1250                             best_frac_feedback_div = frac_feedback_div;
1251                             best_freq = current_freq;
1252                             best_error = error;
1253                             best_vco_diff = vco_diff;
1254                         } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1255                                ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1256                                ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1257                                ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1258                                ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1259                                ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1260                             best_post_div = post_div;
1261                             best_ref_div = ref_div;
1262                             best_feedback_div = feedback_div;
1263                             best_frac_feedback_div = frac_feedback_div;
1264                             best_freq = current_freq;
1265                             best_error = error;
1266                             best_vco_diff = vco_diff;
1267                         }
1268                     }
1269                     if (current_freq < freq)
1270                         min_frac_feed_div = frac_feedback_div + 1;
1271                     else
1272                         max_frac_feed_div = frac_feedback_div;
1273                 }
1274                 if (current_freq < freq)
1275                     min_feed_div = feedback_div + 1;
1276                 else
1277                     max_feed_div = feedback_div;
1278             }
1279         }
1280     }
1281 
1282     *dot_clock_p = best_freq / 10000;
1283     *fb_div_p = best_feedback_div;
1284     *frac_fb_div_p = best_frac_feedback_div;
1285     *ref_div_p = best_ref_div;
1286     *post_div_p = best_post_div;
1287     DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1288               (long long)freq,
1289               best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1290               best_ref_div, best_post_div);
1291 
1292 }
1293 
1294 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1295     .destroy = drm_gem_fb_destroy,
1296     .create_handle = drm_gem_fb_create_handle,
1297 };
1298 
1299 int
1300 radeon_framebuffer_init(struct drm_device *dev,
1301             struct drm_framebuffer *fb,
1302             const struct drm_mode_fb_cmd2 *mode_cmd,
1303             struct drm_gem_object *obj)
1304 {
1305     int ret;
1306     fb->obj[0] = obj;
1307     drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd);
1308     ret = drm_framebuffer_init(dev, fb, &radeon_fb_funcs);
1309     if (ret) {
1310         fb->obj[0] = NULL;
1311         return ret;
1312     }
1313     return 0;
1314 }
1315 
1316 static struct drm_framebuffer *
1317 radeon_user_framebuffer_create(struct drm_device *dev,
1318                    struct drm_file *file_priv,
1319                    const struct drm_mode_fb_cmd2 *mode_cmd)
1320 {
1321     struct drm_gem_object *obj;
1322     struct drm_framebuffer *fb;
1323     int ret;
1324 
1325     obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1326     if (obj ==  NULL) {
1327         dev_err(dev->dev, "No GEM object associated to handle 0x%08X, "
1328             "can't create framebuffer\n", mode_cmd->handles[0]);
1329         return ERR_PTR(-ENOENT);
1330     }
1331 
1332     /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1333     if (obj->import_attach) {
1334         DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
1335         drm_gem_object_put(obj);
1336         return ERR_PTR(-EINVAL);
1337     }
1338 
1339     fb = kzalloc(sizeof(*fb), GFP_KERNEL);
1340     if (fb == NULL) {
1341         drm_gem_object_put(obj);
1342         return ERR_PTR(-ENOMEM);
1343     }
1344 
1345     ret = radeon_framebuffer_init(dev, fb, mode_cmd, obj);
1346     if (ret) {
1347         kfree(fb);
1348         drm_gem_object_put(obj);
1349         return ERR_PTR(ret);
1350     }
1351 
1352     return fb;
1353 }
1354 
1355 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1356     .fb_create = radeon_user_framebuffer_create,
1357     .output_poll_changed = drm_fb_helper_output_poll_changed,
1358 };
1359 
1360 static const struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1361 {   { 0, "driver" },
1362     { 1, "bios" },
1363 };
1364 
1365 static const struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1366 {   { TV_STD_NTSC, "ntsc" },
1367     { TV_STD_PAL, "pal" },
1368     { TV_STD_PAL_M, "pal-m" },
1369     { TV_STD_PAL_60, "pal-60" },
1370     { TV_STD_NTSC_J, "ntsc-j" },
1371     { TV_STD_SCART_PAL, "scart-pal" },
1372     { TV_STD_PAL_CN, "pal-cn" },
1373     { TV_STD_SECAM, "secam" },
1374 };
1375 
1376 static const struct drm_prop_enum_list radeon_underscan_enum_list[] =
1377 {   { UNDERSCAN_OFF, "off" },
1378     { UNDERSCAN_ON, "on" },
1379     { UNDERSCAN_AUTO, "auto" },
1380 };
1381 
1382 static const struct drm_prop_enum_list radeon_audio_enum_list[] =
1383 {   { RADEON_AUDIO_DISABLE, "off" },
1384     { RADEON_AUDIO_ENABLE, "on" },
1385     { RADEON_AUDIO_AUTO, "auto" },
1386 };
1387 
1388 /* XXX support different dither options? spatial, temporal, both, etc. */
1389 static const struct drm_prop_enum_list radeon_dither_enum_list[] =
1390 {   { RADEON_FMT_DITHER_DISABLE, "off" },
1391     { RADEON_FMT_DITHER_ENABLE, "on" },
1392 };
1393 
1394 static const struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1395 {   { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1396     { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1397     { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1398     { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1399 };
1400 
1401 static int radeon_modeset_create_props(struct radeon_device *rdev)
1402 {
1403     int sz;
1404 
1405     if (rdev->is_atom_bios) {
1406         rdev->mode_info.coherent_mode_property =
1407             drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1408         if (!rdev->mode_info.coherent_mode_property)
1409             return -ENOMEM;
1410     }
1411 
1412     if (!ASIC_IS_AVIVO(rdev)) {
1413         sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1414         rdev->mode_info.tmds_pll_property =
1415             drm_property_create_enum(rdev->ddev, 0,
1416                         "tmds_pll",
1417                         radeon_tmds_pll_enum_list, sz);
1418     }
1419 
1420     rdev->mode_info.load_detect_property =
1421         drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1422     if (!rdev->mode_info.load_detect_property)
1423         return -ENOMEM;
1424 
1425     drm_mode_create_scaling_mode_property(rdev->ddev);
1426 
1427     sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1428     rdev->mode_info.tv_std_property =
1429         drm_property_create_enum(rdev->ddev, 0,
1430                     "tv standard",
1431                     radeon_tv_std_enum_list, sz);
1432 
1433     sz = ARRAY_SIZE(radeon_underscan_enum_list);
1434     rdev->mode_info.underscan_property =
1435         drm_property_create_enum(rdev->ddev, 0,
1436                     "underscan",
1437                     radeon_underscan_enum_list, sz);
1438 
1439     rdev->mode_info.underscan_hborder_property =
1440         drm_property_create_range(rdev->ddev, 0,
1441                     "underscan hborder", 0, 128);
1442     if (!rdev->mode_info.underscan_hborder_property)
1443         return -ENOMEM;
1444 
1445     rdev->mode_info.underscan_vborder_property =
1446         drm_property_create_range(rdev->ddev, 0,
1447                     "underscan vborder", 0, 128);
1448     if (!rdev->mode_info.underscan_vborder_property)
1449         return -ENOMEM;
1450 
1451     sz = ARRAY_SIZE(radeon_audio_enum_list);
1452     rdev->mode_info.audio_property =
1453         drm_property_create_enum(rdev->ddev, 0,
1454                      "audio",
1455                      radeon_audio_enum_list, sz);
1456 
1457     sz = ARRAY_SIZE(radeon_dither_enum_list);
1458     rdev->mode_info.dither_property =
1459         drm_property_create_enum(rdev->ddev, 0,
1460                      "dither",
1461                      radeon_dither_enum_list, sz);
1462 
1463     sz = ARRAY_SIZE(radeon_output_csc_enum_list);
1464     rdev->mode_info.output_csc_property =
1465         drm_property_create_enum(rdev->ddev, 0,
1466                      "output_csc",
1467                      radeon_output_csc_enum_list, sz);
1468 
1469     return 0;
1470 }
1471 
1472 void radeon_update_display_priority(struct radeon_device *rdev)
1473 {
1474     /* adjustment options for the display watermarks */
1475     if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1476         /* set display priority to high for r3xx, rv515 chips
1477          * this avoids flickering due to underflow to the
1478          * display controllers during heavy acceleration.
1479          * Don't force high on rs4xx igp chips as it seems to
1480          * affect the sound card.  See kernel bug 15982.
1481          */
1482         if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1483             !(rdev->flags & RADEON_IS_IGP))
1484             rdev->disp_priority = 2;
1485         else
1486             rdev->disp_priority = 0;
1487     } else
1488         rdev->disp_priority = radeon_disp_priority;
1489 
1490 }
1491 
1492 /*
1493  * Allocate hdmi structs and determine register offsets
1494  */
1495 static void radeon_afmt_init(struct radeon_device *rdev)
1496 {
1497     int i;
1498 
1499     for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1500         rdev->mode_info.afmt[i] = NULL;
1501 
1502     if (ASIC_IS_NODCE(rdev)) {
1503         /* nothing to do */
1504     } else if (ASIC_IS_DCE4(rdev)) {
1505         static uint32_t eg_offsets[] = {
1506             EVERGREEN_CRTC0_REGISTER_OFFSET,
1507             EVERGREEN_CRTC1_REGISTER_OFFSET,
1508             EVERGREEN_CRTC2_REGISTER_OFFSET,
1509             EVERGREEN_CRTC3_REGISTER_OFFSET,
1510             EVERGREEN_CRTC4_REGISTER_OFFSET,
1511             EVERGREEN_CRTC5_REGISTER_OFFSET,
1512             0x13830 - 0x7030,
1513         };
1514         int num_afmt;
1515 
1516         /* DCE8 has 7 audio blocks tied to DIG encoders */
1517         /* DCE6 has 6 audio blocks tied to DIG encoders */
1518         /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1519         /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1520         if (ASIC_IS_DCE8(rdev))
1521             num_afmt = 7;
1522         else if (ASIC_IS_DCE6(rdev))
1523             num_afmt = 6;
1524         else if (ASIC_IS_DCE5(rdev))
1525             num_afmt = 6;
1526         else if (ASIC_IS_DCE41(rdev))
1527             num_afmt = 2;
1528         else /* DCE4 */
1529             num_afmt = 6;
1530 
1531         BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1532         for (i = 0; i < num_afmt; i++) {
1533             rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1534             if (rdev->mode_info.afmt[i]) {
1535                 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1536                 rdev->mode_info.afmt[i]->id = i;
1537             }
1538         }
1539     } else if (ASIC_IS_DCE3(rdev)) {
1540         /* DCE3.x has 2 audio blocks tied to DIG encoders */
1541         rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1542         if (rdev->mode_info.afmt[0]) {
1543             rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1544             rdev->mode_info.afmt[0]->id = 0;
1545         }
1546         rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1547         if (rdev->mode_info.afmt[1]) {
1548             rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1549             rdev->mode_info.afmt[1]->id = 1;
1550         }
1551     } else if (ASIC_IS_DCE2(rdev)) {
1552         /* DCE2 has at least 1 routable audio block */
1553         rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1554         if (rdev->mode_info.afmt[0]) {
1555             rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1556             rdev->mode_info.afmt[0]->id = 0;
1557         }
1558         /* r6xx has 2 routable audio blocks */
1559         if (rdev->family >= CHIP_R600) {
1560             rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1561             if (rdev->mode_info.afmt[1]) {
1562                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1563                 rdev->mode_info.afmt[1]->id = 1;
1564             }
1565         }
1566     }
1567 }
1568 
1569 static void radeon_afmt_fini(struct radeon_device *rdev)
1570 {
1571     int i;
1572 
1573     for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1574         kfree(rdev->mode_info.afmt[i]);
1575         rdev->mode_info.afmt[i] = NULL;
1576     }
1577 }
1578 
1579 int radeon_modeset_init(struct radeon_device *rdev)
1580 {
1581     int i;
1582     int ret;
1583 
1584     drm_mode_config_init(rdev->ddev);
1585     rdev->mode_info.mode_config_initialized = true;
1586 
1587     rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1588 
1589     if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600)
1590         rdev->ddev->mode_config.async_page_flip = true;
1591 
1592     if (ASIC_IS_DCE5(rdev)) {
1593         rdev->ddev->mode_config.max_width = 16384;
1594         rdev->ddev->mode_config.max_height = 16384;
1595     } else if (ASIC_IS_AVIVO(rdev)) {
1596         rdev->ddev->mode_config.max_width = 8192;
1597         rdev->ddev->mode_config.max_height = 8192;
1598     } else {
1599         rdev->ddev->mode_config.max_width = 4096;
1600         rdev->ddev->mode_config.max_height = 4096;
1601     }
1602 
1603     rdev->ddev->mode_config.preferred_depth = 24;
1604     rdev->ddev->mode_config.prefer_shadow = 1;
1605 
1606     rdev->ddev->mode_config.fb_modifiers_not_supported = true;
1607 
1608     rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1609 
1610     ret = radeon_modeset_create_props(rdev);
1611     if (ret) {
1612         return ret;
1613     }
1614 
1615     /* init i2c buses */
1616     radeon_i2c_init(rdev);
1617 
1618     /* check combios for a valid hardcoded EDID - Sun servers */
1619     if (!rdev->is_atom_bios) {
1620         /* check for hardcoded EDID in BIOS */
1621         radeon_combios_check_hardcoded_edid(rdev);
1622     }
1623 
1624     /* allocate crtcs */
1625     for (i = 0; i < rdev->num_crtc; i++) {
1626         radeon_crtc_init(rdev->ddev, i);
1627     }
1628 
1629     /* okay we should have all the bios connectors */
1630     ret = radeon_setup_enc_conn(rdev->ddev);
1631     if (!ret) {
1632         return ret;
1633     }
1634 
1635     /* init dig PHYs, disp eng pll */
1636     if (rdev->is_atom_bios) {
1637         radeon_atom_encoder_init(rdev);
1638         radeon_atom_disp_eng_pll_init(rdev);
1639     }
1640 
1641     /* initialize hpd */
1642     radeon_hpd_init(rdev);
1643 
1644     /* setup afmt */
1645     radeon_afmt_init(rdev);
1646 
1647     radeon_fbdev_init(rdev);
1648     drm_kms_helper_poll_init(rdev->ddev);
1649 
1650     /* do pm late init */
1651     ret = radeon_pm_late_init(rdev);
1652 
1653     return 0;
1654 }
1655 
1656 void radeon_modeset_fini(struct radeon_device *rdev)
1657 {
1658     if (rdev->mode_info.mode_config_initialized) {
1659         drm_kms_helper_poll_fini(rdev->ddev);
1660         radeon_hpd_fini(rdev);
1661         drm_helper_force_disable_all(rdev->ddev);
1662         radeon_fbdev_fini(rdev);
1663         radeon_afmt_fini(rdev);
1664         drm_mode_config_cleanup(rdev->ddev);
1665         rdev->mode_info.mode_config_initialized = false;
1666     }
1667 
1668     kfree(rdev->mode_info.bios_hardcoded_edid);
1669 
1670     /* free i2c buses */
1671     radeon_i2c_fini(rdev);
1672 }
1673 
1674 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1675 {
1676     /* try and guess if this is a tv or a monitor */
1677     if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1678         (mode->vdisplay == 576) || /* 576p */
1679         (mode->vdisplay == 720) || /* 720p */
1680         (mode->vdisplay == 1080)) /* 1080p */
1681         return true;
1682     else
1683         return false;
1684 }
1685 
1686 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1687                 const struct drm_display_mode *mode,
1688                 struct drm_display_mode *adjusted_mode)
1689 {
1690     struct drm_device *dev = crtc->dev;
1691     struct radeon_device *rdev = dev->dev_private;
1692     struct drm_encoder *encoder;
1693     struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1694     struct radeon_encoder *radeon_encoder;
1695     struct drm_connector *connector;
1696     bool first = true;
1697     u32 src_v = 1, dst_v = 1;
1698     u32 src_h = 1, dst_h = 1;
1699 
1700     radeon_crtc->h_border = 0;
1701     radeon_crtc->v_border = 0;
1702 
1703     list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1704         if (encoder->crtc != crtc)
1705             continue;
1706         radeon_encoder = to_radeon_encoder(encoder);
1707         connector = radeon_get_connector_for_encoder(encoder);
1708 
1709         if (first) {
1710             /* set scaling */
1711             if (radeon_encoder->rmx_type == RMX_OFF)
1712                 radeon_crtc->rmx_type = RMX_OFF;
1713             else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1714                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1715                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1716             else
1717                 radeon_crtc->rmx_type = RMX_OFF;
1718             /* copy native mode */
1719             memcpy(&radeon_crtc->native_mode,
1720                    &radeon_encoder->native_mode,
1721                 sizeof(struct drm_display_mode));
1722             src_v = crtc->mode.vdisplay;
1723             dst_v = radeon_crtc->native_mode.vdisplay;
1724             src_h = crtc->mode.hdisplay;
1725             dst_h = radeon_crtc->native_mode.hdisplay;
1726 
1727             /* fix up for overscan on hdmi */
1728             if (ASIC_IS_AVIVO(rdev) &&
1729                 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1730                 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1731                  ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1732                   drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1733                   is_hdtv_mode(mode)))) {
1734                 if (radeon_encoder->underscan_hborder != 0)
1735                     radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1736                 else
1737                     radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1738                 if (radeon_encoder->underscan_vborder != 0)
1739                     radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1740                 else
1741                     radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1742                 radeon_crtc->rmx_type = RMX_FULL;
1743                 src_v = crtc->mode.vdisplay;
1744                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1745                 src_h = crtc->mode.hdisplay;
1746                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1747             }
1748             first = false;
1749         } else {
1750             if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1751                 /* WARNING: Right now this can't happen but
1752                  * in the future we need to check that scaling
1753                  * are consistent across different encoder
1754                  * (ie all encoder can work with the same
1755                  *  scaling).
1756                  */
1757                 DRM_ERROR("Scaling not consistent across encoder.\n");
1758                 return false;
1759             }
1760         }
1761     }
1762     if (radeon_crtc->rmx_type != RMX_OFF) {
1763         fixed20_12 a, b;
1764         a.full = dfixed_const(src_v);
1765         b.full = dfixed_const(dst_v);
1766         radeon_crtc->vsc.full = dfixed_div(a, b);
1767         a.full = dfixed_const(src_h);
1768         b.full = dfixed_const(dst_h);
1769         radeon_crtc->hsc.full = dfixed_div(a, b);
1770     } else {
1771         radeon_crtc->vsc.full = dfixed_const(1);
1772         radeon_crtc->hsc.full = dfixed_const(1);
1773     }
1774     return true;
1775 }
1776 
1777 /*
1778  * Retrieve current video scanout position of crtc on a given gpu, and
1779  * an optional accurate timestamp of when query happened.
1780  *
1781  * \param dev Device to query.
1782  * \param crtc Crtc to query.
1783  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1784  *              For driver internal use only also supports these flags:
1785  *
1786  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
1787  *              of a fudged earlier start of vblank.
1788  *
1789  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
1790  *              fudged earlier start of vblank in *vpos and the distance
1791  *              to true start of vblank in *hpos.
1792  *
1793  * \param *vpos Location where vertical scanout position should be stored.
1794  * \param *hpos Location where horizontal scanout position should go.
1795  * \param *stime Target location for timestamp taken immediately before
1796  *               scanout position query. Can be NULL to skip timestamp.
1797  * \param *etime Target location for timestamp taken immediately after
1798  *               scanout position query. Can be NULL to skip timestamp.
1799  *
1800  * Returns vpos as a positive number while in active scanout area.
1801  * Returns vpos as a negative number inside vblank, counting the number
1802  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1803  * until start of active scanout / end of vblank."
1804  *
1805  * \return Flags, or'ed together as follows:
1806  *
1807  * DRM_SCANOUTPOS_VALID = Query successful.
1808  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1809  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1810  * this flag means that returned position may be offset by a constant but
1811  * unknown small number of scanlines wrt. real scanout position.
1812  *
1813  */
1814 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1815                    unsigned int flags, int *vpos, int *hpos,
1816                    ktime_t *stime, ktime_t *etime,
1817                    const struct drm_display_mode *mode)
1818 {
1819     u32 stat_crtc = 0, vbl = 0, position = 0;
1820     int vbl_start, vbl_end, vtotal, ret = 0;
1821     bool in_vbl = true;
1822 
1823     struct radeon_device *rdev = dev->dev_private;
1824 
1825     /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1826 
1827     /* Get optional system timestamp before query. */
1828     if (stime)
1829         *stime = ktime_get();
1830 
1831     if (ASIC_IS_DCE4(rdev)) {
1832         if (pipe == 0) {
1833             vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1834                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1835             position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1836                       EVERGREEN_CRTC0_REGISTER_OFFSET);
1837             ret |= DRM_SCANOUTPOS_VALID;
1838         }
1839         if (pipe == 1) {
1840             vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1841                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1842             position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1843                       EVERGREEN_CRTC1_REGISTER_OFFSET);
1844             ret |= DRM_SCANOUTPOS_VALID;
1845         }
1846         if (pipe == 2) {
1847             vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1848                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1849             position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1850                       EVERGREEN_CRTC2_REGISTER_OFFSET);
1851             ret |= DRM_SCANOUTPOS_VALID;
1852         }
1853         if (pipe == 3) {
1854             vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1855                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1856             position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1857                       EVERGREEN_CRTC3_REGISTER_OFFSET);
1858             ret |= DRM_SCANOUTPOS_VALID;
1859         }
1860         if (pipe == 4) {
1861             vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1862                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1863             position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1864                       EVERGREEN_CRTC4_REGISTER_OFFSET);
1865             ret |= DRM_SCANOUTPOS_VALID;
1866         }
1867         if (pipe == 5) {
1868             vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1869                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1870             position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1871                       EVERGREEN_CRTC5_REGISTER_OFFSET);
1872             ret |= DRM_SCANOUTPOS_VALID;
1873         }
1874     } else if (ASIC_IS_AVIVO(rdev)) {
1875         if (pipe == 0) {
1876             vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1877             position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1878             ret |= DRM_SCANOUTPOS_VALID;
1879         }
1880         if (pipe == 1) {
1881             vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1882             position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1883             ret |= DRM_SCANOUTPOS_VALID;
1884         }
1885     } else {
1886         /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1887         if (pipe == 0) {
1888             /* Assume vbl_end == 0, get vbl_start from
1889              * upper 16 bits.
1890              */
1891             vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1892                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1893             /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1894             position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1895             stat_crtc = RREG32(RADEON_CRTC_STATUS);
1896             if (!(stat_crtc & 1))
1897                 in_vbl = false;
1898 
1899             ret |= DRM_SCANOUTPOS_VALID;
1900         }
1901         if (pipe == 1) {
1902             vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1903                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1904             position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1905             stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1906             if (!(stat_crtc & 1))
1907                 in_vbl = false;
1908 
1909             ret |= DRM_SCANOUTPOS_VALID;
1910         }
1911     }
1912 
1913     /* Get optional system timestamp after query. */
1914     if (etime)
1915         *etime = ktime_get();
1916 
1917     /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1918 
1919     /* Decode into vertical and horizontal scanout position. */
1920     *vpos = position & 0x1fff;
1921     *hpos = (position >> 16) & 0x1fff;
1922 
1923     /* Valid vblank area boundaries from gpu retrieved? */
1924     if (vbl > 0) {
1925         /* Yes: Decode. */
1926         ret |= DRM_SCANOUTPOS_ACCURATE;
1927         vbl_start = vbl & 0x1fff;
1928         vbl_end = (vbl >> 16) & 0x1fff;
1929     }
1930     else {
1931         /* No: Fake something reasonable which gives at least ok results. */
1932         vbl_start = mode->crtc_vdisplay;
1933         vbl_end = 0;
1934     }
1935 
1936     /* Called from driver internal vblank counter query code? */
1937     if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1938         /* Caller wants distance from real vbl_start in *hpos */
1939         *hpos = *vpos - vbl_start;
1940     }
1941 
1942     /* Fudge vblank to start a few scanlines earlier to handle the
1943      * problem that vblank irqs fire a few scanlines before start
1944      * of vblank. Some driver internal callers need the true vblank
1945      * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1946      *
1947      * The cause of the "early" vblank irq is that the irq is triggered
1948      * by the line buffer logic when the line buffer read position enters
1949      * the vblank, whereas our crtc scanout position naturally lags the
1950      * line buffer read position.
1951      */
1952     if (!(flags & USE_REAL_VBLANKSTART))
1953         vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1954 
1955     /* Test scanout position against vblank region. */
1956     if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1957         in_vbl = false;
1958 
1959     /* In vblank? */
1960     if (in_vbl)
1961         ret |= DRM_SCANOUTPOS_IN_VBLANK;
1962 
1963     /* Called from driver internal vblank counter query code? */
1964     if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1965         /* Caller wants distance from fudged earlier vbl_start */
1966         *vpos -= vbl_start;
1967         return ret;
1968     }
1969 
1970     /* Check if inside vblank area and apply corrective offsets:
1971      * vpos will then be >=0 in video scanout area, but negative
1972      * within vblank area, counting down the number of lines until
1973      * start of scanout.
1974      */
1975 
1976     /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1977     if (in_vbl && (*vpos >= vbl_start)) {
1978         vtotal = mode->crtc_vtotal;
1979         *vpos = *vpos - vtotal;
1980     }
1981 
1982     /* Correct for shifted end of vbl at vbl_end. */
1983     *vpos = *vpos - vbl_end;
1984 
1985     return ret;
1986 }
1987 
1988 bool
1989 radeon_get_crtc_scanout_position(struct drm_crtc *crtc,
1990                  bool in_vblank_irq, int *vpos, int *hpos,
1991                  ktime_t *stime, ktime_t *etime,
1992                  const struct drm_display_mode *mode)
1993 {
1994     struct drm_device *dev = crtc->dev;
1995     unsigned int pipe = crtc->index;
1996 
1997     return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1998                       stime, etime, mode);
1999 }
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