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0001 /*
0002  * Copyright 2008 Jerome Glisse.
0003  * All Rights Reserved.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice (including the next
0013  * paragraph) shall be included in all copies or substantial portions of the
0014  * Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0022  * DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors:
0025  *    Jerome Glisse <glisse@freedesktop.org>
0026  */
0027 
0028 #include <linux/list_sort.h>
0029 #include <linux/pci.h>
0030 #include <linux/uaccess.h>
0031 
0032 #include <drm/drm_device.h>
0033 #include <drm/drm_file.h>
0034 #include <drm/radeon_drm.h>
0035 
0036 #include "radeon.h"
0037 #include "radeon_reg.h"
0038 #include "radeon_trace.h"
0039 
0040 #define RADEON_CS_MAX_PRIORITY      32u
0041 #define RADEON_CS_NUM_BUCKETS       (RADEON_CS_MAX_PRIORITY + 1)
0042 
0043 /* This is based on the bucket sort with O(n) time complexity.
0044  * An item with priority "i" is added to bucket[i]. The lists are then
0045  * concatenated in descending order.
0046  */
0047 struct radeon_cs_buckets {
0048     struct list_head bucket[RADEON_CS_NUM_BUCKETS];
0049 };
0050 
0051 static void radeon_cs_buckets_init(struct radeon_cs_buckets *b)
0052 {
0053     unsigned i;
0054 
0055     for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++)
0056         INIT_LIST_HEAD(&b->bucket[i]);
0057 }
0058 
0059 static void radeon_cs_buckets_add(struct radeon_cs_buckets *b,
0060                   struct list_head *item, unsigned priority)
0061 {
0062     /* Since buffers which appear sooner in the relocation list are
0063      * likely to be used more often than buffers which appear later
0064      * in the list, the sort mustn't change the ordering of buffers
0065      * with the same priority, i.e. it must be stable.
0066      */
0067     list_add_tail(item, &b->bucket[min(priority, RADEON_CS_MAX_PRIORITY)]);
0068 }
0069 
0070 static void radeon_cs_buckets_get_list(struct radeon_cs_buckets *b,
0071                        struct list_head *out_list)
0072 {
0073     unsigned i;
0074 
0075     /* Connect the sorted buckets in the output list. */
0076     for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++) {
0077         list_splice(&b->bucket[i], out_list);
0078     }
0079 }
0080 
0081 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
0082 {
0083     struct radeon_cs_chunk *chunk;
0084     struct radeon_cs_buckets buckets;
0085     unsigned i;
0086     bool need_mmap_lock = false;
0087     int r;
0088 
0089     if (p->chunk_relocs == NULL) {
0090         return 0;
0091     }
0092     chunk = p->chunk_relocs;
0093     p->dma_reloc_idx = 0;
0094     /* FIXME: we assume that each relocs use 4 dwords */
0095     p->nrelocs = chunk->length_dw / 4;
0096     p->relocs = kvcalloc(p->nrelocs, sizeof(struct radeon_bo_list),
0097             GFP_KERNEL);
0098     if (p->relocs == NULL) {
0099         return -ENOMEM;
0100     }
0101 
0102     radeon_cs_buckets_init(&buckets);
0103 
0104     for (i = 0; i < p->nrelocs; i++) {
0105         struct drm_radeon_cs_reloc *r;
0106         struct drm_gem_object *gobj;
0107         unsigned priority;
0108 
0109         r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
0110         gobj = drm_gem_object_lookup(p->filp, r->handle);
0111         if (gobj == NULL) {
0112             DRM_ERROR("gem object lookup failed 0x%x\n",
0113                   r->handle);
0114             return -ENOENT;
0115         }
0116         p->relocs[i].robj = gem_to_radeon_bo(gobj);
0117 
0118         /* The userspace buffer priorities are from 0 to 15. A higher
0119          * number means the buffer is more important.
0120          * Also, the buffers used for write have a higher priority than
0121          * the buffers used for read only, which doubles the range
0122          * to 0 to 31. 32 is reserved for the kernel driver.
0123          */
0124         priority = (r->flags & RADEON_RELOC_PRIO_MASK) * 2
0125                + !!r->write_domain;
0126 
0127         /* The first reloc of an UVD job is the msg and that must be in
0128          * VRAM, the second reloc is the DPB and for WMV that must be in
0129          * VRAM as well. Also put everything into VRAM on AGP cards and older
0130          * IGP chips to avoid image corruptions
0131          */
0132         if (p->ring == R600_RING_TYPE_UVD_INDEX &&
0133             (i <= 0 || pci_find_capability(p->rdev->pdev, PCI_CAP_ID_AGP) ||
0134              p->rdev->family == CHIP_RS780 ||
0135              p->rdev->family == CHIP_RS880)) {
0136 
0137             /* TODO: is this still needed for NI+ ? */
0138             p->relocs[i].preferred_domains =
0139                 RADEON_GEM_DOMAIN_VRAM;
0140 
0141             p->relocs[i].allowed_domains =
0142                 RADEON_GEM_DOMAIN_VRAM;
0143 
0144             /* prioritize this over any other relocation */
0145             priority = RADEON_CS_MAX_PRIORITY;
0146         } else {
0147             uint32_t domain = r->write_domain ?
0148                 r->write_domain : r->read_domains;
0149 
0150             if (domain & RADEON_GEM_DOMAIN_CPU) {
0151                 DRM_ERROR("RADEON_GEM_DOMAIN_CPU is not valid "
0152                       "for command submission\n");
0153                 return -EINVAL;
0154             }
0155 
0156             p->relocs[i].preferred_domains = domain;
0157             if (domain == RADEON_GEM_DOMAIN_VRAM)
0158                 domain |= RADEON_GEM_DOMAIN_GTT;
0159             p->relocs[i].allowed_domains = domain;
0160         }
0161 
0162         if (radeon_ttm_tt_has_userptr(p->rdev, p->relocs[i].robj->tbo.ttm)) {
0163             uint32_t domain = p->relocs[i].preferred_domains;
0164             if (!(domain & RADEON_GEM_DOMAIN_GTT)) {
0165                 DRM_ERROR("Only RADEON_GEM_DOMAIN_GTT is "
0166                       "allowed for userptr BOs\n");
0167                 return -EINVAL;
0168             }
0169             need_mmap_lock = true;
0170             domain = RADEON_GEM_DOMAIN_GTT;
0171             p->relocs[i].preferred_domains = domain;
0172             p->relocs[i].allowed_domains = domain;
0173         }
0174 
0175         /* Objects shared as dma-bufs cannot be moved to VRAM */
0176         if (p->relocs[i].robj->prime_shared_count) {
0177             p->relocs[i].allowed_domains &= ~RADEON_GEM_DOMAIN_VRAM;
0178             if (!p->relocs[i].allowed_domains) {
0179                 DRM_ERROR("BO associated with dma-buf cannot "
0180                       "be moved to VRAM\n");
0181                 return -EINVAL;
0182             }
0183         }
0184 
0185         p->relocs[i].tv.bo = &p->relocs[i].robj->tbo;
0186         p->relocs[i].tv.num_shared = !r->write_domain;
0187 
0188         radeon_cs_buckets_add(&buckets, &p->relocs[i].tv.head,
0189                       priority);
0190     }
0191 
0192     radeon_cs_buckets_get_list(&buckets, &p->validated);
0193 
0194     if (p->cs_flags & RADEON_CS_USE_VM)
0195         p->vm_bos = radeon_vm_get_bos(p->rdev, p->ib.vm,
0196                           &p->validated);
0197     if (need_mmap_lock)
0198         mmap_read_lock(current->mm);
0199 
0200     r = radeon_bo_list_validate(p->rdev, &p->ticket, &p->validated, p->ring);
0201 
0202     if (need_mmap_lock)
0203         mmap_read_unlock(current->mm);
0204 
0205     return r;
0206 }
0207 
0208 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
0209 {
0210     p->priority = priority;
0211 
0212     switch (ring) {
0213     default:
0214         DRM_ERROR("unknown ring id: %d\n", ring);
0215         return -EINVAL;
0216     case RADEON_CS_RING_GFX:
0217         p->ring = RADEON_RING_TYPE_GFX_INDEX;
0218         break;
0219     case RADEON_CS_RING_COMPUTE:
0220         if (p->rdev->family >= CHIP_TAHITI) {
0221             if (p->priority > 0)
0222                 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
0223             else
0224                 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
0225         } else
0226             p->ring = RADEON_RING_TYPE_GFX_INDEX;
0227         break;
0228     case RADEON_CS_RING_DMA:
0229         if (p->rdev->family >= CHIP_CAYMAN) {
0230             if (p->priority > 0)
0231                 p->ring = R600_RING_TYPE_DMA_INDEX;
0232             else
0233                 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
0234         } else if (p->rdev->family >= CHIP_RV770) {
0235             p->ring = R600_RING_TYPE_DMA_INDEX;
0236         } else {
0237             return -EINVAL;
0238         }
0239         break;
0240     case RADEON_CS_RING_UVD:
0241         p->ring = R600_RING_TYPE_UVD_INDEX;
0242         break;
0243     case RADEON_CS_RING_VCE:
0244         /* TODO: only use the low priority ring for now */
0245         p->ring = TN_RING_TYPE_VCE1_INDEX;
0246         break;
0247     }
0248     return 0;
0249 }
0250 
0251 static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
0252 {
0253     struct radeon_bo_list *reloc;
0254     int r;
0255 
0256     list_for_each_entry(reloc, &p->validated, tv.head) {
0257         struct dma_resv *resv;
0258 
0259         resv = reloc->robj->tbo.base.resv;
0260         r = radeon_sync_resv(p->rdev, &p->ib.sync, resv,
0261                      reloc->tv.num_shared);
0262         if (r)
0263             return r;
0264     }
0265     return 0;
0266 }
0267 
0268 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
0269 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
0270 {
0271     struct drm_radeon_cs *cs = data;
0272     uint64_t *chunk_array_ptr;
0273     unsigned size, i;
0274     u32 ring = RADEON_CS_RING_GFX;
0275     s32 priority = 0;
0276 
0277     INIT_LIST_HEAD(&p->validated);
0278 
0279     if (!cs->num_chunks) {
0280         return 0;
0281     }
0282 
0283     /* get chunks */
0284     p->idx = 0;
0285     p->ib.sa_bo = NULL;
0286     p->const_ib.sa_bo = NULL;
0287     p->chunk_ib = NULL;
0288     p->chunk_relocs = NULL;
0289     p->chunk_flags = NULL;
0290     p->chunk_const_ib = NULL;
0291     p->chunks_array = kvmalloc_array(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
0292     if (p->chunks_array == NULL) {
0293         return -ENOMEM;
0294     }
0295     chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
0296     if (copy_from_user(p->chunks_array, chunk_array_ptr,
0297                    sizeof(uint64_t)*cs->num_chunks)) {
0298         return -EFAULT;
0299     }
0300     p->cs_flags = 0;
0301     p->nchunks = cs->num_chunks;
0302     p->chunks = kvcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
0303     if (p->chunks == NULL) {
0304         return -ENOMEM;
0305     }
0306     for (i = 0; i < p->nchunks; i++) {
0307         struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
0308         struct drm_radeon_cs_chunk user_chunk;
0309         uint32_t __user *cdata;
0310 
0311         chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
0312         if (copy_from_user(&user_chunk, chunk_ptr,
0313                        sizeof(struct drm_radeon_cs_chunk))) {
0314             return -EFAULT;
0315         }
0316         p->chunks[i].length_dw = user_chunk.length_dw;
0317         if (user_chunk.chunk_id == RADEON_CHUNK_ID_RELOCS) {
0318             p->chunk_relocs = &p->chunks[i];
0319         }
0320         if (user_chunk.chunk_id == RADEON_CHUNK_ID_IB) {
0321             p->chunk_ib = &p->chunks[i];
0322             /* zero length IB isn't useful */
0323             if (p->chunks[i].length_dw == 0)
0324                 return -EINVAL;
0325         }
0326         if (user_chunk.chunk_id == RADEON_CHUNK_ID_CONST_IB) {
0327             p->chunk_const_ib = &p->chunks[i];
0328             /* zero length CONST IB isn't useful */
0329             if (p->chunks[i].length_dw == 0)
0330                 return -EINVAL;
0331         }
0332         if (user_chunk.chunk_id == RADEON_CHUNK_ID_FLAGS) {
0333             p->chunk_flags = &p->chunks[i];
0334             /* zero length flags aren't useful */
0335             if (p->chunks[i].length_dw == 0)
0336                 return -EINVAL;
0337         }
0338 
0339         size = p->chunks[i].length_dw;
0340         cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
0341         p->chunks[i].user_ptr = cdata;
0342         if (user_chunk.chunk_id == RADEON_CHUNK_ID_CONST_IB)
0343             continue;
0344 
0345         if (user_chunk.chunk_id == RADEON_CHUNK_ID_IB) {
0346             if (!p->rdev || !(p->rdev->flags & RADEON_IS_AGP))
0347                 continue;
0348         }
0349 
0350         p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
0351         size *= sizeof(uint32_t);
0352         if (p->chunks[i].kdata == NULL) {
0353             return -ENOMEM;
0354         }
0355         if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
0356             return -EFAULT;
0357         }
0358         if (user_chunk.chunk_id == RADEON_CHUNK_ID_FLAGS) {
0359             p->cs_flags = p->chunks[i].kdata[0];
0360             if (p->chunks[i].length_dw > 1)
0361                 ring = p->chunks[i].kdata[1];
0362             if (p->chunks[i].length_dw > 2)
0363                 priority = (s32)p->chunks[i].kdata[2];
0364         }
0365     }
0366 
0367     /* these are KMS only */
0368     if (p->rdev) {
0369         if ((p->cs_flags & RADEON_CS_USE_VM) &&
0370             !p->rdev->vm_manager.enabled) {
0371             DRM_ERROR("VM not active on asic!\n");
0372             return -EINVAL;
0373         }
0374 
0375         if (radeon_cs_get_ring(p, ring, priority))
0376             return -EINVAL;
0377 
0378         /* we only support VM on some SI+ rings */
0379         if ((p->cs_flags & RADEON_CS_USE_VM) == 0) {
0380             if (p->rdev->asic->ring[p->ring]->cs_parse == NULL) {
0381                 DRM_ERROR("Ring %d requires VM!\n", p->ring);
0382                 return -EINVAL;
0383             }
0384         } else {
0385             if (p->rdev->asic->ring[p->ring]->ib_parse == NULL) {
0386                 DRM_ERROR("VM not supported on ring %d!\n",
0387                       p->ring);
0388                 return -EINVAL;
0389             }
0390         }
0391     }
0392 
0393     return 0;
0394 }
0395 
0396 static int cmp_size_smaller_first(void *priv, const struct list_head *a,
0397                   const struct list_head *b)
0398 {
0399     struct radeon_bo_list *la = list_entry(a, struct radeon_bo_list, tv.head);
0400     struct radeon_bo_list *lb = list_entry(b, struct radeon_bo_list, tv.head);
0401 
0402     /* Sort A before B if A is smaller. */
0403     return (int)la->robj->tbo.resource->num_pages -
0404         (int)lb->robj->tbo.resource->num_pages;
0405 }
0406 
0407 /**
0408  * radeon_cs_parser_fini() - clean parser states
0409  * @parser: parser structure holding parsing context.
0410  * @error:  error number
0411  * @backoff:    indicator to backoff the reservation
0412  *
0413  * If error is set than unvalidate buffer, otherwise just free memory
0414  * used by parsing context.
0415  **/
0416 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error, bool backoff)
0417 {
0418     unsigned i;
0419 
0420     if (!error) {
0421         /* Sort the buffer list from the smallest to largest buffer,
0422          * which affects the order of buffers in the LRU list.
0423          * This assures that the smallest buffers are added first
0424          * to the LRU list, so they are likely to be later evicted
0425          * first, instead of large buffers whose eviction is more
0426          * expensive.
0427          *
0428          * This slightly lowers the number of bytes moved by TTM
0429          * per frame under memory pressure.
0430          */
0431         list_sort(NULL, &parser->validated, cmp_size_smaller_first);
0432 
0433         ttm_eu_fence_buffer_objects(&parser->ticket,
0434                         &parser->validated,
0435                         &parser->ib.fence->base);
0436     } else if (backoff) {
0437         ttm_eu_backoff_reservation(&parser->ticket,
0438                        &parser->validated);
0439     }
0440 
0441     if (parser->relocs != NULL) {
0442         for (i = 0; i < parser->nrelocs; i++) {
0443             struct radeon_bo *bo = parser->relocs[i].robj;
0444             if (bo == NULL)
0445                 continue;
0446 
0447             drm_gem_object_put(&bo->tbo.base);
0448         }
0449     }
0450     kfree(parser->track);
0451     kvfree(parser->relocs);
0452     kvfree(parser->vm_bos);
0453     for (i = 0; i < parser->nchunks; i++)
0454         kvfree(parser->chunks[i].kdata);
0455     kvfree(parser->chunks);
0456     kvfree(parser->chunks_array);
0457     radeon_ib_free(parser->rdev, &parser->ib);
0458     radeon_ib_free(parser->rdev, &parser->const_ib);
0459 }
0460 
0461 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
0462                   struct radeon_cs_parser *parser)
0463 {
0464     int r;
0465 
0466     if (parser->chunk_ib == NULL)
0467         return 0;
0468 
0469     if (parser->cs_flags & RADEON_CS_USE_VM)
0470         return 0;
0471 
0472     r = radeon_cs_parse(rdev, parser->ring, parser);
0473     if (r || parser->parser_error) {
0474         DRM_ERROR("Invalid command stream !\n");
0475         return r;
0476     }
0477 
0478     r = radeon_cs_sync_rings(parser);
0479     if (r) {
0480         if (r != -ERESTARTSYS)
0481             DRM_ERROR("Failed to sync rings: %i\n", r);
0482         return r;
0483     }
0484 
0485     if (parser->ring == R600_RING_TYPE_UVD_INDEX)
0486         radeon_uvd_note_usage(rdev);
0487     else if ((parser->ring == TN_RING_TYPE_VCE1_INDEX) ||
0488          (parser->ring == TN_RING_TYPE_VCE2_INDEX))
0489         radeon_vce_note_usage(rdev);
0490 
0491     r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
0492     if (r) {
0493         DRM_ERROR("Failed to schedule IB !\n");
0494     }
0495     return r;
0496 }
0497 
0498 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *p,
0499                    struct radeon_vm *vm)
0500 {
0501     struct radeon_device *rdev = p->rdev;
0502     struct radeon_bo_va *bo_va;
0503     int i, r;
0504 
0505     r = radeon_vm_update_page_directory(rdev, vm);
0506     if (r)
0507         return r;
0508 
0509     r = radeon_vm_clear_freed(rdev, vm);
0510     if (r)
0511         return r;
0512 
0513     if (vm->ib_bo_va == NULL) {
0514         DRM_ERROR("Tmp BO not in VM!\n");
0515         return -EINVAL;
0516     }
0517 
0518     r = radeon_vm_bo_update(rdev, vm->ib_bo_va,
0519                 rdev->ring_tmp_bo.bo->tbo.resource);
0520     if (r)
0521         return r;
0522 
0523     for (i = 0; i < p->nrelocs; i++) {
0524         struct radeon_bo *bo;
0525 
0526         bo = p->relocs[i].robj;
0527         bo_va = radeon_vm_bo_find(vm, bo);
0528         if (bo_va == NULL) {
0529             dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm);
0530             return -EINVAL;
0531         }
0532 
0533         r = radeon_vm_bo_update(rdev, bo_va, bo->tbo.resource);
0534         if (r)
0535             return r;
0536 
0537         radeon_sync_fence(&p->ib.sync, bo_va->last_pt_update);
0538 
0539         r = dma_resv_reserve_fences(bo->tbo.base.resv, 1);
0540         if (r)
0541             return r;
0542     }
0543 
0544     return radeon_vm_clear_invalids(rdev, vm);
0545 }
0546 
0547 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
0548                  struct radeon_cs_parser *parser)
0549 {
0550     struct radeon_fpriv *fpriv = parser->filp->driver_priv;
0551     struct radeon_vm *vm = &fpriv->vm;
0552     int r;
0553 
0554     if (parser->chunk_ib == NULL)
0555         return 0;
0556     if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
0557         return 0;
0558 
0559     if (parser->const_ib.length_dw) {
0560         r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
0561         if (r) {
0562             return r;
0563         }
0564     }
0565 
0566     r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
0567     if (r) {
0568         return r;
0569     }
0570 
0571     if (parser->ring == R600_RING_TYPE_UVD_INDEX)
0572         radeon_uvd_note_usage(rdev);
0573 
0574     mutex_lock(&vm->mutex);
0575     r = radeon_bo_vm_update_pte(parser, vm);
0576     if (r) {
0577         goto out;
0578     }
0579 
0580     r = radeon_cs_sync_rings(parser);
0581     if (r) {
0582         if (r != -ERESTARTSYS)
0583             DRM_ERROR("Failed to sync rings: %i\n", r);
0584         goto out;
0585     }
0586 
0587     if ((rdev->family >= CHIP_TAHITI) &&
0588         (parser->chunk_const_ib != NULL)) {
0589         r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib, true);
0590     } else {
0591         r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
0592     }
0593 
0594 out:
0595     mutex_unlock(&vm->mutex);
0596     return r;
0597 }
0598 
0599 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
0600 {
0601     if (r == -EDEADLK) {
0602         r = radeon_gpu_reset(rdev);
0603         if (!r)
0604             r = -EAGAIN;
0605     }
0606     return r;
0607 }
0608 
0609 static int radeon_cs_ib_fill(struct radeon_device *rdev, struct radeon_cs_parser *parser)
0610 {
0611     struct radeon_cs_chunk *ib_chunk;
0612     struct radeon_vm *vm = NULL;
0613     int r;
0614 
0615     if (parser->chunk_ib == NULL)
0616         return 0;
0617 
0618     if (parser->cs_flags & RADEON_CS_USE_VM) {
0619         struct radeon_fpriv *fpriv = parser->filp->driver_priv;
0620         vm = &fpriv->vm;
0621 
0622         if ((rdev->family >= CHIP_TAHITI) &&
0623             (parser->chunk_const_ib != NULL)) {
0624             ib_chunk = parser->chunk_const_ib;
0625             if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
0626                 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
0627                 return -EINVAL;
0628             }
0629             r =  radeon_ib_get(rdev, parser->ring, &parser->const_ib,
0630                        vm, ib_chunk->length_dw * 4);
0631             if (r) {
0632                 DRM_ERROR("Failed to get const ib !\n");
0633                 return r;
0634             }
0635             parser->const_ib.is_const_ib = true;
0636             parser->const_ib.length_dw = ib_chunk->length_dw;
0637             if (copy_from_user(parser->const_ib.ptr,
0638                            ib_chunk->user_ptr,
0639                            ib_chunk->length_dw * 4))
0640                 return -EFAULT;
0641         }
0642 
0643         ib_chunk = parser->chunk_ib;
0644         if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
0645             DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
0646             return -EINVAL;
0647         }
0648     }
0649     ib_chunk = parser->chunk_ib;
0650 
0651     r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
0652                vm, ib_chunk->length_dw * 4);
0653     if (r) {
0654         DRM_ERROR("Failed to get ib !\n");
0655         return r;
0656     }
0657     parser->ib.length_dw = ib_chunk->length_dw;
0658     if (ib_chunk->kdata)
0659         memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4);
0660     else if (copy_from_user(parser->ib.ptr, ib_chunk->user_ptr, ib_chunk->length_dw * 4))
0661         return -EFAULT;
0662     return 0;
0663 }
0664 
0665 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
0666 {
0667     struct radeon_device *rdev = dev->dev_private;
0668     struct radeon_cs_parser parser;
0669     int r;
0670 
0671     down_read(&rdev->exclusive_lock);
0672     if (!rdev->accel_working) {
0673         up_read(&rdev->exclusive_lock);
0674         return -EBUSY;
0675     }
0676     if (rdev->in_reset) {
0677         up_read(&rdev->exclusive_lock);
0678         r = radeon_gpu_reset(rdev);
0679         if (!r)
0680             r = -EAGAIN;
0681         return r;
0682     }
0683     /* initialize parser */
0684     memset(&parser, 0, sizeof(struct radeon_cs_parser));
0685     parser.filp = filp;
0686     parser.rdev = rdev;
0687     parser.dev = rdev->dev;
0688     parser.family = rdev->family;
0689     r = radeon_cs_parser_init(&parser, data);
0690     if (r) {
0691         DRM_ERROR("Failed to initialize parser !\n");
0692         radeon_cs_parser_fini(&parser, r, false);
0693         up_read(&rdev->exclusive_lock);
0694         r = radeon_cs_handle_lockup(rdev, r);
0695         return r;
0696     }
0697 
0698     r = radeon_cs_ib_fill(rdev, &parser);
0699     if (!r) {
0700         r = radeon_cs_parser_relocs(&parser);
0701         if (r && r != -ERESTARTSYS)
0702             DRM_ERROR("Failed to parse relocation %d!\n", r);
0703     }
0704 
0705     if (r) {
0706         radeon_cs_parser_fini(&parser, r, false);
0707         up_read(&rdev->exclusive_lock);
0708         r = radeon_cs_handle_lockup(rdev, r);
0709         return r;
0710     }
0711 
0712     trace_radeon_cs(&parser);
0713 
0714     r = radeon_cs_ib_chunk(rdev, &parser);
0715     if (r) {
0716         goto out;
0717     }
0718     r = radeon_cs_ib_vm_chunk(rdev, &parser);
0719     if (r) {
0720         goto out;
0721     }
0722 out:
0723     radeon_cs_parser_fini(&parser, r, true);
0724     up_read(&rdev->exclusive_lock);
0725     r = radeon_cs_handle_lockup(rdev, r);
0726     return r;
0727 }
0728 
0729 /**
0730  * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
0731  * @p:      parser structure holding parsing context.
0732  * @pkt:    where to store packet information
0733  * @idx:    packet index
0734  *
0735  * Assume that chunk_ib_index is properly set. Will return -EINVAL
0736  * if packet is bigger than remaining ib size. or if packets is unknown.
0737  **/
0738 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
0739                struct radeon_cs_packet *pkt,
0740                unsigned idx)
0741 {
0742     struct radeon_cs_chunk *ib_chunk = p->chunk_ib;
0743     struct radeon_device *rdev = p->rdev;
0744     uint32_t header;
0745     int ret = 0, i;
0746 
0747     if (idx >= ib_chunk->length_dw) {
0748         DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
0749               idx, ib_chunk->length_dw);
0750         return -EINVAL;
0751     }
0752     header = radeon_get_ib_value(p, idx);
0753     pkt->idx = idx;
0754     pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
0755     pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
0756     pkt->one_reg_wr = 0;
0757     switch (pkt->type) {
0758     case RADEON_PACKET_TYPE0:
0759         if (rdev->family < CHIP_R600) {
0760             pkt->reg = R100_CP_PACKET0_GET_REG(header);
0761             pkt->one_reg_wr =
0762                 RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
0763         } else
0764             pkt->reg = R600_CP_PACKET0_GET_REG(header);
0765         break;
0766     case RADEON_PACKET_TYPE3:
0767         pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
0768         break;
0769     case RADEON_PACKET_TYPE2:
0770         pkt->count = -1;
0771         break;
0772     default:
0773         DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
0774         ret = -EINVAL;
0775         goto dump_ib;
0776     }
0777     if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
0778         DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
0779               pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
0780         ret = -EINVAL;
0781         goto dump_ib;
0782     }
0783     return 0;
0784 
0785 dump_ib:
0786     for (i = 0; i < ib_chunk->length_dw; i++) {
0787         if (i == idx)
0788             printk("\t0x%08x <---\n", radeon_get_ib_value(p, i));
0789         else
0790             printk("\t0x%08x\n", radeon_get_ib_value(p, i));
0791     }
0792     return ret;
0793 }
0794 
0795 /**
0796  * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
0797  * @p:      structure holding the parser context.
0798  *
0799  * Check if the next packet is NOP relocation packet3.
0800  **/
0801 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
0802 {
0803     struct radeon_cs_packet p3reloc;
0804     int r;
0805 
0806     r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
0807     if (r)
0808         return false;
0809     if (p3reloc.type != RADEON_PACKET_TYPE3)
0810         return false;
0811     if (p3reloc.opcode != RADEON_PACKET3_NOP)
0812         return false;
0813     return true;
0814 }
0815 
0816 /**
0817  * radeon_cs_dump_packet() - dump raw packet context
0818  * @p:      structure holding the parser context.
0819  * @pkt:    structure holding the packet.
0820  *
0821  * Used mostly for debugging and error reporting.
0822  **/
0823 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
0824                struct radeon_cs_packet *pkt)
0825 {
0826     volatile uint32_t *ib;
0827     unsigned i;
0828     unsigned idx;
0829 
0830     ib = p->ib.ptr;
0831     idx = pkt->idx;
0832     for (i = 0; i <= (pkt->count + 1); i++, idx++)
0833         DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
0834 }
0835 
0836 /**
0837  * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
0838  * @p:          parser structure holding parsing context.
0839  * @cs_reloc:       reloc informations
0840  * @nomm:       no memory management for debugging
0841  *
0842  * Check if next packet is relocation packet3, do bo validation and compute
0843  * GPU offset using the provided start.
0844  **/
0845 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
0846                 struct radeon_bo_list **cs_reloc,
0847                 int nomm)
0848 {
0849     struct radeon_cs_chunk *relocs_chunk;
0850     struct radeon_cs_packet p3reloc;
0851     unsigned idx;
0852     int r;
0853 
0854     if (p->chunk_relocs == NULL) {
0855         DRM_ERROR("No relocation chunk !\n");
0856         return -EINVAL;
0857     }
0858     *cs_reloc = NULL;
0859     relocs_chunk = p->chunk_relocs;
0860     r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
0861     if (r)
0862         return r;
0863     p->idx += p3reloc.count + 2;
0864     if (p3reloc.type != RADEON_PACKET_TYPE3 ||
0865         p3reloc.opcode != RADEON_PACKET3_NOP) {
0866         DRM_ERROR("No packet3 for relocation for packet at %d.\n",
0867               p3reloc.idx);
0868         radeon_cs_dump_packet(p, &p3reloc);
0869         return -EINVAL;
0870     }
0871     idx = radeon_get_ib_value(p, p3reloc.idx + 1);
0872     if (idx >= relocs_chunk->length_dw) {
0873         DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
0874               idx, relocs_chunk->length_dw);
0875         radeon_cs_dump_packet(p, &p3reloc);
0876         return -EINVAL;
0877     }
0878     /* FIXME: we assume reloc size is 4 dwords */
0879     if (nomm) {
0880         *cs_reloc = p->relocs;
0881         (*cs_reloc)->gpu_offset =
0882             (u64)relocs_chunk->kdata[idx + 3] << 32;
0883         (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0];
0884     } else
0885         *cs_reloc = &p->relocs[(idx / 4)];
0886     return 0;
0887 }
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