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0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  * Copyright 2009 Jerome Glisse.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors: Dave Airlie
0025  *          Alex Deucher
0026  *          Jerome Glisse
0027  */
0028 
0029 #include <linux/pci.h>
0030 
0031 #include <drm/drm_device.h>
0032 #include <drm/radeon_drm.h>
0033 
0034 #include "atom.h"
0035 #include "radeon.h"
0036 #include "radeon_asic.h"
0037 #include "radeon_reg.h"
0038 
0039 /* 10 khz */
0040 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
0041 {
0042     struct radeon_pll *spll = &rdev->clock.spll;
0043     uint32_t fb_div, ref_div, post_div, sclk;
0044 
0045     fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
0046     fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK;
0047     fb_div <<= 1;
0048     fb_div *= spll->reference_freq;
0049 
0050     ref_div =
0051         RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
0052 
0053     if (ref_div == 0)
0054         return 0;
0055 
0056     sclk = fb_div / ref_div;
0057 
0058     post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;
0059     if (post_div == 2)
0060         sclk >>= 1;
0061     else if (post_div == 3)
0062         sclk >>= 2;
0063     else if (post_div == 4)
0064         sclk >>= 3;
0065 
0066     return sclk;
0067 }
0068 
0069 /* 10 khz */
0070 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
0071 {
0072     struct radeon_pll *mpll = &rdev->clock.mpll;
0073     uint32_t fb_div, ref_div, post_div, mclk;
0074 
0075     fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
0076     fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK;
0077     fb_div <<= 1;
0078     fb_div *= mpll->reference_freq;
0079 
0080     ref_div =
0081         RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
0082 
0083     if (ref_div == 0)
0084         return 0;
0085 
0086     mclk = fb_div / ref_div;
0087 
0088     post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;
0089     if (post_div == 2)
0090         mclk >>= 1;
0091     else if (post_div == 3)
0092         mclk >>= 2;
0093     else if (post_div == 4)
0094         mclk >>= 3;
0095 
0096     return mclk;
0097 }
0098 
0099 #ifdef CONFIG_OF
0100 /*
0101  * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
0102  * tree. Hopefully, ATI OF driver is kind enough to fill these
0103  */
0104 static bool radeon_read_clocks_OF(struct drm_device *dev)
0105 {
0106     struct radeon_device *rdev = dev->dev_private;
0107     struct device_node *dp = rdev->pdev->dev.of_node;
0108     const u32 *val;
0109     struct radeon_pll *p1pll = &rdev->clock.p1pll;
0110     struct radeon_pll *p2pll = &rdev->clock.p2pll;
0111     struct radeon_pll *spll = &rdev->clock.spll;
0112     struct radeon_pll *mpll = &rdev->clock.mpll;
0113 
0114     if (dp == NULL)
0115         return false;
0116     val = of_get_property(dp, "ATY,RefCLK", NULL);
0117     if (!val || !*val) {
0118         pr_warn("radeonfb: No ATY,RefCLK property !\n");
0119         return false;
0120     }
0121     p1pll->reference_freq = p2pll->reference_freq = (*val) / 10;
0122     p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
0123     if (p1pll->reference_div < 2)
0124         p1pll->reference_div = 12;
0125     p2pll->reference_div = p1pll->reference_div;
0126 
0127     /* These aren't in the device-tree */
0128     if (rdev->family >= CHIP_R420) {
0129         p1pll->pll_in_min = 100;
0130         p1pll->pll_in_max = 1350;
0131         p1pll->pll_out_min = 20000;
0132         p1pll->pll_out_max = 50000;
0133         p2pll->pll_in_min = 100;
0134         p2pll->pll_in_max = 1350;
0135         p2pll->pll_out_min = 20000;
0136         p2pll->pll_out_max = 50000;
0137     } else {
0138         p1pll->pll_in_min = 40;
0139         p1pll->pll_in_max = 500;
0140         p1pll->pll_out_min = 12500;
0141         p1pll->pll_out_max = 35000;
0142         p2pll->pll_in_min = 40;
0143         p2pll->pll_in_max = 500;
0144         p2pll->pll_out_min = 12500;
0145         p2pll->pll_out_max = 35000;
0146     }
0147     /* not sure what the max should be in all cases */
0148     rdev->clock.max_pixel_clock = 35000;
0149 
0150     spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
0151     spll->reference_div = mpll->reference_div =
0152         RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
0153                 RADEON_M_SPLL_REF_DIV_MASK;
0154 
0155     val = of_get_property(dp, "ATY,SCLK", NULL);
0156     if (val && *val)
0157         rdev->clock.default_sclk = (*val) / 10;
0158     else
0159         rdev->clock.default_sclk =
0160             radeon_legacy_get_engine_clock(rdev);
0161 
0162     val = of_get_property(dp, "ATY,MCLK", NULL);
0163     if (val && *val)
0164         rdev->clock.default_mclk = (*val) / 10;
0165     else
0166         rdev->clock.default_mclk =
0167             radeon_legacy_get_memory_clock(rdev);
0168 
0169     DRM_INFO("Using device-tree clock info\n");
0170 
0171     return true;
0172 }
0173 #else
0174 static bool radeon_read_clocks_OF(struct drm_device *dev)
0175 {
0176     return false;
0177 }
0178 #endif /* CONFIG_OF */
0179 
0180 void radeon_get_clock_info(struct drm_device *dev)
0181 {
0182     struct radeon_device *rdev = dev->dev_private;
0183     struct radeon_pll *p1pll = &rdev->clock.p1pll;
0184     struct radeon_pll *p2pll = &rdev->clock.p2pll;
0185     struct radeon_pll *dcpll = &rdev->clock.dcpll;
0186     struct radeon_pll *spll = &rdev->clock.spll;
0187     struct radeon_pll *mpll = &rdev->clock.mpll;
0188     int ret;
0189 
0190     if (rdev->is_atom_bios)
0191         ret = radeon_atom_get_clock_info(dev);
0192     else
0193         ret = radeon_combios_get_clock_info(dev);
0194     if (!ret)
0195         ret = radeon_read_clocks_OF(dev);
0196 
0197     if (ret) {
0198         if (p1pll->reference_div < 2) {
0199             if (!ASIC_IS_AVIVO(rdev)) {
0200                 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);
0201                 if (ASIC_IS_R300(rdev))
0202                     p1pll->reference_div =
0203                         (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
0204                 else
0205                     p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
0206                 if (p1pll->reference_div < 2)
0207                     p1pll->reference_div = 12;
0208             } else
0209                 p1pll->reference_div = 12;
0210         }
0211         if (p2pll->reference_div < 2)
0212             p2pll->reference_div = 12;
0213         if (rdev->family < CHIP_RS600) {
0214             if (spll->reference_div < 2)
0215                 spll->reference_div =
0216                     RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
0217                     RADEON_M_SPLL_REF_DIV_MASK;
0218         }
0219         if (mpll->reference_div < 2)
0220             mpll->reference_div = spll->reference_div;
0221     } else {
0222         if (ASIC_IS_AVIVO(rdev)) {
0223             /* TODO FALLBACK */
0224         } else {
0225             DRM_INFO("Using generic clock info\n");
0226 
0227             /* may need to be per card */
0228             rdev->clock.max_pixel_clock = 35000;
0229 
0230             if (rdev->flags & RADEON_IS_IGP) {
0231                 p1pll->reference_freq = 1432;
0232                 p2pll->reference_freq = 1432;
0233                 spll->reference_freq = 1432;
0234                 mpll->reference_freq = 1432;
0235             } else {
0236                 p1pll->reference_freq = 2700;
0237                 p2pll->reference_freq = 2700;
0238                 spll->reference_freq = 2700;
0239                 mpll->reference_freq = 2700;
0240             }
0241             p1pll->reference_div =
0242                 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
0243             if (p1pll->reference_div < 2)
0244                 p1pll->reference_div = 12;
0245             p2pll->reference_div = p1pll->reference_div;
0246 
0247             if (rdev->family >= CHIP_R420) {
0248                 p1pll->pll_in_min = 100;
0249                 p1pll->pll_in_max = 1350;
0250                 p1pll->pll_out_min = 20000;
0251                 p1pll->pll_out_max = 50000;
0252                 p2pll->pll_in_min = 100;
0253                 p2pll->pll_in_max = 1350;
0254                 p2pll->pll_out_min = 20000;
0255                 p2pll->pll_out_max = 50000;
0256             } else {
0257                 p1pll->pll_in_min = 40;
0258                 p1pll->pll_in_max = 500;
0259                 p1pll->pll_out_min = 12500;
0260                 p1pll->pll_out_max = 35000;
0261                 p2pll->pll_in_min = 40;
0262                 p2pll->pll_in_max = 500;
0263                 p2pll->pll_out_min = 12500;
0264                 p2pll->pll_out_max = 35000;
0265             }
0266 
0267             spll->reference_div =
0268                 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
0269                 RADEON_M_SPLL_REF_DIV_MASK;
0270             mpll->reference_div = spll->reference_div;
0271             rdev->clock.default_sclk =
0272                 radeon_legacy_get_engine_clock(rdev);
0273             rdev->clock.default_mclk =
0274                 radeon_legacy_get_memory_clock(rdev);
0275         }
0276     }
0277 
0278     /* pixel clocks */
0279     if (ASIC_IS_AVIVO(rdev)) {
0280         p1pll->min_post_div = 2;
0281         p1pll->max_post_div = 0x7f;
0282         p1pll->min_frac_feedback_div = 0;
0283         p1pll->max_frac_feedback_div = 9;
0284         p2pll->min_post_div = 2;
0285         p2pll->max_post_div = 0x7f;
0286         p2pll->min_frac_feedback_div = 0;
0287         p2pll->max_frac_feedback_div = 9;
0288     } else {
0289         p1pll->min_post_div = 1;
0290         p1pll->max_post_div = 16;
0291         p1pll->min_frac_feedback_div = 0;
0292         p1pll->max_frac_feedback_div = 0;
0293         p2pll->min_post_div = 1;
0294         p2pll->max_post_div = 12;
0295         p2pll->min_frac_feedback_div = 0;
0296         p2pll->max_frac_feedback_div = 0;
0297     }
0298 
0299     /* dcpll is DCE4 only */
0300     dcpll->min_post_div = 2;
0301     dcpll->max_post_div = 0x7f;
0302     dcpll->min_frac_feedback_div = 0;
0303     dcpll->max_frac_feedback_div = 9;
0304     dcpll->min_ref_div = 2;
0305     dcpll->max_ref_div = 0x3ff;
0306     dcpll->min_feedback_div = 4;
0307     dcpll->max_feedback_div = 0xfff;
0308     dcpll->best_vco = 0;
0309 
0310     p1pll->min_ref_div = 2;
0311     p1pll->max_ref_div = 0x3ff;
0312     p1pll->min_feedback_div = 4;
0313     p1pll->max_feedback_div = 0x7ff;
0314     p1pll->best_vco = 0;
0315 
0316     p2pll->min_ref_div = 2;
0317     p2pll->max_ref_div = 0x3ff;
0318     p2pll->min_feedback_div = 4;
0319     p2pll->max_feedback_div = 0x7ff;
0320     p2pll->best_vco = 0;
0321 
0322     /* system clock */
0323     spll->min_post_div = 1;
0324     spll->max_post_div = 1;
0325     spll->min_ref_div = 2;
0326     spll->max_ref_div = 0xff;
0327     spll->min_feedback_div = 4;
0328     spll->max_feedback_div = 0xff;
0329     spll->best_vco = 0;
0330 
0331     /* memory clock */
0332     mpll->min_post_div = 1;
0333     mpll->max_post_div = 1;
0334     mpll->min_ref_div = 2;
0335     mpll->max_ref_div = 0xff;
0336     mpll->min_feedback_div = 4;
0337     mpll->max_feedback_div = 0xff;
0338     mpll->best_vco = 0;
0339 
0340     if (!rdev->clock.default_sclk)
0341         rdev->clock.default_sclk = radeon_get_engine_clock(rdev);
0342     if ((!rdev->clock.default_mclk) && rdev->asic->pm.get_memory_clock)
0343         rdev->clock.default_mclk = radeon_get_memory_clock(rdev);
0344 
0345     rdev->pm.current_sclk = rdev->clock.default_sclk;
0346     rdev->pm.current_mclk = rdev->clock.default_mclk;
0347 
0348 }
0349 
0350 /* 10 khz */
0351 static uint32_t calc_eng_mem_clock(struct radeon_device *rdev,
0352                    uint32_t req_clock,
0353                    int *fb_div, int *post_div)
0354 {
0355     struct radeon_pll *spll = &rdev->clock.spll;
0356     int ref_div = spll->reference_div;
0357 
0358     if (!ref_div)
0359         ref_div =
0360             RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
0361             RADEON_M_SPLL_REF_DIV_MASK;
0362 
0363     if (req_clock < 15000) {
0364         *post_div = 8;
0365         req_clock *= 8;
0366     } else if (req_clock < 30000) {
0367         *post_div = 4;
0368         req_clock *= 4;
0369     } else if (req_clock < 60000) {
0370         *post_div = 2;
0371         req_clock *= 2;
0372     } else
0373         *post_div = 1;
0374 
0375     req_clock *= ref_div;
0376     req_clock += spll->reference_freq;
0377     req_clock /= (2 * spll->reference_freq);
0378 
0379     *fb_div = req_clock & 0xff;
0380 
0381     req_clock = (req_clock & 0xffff) << 1;
0382     req_clock *= spll->reference_freq;
0383     req_clock /= ref_div;
0384     req_clock /= *post_div;
0385 
0386     return req_clock;
0387 }
0388 
0389 /* 10 khz */
0390 void radeon_legacy_set_engine_clock(struct radeon_device *rdev,
0391                     uint32_t eng_clock)
0392 {
0393     uint32_t tmp;
0394     int fb_div, post_div;
0395 
0396     /* XXX: wait for idle */
0397 
0398     eng_clock = calc_eng_mem_clock(rdev, eng_clock, &fb_div, &post_div);
0399 
0400     tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
0401     tmp &= ~RADEON_DONT_USE_XTALIN;
0402     WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
0403 
0404     tmp = RREG32_PLL(RADEON_SCLK_CNTL);
0405     tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
0406     WREG32_PLL(RADEON_SCLK_CNTL, tmp);
0407 
0408     udelay(10);
0409 
0410     tmp = RREG32_PLL(RADEON_SPLL_CNTL);
0411     tmp |= RADEON_SPLL_SLEEP;
0412     WREG32_PLL(RADEON_SPLL_CNTL, tmp);
0413 
0414     udelay(2);
0415 
0416     tmp = RREG32_PLL(RADEON_SPLL_CNTL);
0417     tmp |= RADEON_SPLL_RESET;
0418     WREG32_PLL(RADEON_SPLL_CNTL, tmp);
0419 
0420     udelay(200);
0421 
0422     tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
0423     tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT);
0424     tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT;
0425     WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp);
0426 
0427     /* XXX: verify on different asics */
0428     tmp = RREG32_PLL(RADEON_SPLL_CNTL);
0429     tmp &= ~RADEON_SPLL_PVG_MASK;
0430     if ((eng_clock * post_div) >= 90000)
0431         tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT);
0432     else
0433         tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT);
0434     WREG32_PLL(RADEON_SPLL_CNTL, tmp);
0435 
0436     tmp = RREG32_PLL(RADEON_SPLL_CNTL);
0437     tmp &= ~RADEON_SPLL_SLEEP;
0438     WREG32_PLL(RADEON_SPLL_CNTL, tmp);
0439 
0440     udelay(2);
0441 
0442     tmp = RREG32_PLL(RADEON_SPLL_CNTL);
0443     tmp &= ~RADEON_SPLL_RESET;
0444     WREG32_PLL(RADEON_SPLL_CNTL, tmp);
0445 
0446     udelay(200);
0447 
0448     tmp = RREG32_PLL(RADEON_SCLK_CNTL);
0449     tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
0450     switch (post_div) {
0451     case 1:
0452     default:
0453         tmp |= 1;
0454         break;
0455     case 2:
0456         tmp |= 2;
0457         break;
0458     case 4:
0459         tmp |= 3;
0460         break;
0461     case 8:
0462         tmp |= 4;
0463         break;
0464     }
0465     WREG32_PLL(RADEON_SCLK_CNTL, tmp);
0466 
0467     udelay(20);
0468 
0469     tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
0470     tmp |= RADEON_DONT_USE_XTALIN;
0471     WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
0472 
0473     udelay(10);
0474 }
0475 
0476 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
0477 {
0478     uint32_t tmp;
0479 
0480     if (enable) {
0481         if (rdev->flags & RADEON_SINGLE_CRTC) {
0482             tmp = RREG32_PLL(RADEON_SCLK_CNTL);
0483             if ((RREG32(RADEON_CONFIG_CNTL) &
0484                  RADEON_CFG_ATI_REV_ID_MASK) >
0485                 RADEON_CFG_ATI_REV_A13) {
0486                 tmp &=
0487                     ~(RADEON_SCLK_FORCE_CP |
0488                       RADEON_SCLK_FORCE_RB);
0489             }
0490             tmp &=
0491                 ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
0492                   RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE |
0493                   RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE |
0494                   RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM |
0495                   RADEON_SCLK_FORCE_TDM);
0496             WREG32_PLL(RADEON_SCLK_CNTL, tmp);
0497         } else if (ASIC_IS_R300(rdev)) {
0498             if ((rdev->family == CHIP_RS400) ||
0499                 (rdev->family == CHIP_RS480)) {
0500                 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
0501                 tmp &=
0502                     ~(RADEON_SCLK_FORCE_DISP2 |
0503                       RADEON_SCLK_FORCE_CP |
0504                       RADEON_SCLK_FORCE_HDP |
0505                       RADEON_SCLK_FORCE_DISP1 |
0506                       RADEON_SCLK_FORCE_TOP |
0507                       RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP
0508                       | RADEON_SCLK_FORCE_IDCT |
0509                       RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR
0510                       | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX
0511                       | R300_SCLK_FORCE_US |
0512                       RADEON_SCLK_FORCE_TV_SCLK |
0513                       R300_SCLK_FORCE_SU |
0514                       RADEON_SCLK_FORCE_OV0);
0515                 tmp |= RADEON_DYN_STOP_LAT_MASK;
0516                 tmp |=
0517                     RADEON_SCLK_FORCE_TOP |
0518                     RADEON_SCLK_FORCE_VIP;
0519                 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
0520 
0521                 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
0522                 tmp &= ~RADEON_SCLK_MORE_FORCEON;
0523                 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
0524                 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
0525 
0526                 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
0527                 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
0528                     RADEON_PIXCLK_DAC_ALWAYS_ONb);
0529                 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
0530 
0531                 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
0532                 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
0533                     RADEON_PIX2CLK_DAC_ALWAYS_ONb |
0534                     RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
0535                     R300_DVOCLK_ALWAYS_ONb |
0536                     RADEON_PIXCLK_BLEND_ALWAYS_ONb |
0537                     RADEON_PIXCLK_GV_ALWAYS_ONb |
0538                     R300_PIXCLK_DVO_ALWAYS_ONb |
0539                     RADEON_PIXCLK_LVDS_ALWAYS_ONb |
0540                     RADEON_PIXCLK_TMDS_ALWAYS_ONb |
0541                     R300_PIXCLK_TRANS_ALWAYS_ONb |
0542                     R300_PIXCLK_TVO_ALWAYS_ONb |
0543                     R300_P2G2CLK_ALWAYS_ONb |
0544                     R300_P2G2CLK_DAC_ALWAYS_ONb);
0545                 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
0546             } else if (rdev->family >= CHIP_RV350) {
0547                 tmp = RREG32_PLL(R300_SCLK_CNTL2);
0548                 tmp &= ~(R300_SCLK_FORCE_TCL |
0549                      R300_SCLK_FORCE_GA |
0550                      R300_SCLK_FORCE_CBA);
0551                 tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT |
0552                     R300_SCLK_GA_MAX_DYN_STOP_LAT |
0553                     R300_SCLK_CBA_MAX_DYN_STOP_LAT);
0554                 WREG32_PLL(R300_SCLK_CNTL2, tmp);
0555 
0556                 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
0557                 tmp &=
0558                     ~(RADEON_SCLK_FORCE_DISP2 |
0559                       RADEON_SCLK_FORCE_CP |
0560                       RADEON_SCLK_FORCE_HDP |
0561                       RADEON_SCLK_FORCE_DISP1 |
0562                       RADEON_SCLK_FORCE_TOP |
0563                       RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP
0564                       | RADEON_SCLK_FORCE_IDCT |
0565                       RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR
0566                       | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX
0567                       | R300_SCLK_FORCE_US |
0568                       RADEON_SCLK_FORCE_TV_SCLK |
0569                       R300_SCLK_FORCE_SU |
0570                       RADEON_SCLK_FORCE_OV0);
0571                 tmp |= RADEON_DYN_STOP_LAT_MASK;
0572                 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
0573 
0574                 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
0575                 tmp &= ~RADEON_SCLK_MORE_FORCEON;
0576                 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
0577                 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
0578 
0579                 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
0580                 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
0581                     RADEON_PIXCLK_DAC_ALWAYS_ONb);
0582                 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
0583 
0584                 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
0585                 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
0586                     RADEON_PIX2CLK_DAC_ALWAYS_ONb |
0587                     RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
0588                     R300_DVOCLK_ALWAYS_ONb |
0589                     RADEON_PIXCLK_BLEND_ALWAYS_ONb |
0590                     RADEON_PIXCLK_GV_ALWAYS_ONb |
0591                     R300_PIXCLK_DVO_ALWAYS_ONb |
0592                     RADEON_PIXCLK_LVDS_ALWAYS_ONb |
0593                     RADEON_PIXCLK_TMDS_ALWAYS_ONb |
0594                     R300_PIXCLK_TRANS_ALWAYS_ONb |
0595                     R300_PIXCLK_TVO_ALWAYS_ONb |
0596                     R300_P2G2CLK_ALWAYS_ONb |
0597                     R300_P2G2CLK_DAC_ALWAYS_ONb);
0598                 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
0599 
0600                 tmp = RREG32_PLL(RADEON_MCLK_MISC);
0601                 tmp |= (RADEON_MC_MCLK_DYN_ENABLE |
0602                     RADEON_IO_MCLK_DYN_ENABLE);
0603                 WREG32_PLL(RADEON_MCLK_MISC, tmp);
0604 
0605                 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
0606                 tmp |= (RADEON_FORCEON_MCLKA |
0607                     RADEON_FORCEON_MCLKB);
0608 
0609                 tmp &= ~(RADEON_FORCEON_YCLKA |
0610                      RADEON_FORCEON_YCLKB |
0611                      RADEON_FORCEON_MC);
0612 
0613                 /* Some releases of vbios have set DISABLE_MC_MCLKA
0614                    and DISABLE_MC_MCLKB bits in the vbios table.  Setting these
0615                    bits will cause H/W hang when reading video memory with dynamic clocking
0616                    enabled. */
0617                 if ((tmp & R300_DISABLE_MC_MCLKA) &&
0618                     (tmp & R300_DISABLE_MC_MCLKB)) {
0619                     /* If both bits are set, then check the active channels */
0620                     tmp = RREG32_PLL(RADEON_MCLK_CNTL);
0621                     if (rdev->mc.vram_width == 64) {
0622                         if (RREG32(RADEON_MEM_CNTL) &
0623                             R300_MEM_USE_CD_CH_ONLY)
0624                             tmp &=
0625                                 ~R300_DISABLE_MC_MCLKB;
0626                         else
0627                             tmp &=
0628                                 ~R300_DISABLE_MC_MCLKA;
0629                     } else {
0630                         tmp &= ~(R300_DISABLE_MC_MCLKA |
0631                              R300_DISABLE_MC_MCLKB);
0632                     }
0633                 }
0634 
0635                 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
0636             } else {
0637                 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
0638                 tmp &= ~(R300_SCLK_FORCE_VAP);
0639                 tmp |= RADEON_SCLK_FORCE_CP;
0640                 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
0641                 mdelay(15);
0642 
0643                 tmp = RREG32_PLL(R300_SCLK_CNTL2);
0644                 tmp &= ~(R300_SCLK_FORCE_TCL |
0645                      R300_SCLK_FORCE_GA |
0646                      R300_SCLK_FORCE_CBA);
0647                 WREG32_PLL(R300_SCLK_CNTL2, tmp);
0648             }
0649         } else {
0650             tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
0651 
0652             tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK |
0653                  RADEON_DISP_DYN_STOP_LAT_MASK |
0654                  RADEON_DYN_STOP_MODE_MASK);
0655 
0656             tmp |= (RADEON_ENGIN_DYNCLK_MODE |
0657                 (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT));
0658             WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);
0659             mdelay(15);
0660 
0661             tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
0662             tmp |= RADEON_SCLK_DYN_START_CNTL;
0663             WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
0664             mdelay(15);
0665 
0666             /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
0667                to lockup randomly, leave them as set by BIOS.
0668              */
0669             tmp = RREG32_PLL(RADEON_SCLK_CNTL);
0670             /*tmp &= RADEON_SCLK_SRC_SEL_MASK; */
0671             tmp &= ~RADEON_SCLK_FORCEON_MASK;
0672 
0673             /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300 */
0674             if (((rdev->family == CHIP_RV250) &&
0675                  ((RREG32(RADEON_CONFIG_CNTL) &
0676                    RADEON_CFG_ATI_REV_ID_MASK) <
0677                   RADEON_CFG_ATI_REV_A13))
0678                 || ((rdev->family == CHIP_RV100)
0679                 &&
0680                 ((RREG32(RADEON_CONFIG_CNTL) &
0681                   RADEON_CFG_ATI_REV_ID_MASK) <=
0682                  RADEON_CFG_ATI_REV_A13))) {
0683                 tmp |= RADEON_SCLK_FORCE_CP;
0684                 tmp |= RADEON_SCLK_FORCE_VIP;
0685             }
0686 
0687             WREG32_PLL(RADEON_SCLK_CNTL, tmp);
0688 
0689             if ((rdev->family == CHIP_RV200) ||
0690                 (rdev->family == CHIP_RV250) ||
0691                 (rdev->family == CHIP_RV280)) {
0692                 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
0693                 tmp &= ~RADEON_SCLK_MORE_FORCEON;
0694 
0695                 /* RV200::A11 A12 RV250::A11 A12 */
0696                 if (((rdev->family == CHIP_RV200) ||
0697                      (rdev->family == CHIP_RV250)) &&
0698                     ((RREG32(RADEON_CONFIG_CNTL) &
0699                       RADEON_CFG_ATI_REV_ID_MASK) <
0700                      RADEON_CFG_ATI_REV_A13)) {
0701                     tmp |= RADEON_SCLK_MORE_FORCEON;
0702                 }
0703                 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
0704                 mdelay(15);
0705             }
0706 
0707             /* RV200::A11 A12, RV250::A11 A12 */
0708             if (((rdev->family == CHIP_RV200) ||
0709                  (rdev->family == CHIP_RV250)) &&
0710                 ((RREG32(RADEON_CONFIG_CNTL) &
0711                   RADEON_CFG_ATI_REV_ID_MASK) <
0712                  RADEON_CFG_ATI_REV_A13)) {
0713                 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
0714                 tmp |= RADEON_TCL_BYPASS_DISABLE;
0715                 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
0716             }
0717             mdelay(15);
0718 
0719             /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */
0720             tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
0721             tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
0722                 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
0723                 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
0724                 RADEON_PIXCLK_GV_ALWAYS_ONb |
0725                 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
0726                 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
0727                 RADEON_PIXCLK_TMDS_ALWAYS_ONb);
0728 
0729             WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
0730             mdelay(15);
0731 
0732             tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
0733             tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
0734                 RADEON_PIXCLK_DAC_ALWAYS_ONb);
0735 
0736             WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
0737             mdelay(15);
0738         }
0739     } else {
0740         /* Turn everything OFF (ForceON to everything) */
0741         if (rdev->flags & RADEON_SINGLE_CRTC) {
0742             tmp = RREG32_PLL(RADEON_SCLK_CNTL);
0743             tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP |
0744                 RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP
0745                 | RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE |
0746                 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP |
0747                 RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB |
0748                 RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM |
0749                 RADEON_SCLK_FORCE_RB);
0750             WREG32_PLL(RADEON_SCLK_CNTL, tmp);
0751         } else if ((rdev->family == CHIP_RS400) ||
0752                (rdev->family == CHIP_RS480)) {
0753             tmp = RREG32_PLL(RADEON_SCLK_CNTL);
0754             tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
0755                 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1
0756                 | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
0757                 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
0758                 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
0759                 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
0760                 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
0761                 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
0762             WREG32_PLL(RADEON_SCLK_CNTL, tmp);
0763 
0764             tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
0765             tmp |= RADEON_SCLK_MORE_FORCEON;
0766             WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
0767 
0768             tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
0769             tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
0770                  RADEON_PIXCLK_DAC_ALWAYS_ONb |
0771                  R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
0772             WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
0773 
0774             tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
0775             tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
0776                  RADEON_PIX2CLK_DAC_ALWAYS_ONb |
0777                  RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
0778                  R300_DVOCLK_ALWAYS_ONb |
0779                  RADEON_PIXCLK_BLEND_ALWAYS_ONb |
0780                  RADEON_PIXCLK_GV_ALWAYS_ONb |
0781                  R300_PIXCLK_DVO_ALWAYS_ONb |
0782                  RADEON_PIXCLK_LVDS_ALWAYS_ONb |
0783                  RADEON_PIXCLK_TMDS_ALWAYS_ONb |
0784                  R300_PIXCLK_TRANS_ALWAYS_ONb |
0785                  R300_PIXCLK_TVO_ALWAYS_ONb |
0786                  R300_P2G2CLK_ALWAYS_ONb |
0787                  R300_P2G2CLK_DAC_ALWAYS_ONb |
0788                  R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
0789             WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
0790         } else if (rdev->family >= CHIP_RV350) {
0791             /* for RV350/M10, no delays are required. */
0792             tmp = RREG32_PLL(R300_SCLK_CNTL2);
0793             tmp |= (R300_SCLK_FORCE_TCL |
0794                 R300_SCLK_FORCE_GA | R300_SCLK_FORCE_CBA);
0795             WREG32_PLL(R300_SCLK_CNTL2, tmp);
0796 
0797             tmp = RREG32_PLL(RADEON_SCLK_CNTL);
0798             tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
0799                 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1
0800                 | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
0801                 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
0802                 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
0803                 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
0804                 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
0805                 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
0806             WREG32_PLL(RADEON_SCLK_CNTL, tmp);
0807 
0808             tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
0809             tmp |= RADEON_SCLK_MORE_FORCEON;
0810             WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
0811 
0812             tmp = RREG32_PLL(RADEON_MCLK_CNTL);
0813             tmp |= (RADEON_FORCEON_MCLKA |
0814                 RADEON_FORCEON_MCLKB |
0815                 RADEON_FORCEON_YCLKA |
0816                 RADEON_FORCEON_YCLKB | RADEON_FORCEON_MC);
0817             WREG32_PLL(RADEON_MCLK_CNTL, tmp);
0818 
0819             tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
0820             tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
0821                  RADEON_PIXCLK_DAC_ALWAYS_ONb |
0822                  R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
0823             WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
0824 
0825             tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
0826             tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
0827                  RADEON_PIX2CLK_DAC_ALWAYS_ONb |
0828                  RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
0829                  R300_DVOCLK_ALWAYS_ONb |
0830                  RADEON_PIXCLK_BLEND_ALWAYS_ONb |
0831                  RADEON_PIXCLK_GV_ALWAYS_ONb |
0832                  R300_PIXCLK_DVO_ALWAYS_ONb |
0833                  RADEON_PIXCLK_LVDS_ALWAYS_ONb |
0834                  RADEON_PIXCLK_TMDS_ALWAYS_ONb |
0835                  R300_PIXCLK_TRANS_ALWAYS_ONb |
0836                  R300_PIXCLK_TVO_ALWAYS_ONb |
0837                  R300_P2G2CLK_ALWAYS_ONb |
0838                  R300_P2G2CLK_DAC_ALWAYS_ONb |
0839                  R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
0840             WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
0841         } else {
0842             tmp = RREG32_PLL(RADEON_SCLK_CNTL);
0843             tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2);
0844             tmp |= RADEON_SCLK_FORCE_SE;
0845 
0846             if (rdev->flags & RADEON_SINGLE_CRTC) {
0847                 tmp |= (RADEON_SCLK_FORCE_RB |
0848                     RADEON_SCLK_FORCE_TDM |
0849                     RADEON_SCLK_FORCE_TAM |
0850                     RADEON_SCLK_FORCE_PB |
0851                     RADEON_SCLK_FORCE_RE |
0852                     RADEON_SCLK_FORCE_VIP |
0853                     RADEON_SCLK_FORCE_IDCT |
0854                     RADEON_SCLK_FORCE_TOP |
0855                     RADEON_SCLK_FORCE_DISP1 |
0856                     RADEON_SCLK_FORCE_DISP2 |
0857                     RADEON_SCLK_FORCE_HDP);
0858             } else if ((rdev->family == CHIP_R300) ||
0859                    (rdev->family == CHIP_R350)) {
0860                 tmp |= (RADEON_SCLK_FORCE_HDP |
0861                     RADEON_SCLK_FORCE_DISP1 |
0862                     RADEON_SCLK_FORCE_DISP2 |
0863                     RADEON_SCLK_FORCE_TOP |
0864                     RADEON_SCLK_FORCE_IDCT |
0865                     RADEON_SCLK_FORCE_VIP);
0866             }
0867             WREG32_PLL(RADEON_SCLK_CNTL, tmp);
0868 
0869             mdelay(16);
0870 
0871             if ((rdev->family == CHIP_R300) ||
0872                 (rdev->family == CHIP_R350)) {
0873                 tmp = RREG32_PLL(R300_SCLK_CNTL2);
0874                 tmp |= (R300_SCLK_FORCE_TCL |
0875                     R300_SCLK_FORCE_GA |
0876                     R300_SCLK_FORCE_CBA);
0877                 WREG32_PLL(R300_SCLK_CNTL2, tmp);
0878                 mdelay(16);
0879             }
0880 
0881             if (rdev->flags & RADEON_IS_IGP) {
0882                 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
0883                 tmp &= ~(RADEON_FORCEON_MCLKA |
0884                      RADEON_FORCEON_YCLKA);
0885                 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
0886                 mdelay(16);
0887             }
0888 
0889             if ((rdev->family == CHIP_RV200) ||
0890                 (rdev->family == CHIP_RV250) ||
0891                 (rdev->family == CHIP_RV280)) {
0892                 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
0893                 tmp |= RADEON_SCLK_MORE_FORCEON;
0894                 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
0895                 mdelay(16);
0896             }
0897 
0898             tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
0899             tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
0900                  RADEON_PIX2CLK_DAC_ALWAYS_ONb |
0901                  RADEON_PIXCLK_BLEND_ALWAYS_ONb |
0902                  RADEON_PIXCLK_GV_ALWAYS_ONb |
0903                  RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
0904                  RADEON_PIXCLK_LVDS_ALWAYS_ONb |
0905                  RADEON_PIXCLK_TMDS_ALWAYS_ONb);
0906 
0907             WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
0908             mdelay(16);
0909 
0910             tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
0911             tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
0912                  RADEON_PIXCLK_DAC_ALWAYS_ONb);
0913             WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
0914         }
0915     }
0916 }
0917
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